EESchema Schematic File Version 2 date Sun 22 Aug 2010 07:03:34 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 LIBS:usb-48204-0001 LIBS:microsmd075f LIBS:mic2550 LIBS:rj45-48025 LIBS:xue-nv LIBS:xc6slx75fgg484 LIBS:xc6slx45fgg484 LIBS:micron_mobile_ddr LIBS:micron_ddr_512Mb LIBS:k8001 LIBS:device LIBS:transistors LIBS:conn LIBS:linear LIBS:regul LIBS:74xx LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx LIBS:special LIBS:microcontrollers LIBS:dsp LIBS:microchip LIBS:analog_switches LIBS:motorola LIBS:texas LIBS:intel LIBS:audio LIBS:interface LIBS:digital-audio LIBS:philips LIBS:display LIBS:cypress LIBS:siliconi LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves LIBS:pasives-connectors LIBS:x25x64mb LIBS:attiny LIBS:PSU LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 1 8 Title "" Date "23 aug 2010" Rev "" Comp "" Comment1 "" Comment2 "" Comment3 "" Comment4 "" $EndDescr Wire Wire Line 5950 8150 4950 8150 Wire Wire Line 5950 7950 4950 7950 Wire Wire Line 10650 4400 9300 4400 Wire Wire Line 10650 4300 9300 4300 Wire Wire Line 10650 3950 9300 3950 Wire Wire Line 10650 3750 9300 3750 Wire Wire Line 10650 3650 9300 3650 Wire Bus Line 10650 4050 9300 4050 Wire Wire Line 10600 6700 9300 6700 Wire Wire Line 9300 3000 10650 3000 Wire Bus Line 10600 7200 9300 7200 Wire Bus Line 9300 7600 10600 7600 Wire Wire Line 10650 5750 9300 5750 Wire Wire Line 10650 5550 9300 5550 Wire Wire Line 9300 7900 10600 7900 Wire Wire Line 9300 7700 10600 7700 Wire Wire Line 9300 7500 10600 7500 Wire Wire Line 9300 7300 10600 7300 Wire Wire Line 9300 7000 10600 7000 Wire Wire Line 9300 6600 10600 6600 Wire Wire Line 9300 6350 10600 6350 Wire Bus Line 4700 2950 5950 2950 Wire Wire Line 4700 3350 5950 3350 Wire Wire Line 4700 3450 5950 3450 Wire Wire Line 4700 3650 5950 3650 Wire Wire Line 4700 4500 5950 4500 Wire Wire Line 4700 4350 5950 4350 Wire Wire Line 4700 4900 5950 4900 Wire Wire Line 4700 6400 5950 6400 Wire Wire Line 4700 5500 5950 5500 Wire Wire Line 4700 5800 5950 5800 Wire Bus Line 4700 5150 5950 5150 Wire Wire Line 4700 4000 5950 4000 Wire Wire Line 4700 6050 5950 6050 Wire Bus Line 4700 5050 5950 5050 Wire Bus Line 5950 5050 5950 5100 Wire Wire Line 4700 6150 5950 6150 Wire Wire Line 5950 4100 4700 4100 Wire Bus Line 4700 3050 5950 3050 Wire Wire Line 4700 5400 5950 5400 Wire Wire Line 4700 5700 5950 5700 Wire Wire Line 4700 6300 5950 6300 Wire Bus Line 4700 5250 5950 5250 Wire Wire Line 4700 6550 5950 6550 Wire Wire Line 4700 5950 5950 5950 Wire Wire Line 4700 4250 5950 4250 Wire Wire Line 4700 3900 5950 3900 Wire Wire Line 4700 3750 5950 3750 Wire Wire Line 4700 2800 5950 2800 Wire Bus Line 4700 3150 5950 3150 Wire Wire Line 9300 6500 10600 6500 Wire Wire Line 10600 6900 9300 6900 Wire Wire Line 9300 7400 10600 7400 Wire Wire Line 9300 7800 10600 7800 Wire Wire Line 10650 5450 9300 5450 Wire Wire Line 10650 5650 9300 5650 Wire Wire Line 10650 5850 9300 5850 Wire Wire Line 9300 2900 10650 2900 Wire Bus Line 9300 3100 10650 3100 Wire Wire Line 10600 6800 9300 6800 Wire Wire Line 9300 3550 10650 3550 Wire Wire Line 10650 3850 9300 3850 Wire Wire Line 10650 3450 9300 3450 Wire Bus Line 10650 4500 9300 4500 Wire Wire Line 5950 7850 4950 7850 Wire Wire Line 4950 8050 5950 8050 $Sheet S 3750 7800 1200 700 U 4C716A4D F0 "DBG_PRG" 60 F1 "DBG_PRG.sch" 60 F2 "FPGA_TDO" B R 4950 8050 60 F3 "FPGA_TDI" B R 4950 7950 60 F4 "FPGA_TMS" B R 4950 8150 60 F5 "FPGA_TCK" B R 4950 7850 60 $EndSheet $Sheet S 10750 8650 1100 1300 U 4C69ED5F F0 "PSU" 60 F1 "PSU.sch" 60 $EndSheet $Sheet S 10650 2700 1050 1950 U 4C4227FE F0 "Non volatile memories" 60 F1 "NV_MEMORIES.sch" 60 F2 "SD_CMD" I L 10650 3000 60 F3 "SD_CLK" I L 10650 2900 60 F4 "SD_DAT[0..3]" B L 10650 3100 60 F5 "NF_D[0..7]" B L 10650 4050 60 F6 "NF_ALE" B L 10650 3550 60 F7 "NF_CLE" B L 10650 3650 60 F8 "NF_WE_N" B L 10650 3750 60 F9 "NF_CS1_N" B L 10650 3450 60 F10 "NF_RE_N" B L 10650 3850 60 F11 "NF_RNB" B L 10650 3950 60 F12 "SPI_CLK" I L 10650 4400 60 F13 "SPI_FLASH_CS#" I L 10650 4300 60 F14 "SPI_DQ[0..3]" B L 10650 4500 60 $EndSheet $Sheet S 10650 5250 1150 750 U 4C5F1EDC F0 "USB" 60 F1 "USB.sch" 60 F2 "USBA_SPD" B L 10650 5450 60 F3 "USBA_OE_N" B L 10650 5550 60 F4 "USBA_RCV" B L 10650 5650 60 F5 "USBA_VP" B L 10650 5750 60 F6 "USBA_VM" B L 10650 5850 60 $EndSheet Text Notes 12850 10750 0 60 ~ 0 Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com $Sheet S 5950 2700 3350 5800 U 4C431A63 F0 "FPGA Spartan6" 60 F1 "FPGA.sch" 60 F2 "M1_CLK" O L 5950 4000 60 F3 "M1_CLK#" O L 5950 4100 60 F4 "M0_CLK" O L 5950 6050 60 F5 "M0_CLK#" O L 5950 6150 60 F6 "M0_A[0..12]" O L 5950 5150 60 F7 "M1_A[0..12]" O L 5950 3050 60 F8 "M0_DQ[0..15]" B L 5950 5050 60 F9 "M0_UDQS" O L 5950 5400 60 F10 "M0_LDM" O L 5950 5800 60 F11 "M0_LDQS" O L 5950 5500 60 F12 "M0_UDM" O L 5950 5700 60 F13 "M0_RAS#" O L 5950 6400 60 F14 "M0_WE#" O L 5950 6550 60 F15 "M0_CKE" O L 5950 5950 60 F16 "M0_CAS#" O L 5950 6300 60 F17 "M1_CAS#" O L 5950 4250 60 F18 "M1_CKE" O L 5950 3900 60 F19 "M0_CS#" O L 5950 4900 60 F20 "M1_CS#" O L 5950 2800 60 F21 "M1_WE#" O L 5950 4500 60 F22 "M1_RAS#" O L 5950 4350 60 F23 "M1_UDM" O L 5950 3650 60 F24 "M1_LDQS" O L 5950 3450 60 F25 "M1_LDM" O L 5950 3750 60 F26 "M1_UDQS" O L 5950 3350 60 F27 "M1_DQ[0..15]" B L 5950 2950 60 F28 "M1_BA[0..1]" O L 5950 3150 60 F29 "M0_BA[0..1]" O L 5950 5250 60 F30 "USBA_VM" B R 9300 5850 60 F31 "USBA_VP" B R 9300 5750 60 F32 "USBA_RCV" B R 9300 5650 60 F33 "USBA_OE_N" B R 9300 5550 60 F34 "USBA_SPD" B R 9300 5450 60 F35 "ETH_CLK" B R 9300 7900 60 F36 "ETH_RXC" B R 9300 6500 60 F37 "ETH_TXC" B R 9300 7500 60 F38 "ETH_TXD[0..3]" O R 9300 7600 60 F39 "ETH_TXEN" B R 9300 7700 60 F40 "ETH_TXER" B R 9300 7800 60 F41 "ETH_RXER" B R 9300 7400 60 F42 "ETH_RXDV" B R 9300 7300 60 F43 "ETH_RXD[0..3]" I R 9300 7200 60 F44 "ETH_RESET_N" B R 9300 6600 60 F45 "ETH_MDIO" B R 9300 6900 60 F46 "ETH_MDC" B R 9300 7000 60 F47 "ETH_INT" B R 9300 6350 60 F48 "SD_CLK" B R 9300 2900 60 F49 "SD_CMD" B R 9300 3000 60 F50 "SD_DAT[0..3]" B R 9300 3100 60 F51 "ETH_CRS" I R 9300 6700 60 F52 "ETH_COL" I R 9300 6800 60 F53 "NF_D[0..7]" B R 9300 4050 60 F54 "NF_WE_N" O R 9300 3750 60 F55 "NF_ALE" O R 9300 3550 60 F56 "NF_CLE" O R 9300 3650 60 F57 "NF_CS1_N" O R 9300 3450 60 F58 "NF_RE_N" O R 9300 3850 60 F59 "NF_RNB" B R 9300 3950 60 F60 "PROG_CCLK" O R 9300 4400 60 F61 "PROG_CSO" O R 9300 4300 60 F62 "PROG_MISO[0..3]" B R 9300 4500 60 F63 "S6_TCK" I L 5950 7850 60 F64 "S6_TDI" I L 5950 7950 60 F65 "S6_TDO" O L 5950 8050 60 F66 "S6_TMS" I L 5950 8150 60 $EndSheet $Sheet S 10600 6250 1300 1800 U 4C4320F3 F0 "Ethernet Phy" 60 F1 "eth_phy.sch" 60 F2 "ETH_RXC" O L 10600 6500 60 F3 "ETH_RST_N" I L 10600 6600 60 F4 "ETH_CRS" O L 10600 6700 60 F5 "ETH_COL" O L 10600 6800 60 F6 "ETH_MDIO" B L 10600 6900 60 F7 "ETH_MDC" I L 10600 7000 60 F8 "ETH_RXD[0..3]" O L 10600 7200 60 F9 "ETH_RXDV" O L 10600 7300 60 F10 "ETH_RXER" O L 10600 7400 60 F11 "ETH_TXC" B L 10600 7500 60 F12 "ETH_TXD[0..3]" I L 10600 7600 60 F13 "ETH_TXEN" I L 10600 7700 60 F14 "ETH_TXER" I L 10600 7800 60 F15 "ETH_CLK" I L 10600 7900 60 F16 "ETH_INT" O L 10600 6350 60 $EndSheet $Sheet S 3600 2700 1100 4000 U 4C421DD3 F0 "DDR Banks" 60 F1 "DRAM.sch" 60 F2 "M0_BA[0..1]" I R 4700 5250 60 F3 "M1_BA[0..1]" I R 4700 3150 60 F4 "M0_WE#" I R 4700 6550 60 F5 "M0_RAS#" I R 4700 6400 60 F6 "M1_RAS#" I R 4700 4350 60 F7 "M1_WE#" I R 4700 4500 60 F8 "M0_CAS#" I R 4700 6300 60 F9 "M0_CKE" I R 4700 5950 60 F10 "M0_CLK" I R 4700 6050 60 F11 "M0_CLK#" I R 4700 6150 60 F12 "M0_CS#" I R 4700 4900 60 F13 "M1_CLK#" I R 4700 4100 60 F14 "M1_CLK" I R 4700 4000 60 F15 "M1_CKE" I R 4700 3900 60 F16 "M1_CAS#" I R 4700 4250 60 F17 "M0_DQ[0..15]" B R 4700 5050 60 F18 "M0_UDM" I R 4700 5700 60 F19 "M0_LDQS" I R 4700 5500 60 F20 "M0_A[0..12]" I R 4700 5150 60 F21 "M0_LDM" I R 4700 5800 60 F22 "M0_UDQS" I R 4700 5400 60 F23 "M1_UDQS" I R 4700 3350 60 F24 "M1_LDM" I R 4700 3750 60 F25 "M1_LDQS" I R 4700 3450 60 F26 "M1_UDM" I R 4700 3650 60 F27 "M1_CS#" I R 4700 2800 60 F28 "M1_A[0..12]" I R 4700 3050 60 F29 "M1_DQ[0..15]" B R 4700 2950 60 $EndSheet $EndSCHEMATC