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095339fb97
xue/kicad/xue-rnc/eth_phy.sch
Juan64Bits b22aa62b24 Ethernet-phy and USB connected to FPGA
2010-08-09 15:37:18 -05:00

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13 KiB
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EESchema Schematic File Version 2 date Mon 09 Aug 2010 03:34:05 PM COT
LIBS:power,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache
EELAYER 24 0
EELAYER END
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Sheet 4 6
Title ""
Date "4 aug 2010"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
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Connection ~ 1650 3050
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Connection ~ 1900 1100
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Wire Wire Line
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ETH_A1.8V
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ETH_1.8V
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ETH_PLL1.8V
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ETH_1.8V
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GND
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3.3V
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3.3V
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GND
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GND
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Text GLabel 8150 3750 3 40 BiDi ~ 0
3.3V
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Text Label 5850 6250 0 60 ~ 0
ETH_RXD1
Text Label 3150 4800 0 40 ~ 0
ETH_LED1
Text Label 3150 4700 0 40 ~ 0
ETH_LED0
Text Label 7850 5900 0 40 ~ 0
ETH_LED1
Text Label 7850 5700 0 40 ~ 0
ETH_LED0
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1 8750 5700
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GND
Text GLabel 8900 4850 0 40 BiDi ~ 0
3.3V
$Comp
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1 9850 5150
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$EndComp
Text HLabel 3700 5750 0 60 Output ~ 0
ETH_RXC
Text HLabel 3700 5650 0 60 Input ~ 0
ETH_RST_N
Text HLabel 3700 4450 0 60 Output ~ 0
ETH_CRS
Text HLabel 3700 4350 0 60 Output ~ 0
ETH_COL
Text HLabel 3700 4550 0 60 Output ~ 0
ETH_INT
Text HLabel 3450 5150 0 60 BiDi ~ 0
ETH_MDIO
Text HLabel 3750 5050 0 60 Input ~ 0
ETH_MDC
Text Label 3150 5950 0 40 ~ 0
ETH_RXD1
Text Label 3150 5850 0 40 ~ 0
ETH_RXD0
Text Label 5850 6350 0 60 ~ 0
ETH_RXD0
Text Label 6400 6150 2 60 ~ 0
ETH_RXD2
Text Label 6400 6050 2 60 ~ 0
ETH_RXD3
Text HLabel 6650 6450 2 60 Output ~ 0
ETH_RXD[0..3]
Entry Wire Line
6400 6350 6500 6450
Entry Wire Line
6400 6250 6500 6350
Entry Wire Line
6400 6150 6500 6250
Entry Wire Line
6400 6050 6500 6150
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ETH_RXDV
Text HLabel 5650 5850 2 60 Output ~ 0
ETH_RXER
Text Label 6400 5350 2 60 ~ 0
ETH_TXD0
Text Label 6400 5250 2 60 ~ 0
ETH_TXD1
Text Label 6400 5150 2 60 ~ 0
ETH_TXD2
Text Label 6400 5050 2 60 ~ 0
ETH_TXD3
Text HLabel 5650 5450 2 60 BiDi ~ 0
ETH_TXC
Text HLabel 6650 4950 2 60 Input ~ 0
ETH_TXD[0..3]
Text HLabel 5650 4950 2 60 Input ~ 0
ETH_TXEN
Text HLabel 5650 4850 2 60 Input ~ 0
ETH_TXER
Entry Wire Line
6400 5050 6500 4950
Entry Wire Line
6400 5050 6500 4950
Entry Wire Line
6400 5150 6500 5050
Entry Wire Line
6400 5250 6500 5150
Entry Wire Line
6400 5350 6500 5250
Text HLabel 5700 4550 2 60 Input ~ 0
ETH_CLK
$EndSCHEMATC
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