mirror of
git://projects.qi-hardware.com/xue.git
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395 lines
8.7 KiB
Plaintext
395 lines
8.7 KiB
Plaintext
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
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LIBS:power
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LIBS:r_pack2
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LIBS:v0402mhs03
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LIBS:usb-48204-0001
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LIBS:microsmd075f
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LIBS:mic2550
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LIBS:rj45-48025
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LIBS:xue-nv
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LIBS:xc6slx75fgg484
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LIBS:xc6slx45fgg484
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LIBS:micron_mobile_ddr
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LIBS:micron_ddr_512Mb
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LIBS:k8001
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:special
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:pasives-connectors
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LIBS:x25x64mb
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LIBS:attiny
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LIBS:PSU
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LIBS:xue-rnc-cache
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EELAYER 24 0
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EELAYER END
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$Descr A3 16535 11700
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Sheet 1 9
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Title ""
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Date "7 sep 2010"
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 5950 5150 3350 4150
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U 4C7BC2B2
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F0 "FPGA, Port0, Port2, PROG IF" 60
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F1 "FPGA_0_2_PROG.sch" 60
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F2 "S6_TCK" I L 5950 6450 60
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F3 "S6_TDI" I L 5950 6550 60
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F4 "S6_TDO" O L 5950 6650 60
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F5 "S6_TMS" I L 5950 6750 60
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F6 "PROG_MISO[0..3]" B R 9300 9150 60
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F7 "PROG_CCLK" O R 9300 9050 60
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F8 "PROG_CSO" O R 9300 8950 60
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F9 "NF_D[0..7]" B R 9300 8700 60
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F10 "ETH_COL" B R 9300 5850 60
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F11 "ETH_CRS" B R 9300 5750 60
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F12 "NF_WE_N" O R 9300 8400 60
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F13 "NF_ALE" O R 9300 8200 60
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F14 "NF_CLE" O R 9300 8300 60
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F15 "NF_CS1_N" O R 9300 8100 60
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F16 "NF_RE_N" O R 9300 8500 60
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F17 "NF_RNB" B R 9300 8600 60
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F18 "SD_CLK" B R 9300 7550 60
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F19 "SD_CMD" B R 9300 7650 60
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F20 "SD_DAT[0..3]" B R 9300 7750 60
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F21 "ETH_CLK" B R 9300 6950 60
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F22 "ETH_RXC" B R 9300 5550 60
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F23 "ETH_TXC" B R 9300 6550 60
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F24 "ETH_TXD[0..3]" O R 9300 6650 60
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F25 "ETH_TXEN" B R 9300 6750 60
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F26 "ETH_TXER" B R 9300 6850 60
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F27 "ETH_RXER" B R 9300 6450 60
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F28 "ETH_RXDV" B R 9300 6350 60
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F29 "ETH_RXD[0..3]" I R 9300 6250 60
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F30 "ETH_RESET_N" B R 9300 5650 60
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F31 "ETH_MDIO" B R 9300 5950 60
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F32 "ETH_MDC" B R 9300 6050 60
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F33 "ETH_INT" B R 9300 5400 60
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$EndSheet
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$Sheet
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S 5950 700 3300 4200
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U 4C7BC2A2
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F0 "FPGA Port 1, Port 3 (DDR, USB)" 60
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F1 "FPGA_1_3.sch" 60
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F2 "USBD_VP" B R 9250 1850 60
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F3 "USBD_SPD" B R 9250 1550 60
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F4 "USBD_OE_N" B R 9250 1650 60
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F5 "USBD_RCV" B R 9250 1750 60
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F6 "USBD_VM" B R 9250 1950 60
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F7 "M0_CKE" O L 5950 4100 60
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F8 "M0_UDM" O L 5950 3850 60
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F9 "M0_UDQS" O L 5950 3550 60
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F10 "M0_BA[0..1]" O L 5950 3400 60
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F11 "M0_CAS#" O L 5950 4450 60
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F12 "M0_RAS#" O L 5950 4550 60
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F13 "M0_WE#" O L 5950 4700 60
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F14 "M0_LDM" O L 5950 3950 60
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F15 "M0_LDQS" O L 5950 3650 60
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F16 "M1_UDQS" O L 5950 1500 60
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F17 "M1_UDM" O L 5950 1800 60
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F18 "M1_LDQS" O L 5950 1600 60
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F19 "M1_LDM" O L 5950 1900 60
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F20 "M1_WE#" O L 5950 2650 60
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F21 "M1_CKE" O L 5950 2050 60
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F22 "M1_RAS#" O L 5950 2500 60
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F23 "M1_CAS#" O L 5950 2400 60
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F24 "M1_BA[0..1]" O L 5950 1300 60
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F25 "M1_CS#" O L 5950 950 60
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F26 "USBA_VM" B R 9250 1350 60
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F27 "USBA_VP" B R 9250 1250 60
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F28 "USBA_RCV" B R 9250 1150 60
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F29 "USBA_OE_N" B R 9250 1050 60
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F30 "USBA_SPD" B R 9250 950 60
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F31 "M1_DQ[0..15]" B L 5950 1100 60
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F32 "M0_CS#" O L 5950 3050 60
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F33 "M0_DQ[0..15]" B L 5950 3200 60
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F34 "M0_A[0..12]" O L 5950 3300 60
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F35 "M1_A[0..12]" O L 5950 1200 60
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F36 "M1_CLK" O L 5950 2150 60
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F37 "M1_CLK#" O L 5950 2250 60
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F38 "M0_CLK" O L 5950 4200 60
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F39 "M0_CLK#" O L 5950 4300 60
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$EndSheet
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Wire Wire Line
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10600 1950 9250 1950
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Wire Wire Line
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10600 1750 9250 1750
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Wire Wire Line
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10600 1550 9250 1550
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Wire Wire Line
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4950 6650 5950 6650
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Wire Wire Line
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5950 6450 4950 6450
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Wire Bus Line
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10650 9150 9300 9150
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Wire Wire Line
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10650 8100 9300 8100
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Wire Wire Line
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10650 8500 9300 8500
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Wire Wire Line
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9300 8200 10650 8200
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Wire Wire Line
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10600 5850 9300 5850
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Wire Bus Line
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9300 7750 10650 7750
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Wire Wire Line
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9300 7550 10650 7550
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Wire Wire Line
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10600 1350 9250 1350
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Wire Wire Line
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10600 1150 9250 1150
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Wire Wire Line
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10600 950 9250 950
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Wire Wire Line
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9300 6850 10600 6850
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Wire Wire Line
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9300 6450 10600 6450
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Wire Wire Line
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10600 5950 9300 5950
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Wire Wire Line
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9300 5550 10600 5550
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Wire Bus Line
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4700 1300 5950 1300
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Wire Wire Line
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4700 950 5950 950
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Wire Wire Line
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4700 1900 5950 1900
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Wire Wire Line
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4700 2050 5950 2050
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Wire Wire Line
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4700 2400 5950 2400
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Wire Wire Line
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4700 4100 5950 4100
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Wire Wire Line
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4700 4700 5950 4700
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Wire Bus Line
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4700 3400 5950 3400
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Wire Wire Line
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4700 4450 5950 4450
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Wire Wire Line
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4700 3850 5950 3850
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Wire Wire Line
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4700 3550 5950 3550
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Wire Bus Line
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4700 1200 5950 1200
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Wire Wire Line
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5950 2250 4700 2250
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Wire Wire Line
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4700 4300 5950 4300
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Wire Bus Line
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5950 3250 5950 3200
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Wire Bus Line
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5950 3200 4700 3200
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Wire Wire Line
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4700 4200 5950 4200
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Wire Wire Line
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4700 2150 5950 2150
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Wire Bus Line
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4700 3300 5950 3300
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Wire Wire Line
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4700 3950 5950 3950
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Wire Wire Line
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4700 3650 5950 3650
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Wire Wire Line
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4700 4550 5950 4550
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Wire Wire Line
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4700 3050 5950 3050
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Wire Wire Line
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4700 2500 5950 2500
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Wire Wire Line
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4700 2650 5950 2650
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Wire Wire Line
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4700 1800 5950 1800
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Wire Wire Line
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4700 1600 5950 1600
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Wire Wire Line
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4700 1500 5950 1500
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Wire Bus Line
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4700 1100 5950 1100
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Wire Wire Line
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9300 5400 10600 5400
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Wire Wire Line
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9300 5650 10600 5650
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Wire Wire Line
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9300 6050 10600 6050
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Wire Wire Line
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9300 6350 10600 6350
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Wire Wire Line
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9300 6550 10600 6550
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Wire Wire Line
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9300 6750 10600 6750
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Wire Wire Line
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9300 6950 10600 6950
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Wire Wire Line
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10600 1050 9250 1050
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Wire Wire Line
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10600 1250 9250 1250
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Wire Bus Line
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9300 6650 10600 6650
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Wire Bus Line
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10600 6250 9300 6250
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Wire Wire Line
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9300 7650 10650 7650
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Wire Wire Line
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10600 5750 9300 5750
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Wire Bus Line
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10650 8700 9300 8700
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Wire Wire Line
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10650 8300 9300 8300
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Wire Wire Line
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10650 8400 9300 8400
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Wire Wire Line
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10650 8600 9300 8600
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Wire Wire Line
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10650 8950 9300 8950
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Wire Wire Line
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10650 9050 9300 9050
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Wire Wire Line
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5950 6550 4950 6550
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Wire Wire Line
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5950 6750 4950 6750
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Wire Wire Line
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10600 1650 9250 1650
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Wire Wire Line
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10600 1850 9250 1850
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$Sheet
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S 3750 6400 1200 700
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U 4C716A4D
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F0 "DBG_PRG" 60
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F1 "DBG_PRG.sch" 60
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F2 "FPGA_TDO" B R 4950 6650 60
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F3 "FPGA_TDI" B R 4950 6550 60
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F4 "FPGA_TMS" B R 4950 6750 60
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F5 "FPGA_TCK" B R 4950 6450 60
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$EndSheet
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$Sheet
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S 3750 8000 1100 1300
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U 4C69ED5F
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F0 "PSU" 60
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F1 "PSU.sch" 60
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$EndSheet
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$Sheet
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S 10650 7350 1050 1950
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U 4C4227FE
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F0 "Non volatile memories" 60
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F1 "NV_MEMORIES.sch" 60
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F2 "SD_CMD" I L 10650 7650 60
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F3 "SD_CLK" I L 10650 7550 60
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F4 "SD_DAT[0..3]" B L 10650 7750 60
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F5 "NF_D[0..7]" B L 10650 8700 60
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F6 "NF_ALE" B L 10650 8200 60
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F7 "NF_CLE" B L 10650 8300 60
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F8 "NF_WE_N" B L 10650 8400 60
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F9 "NF_CS1_N" B L 10650 8100 60
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F10 "NF_RE_N" B L 10650 8500 60
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F11 "NF_RNB" B L 10650 8600 60
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F12 "SPI_CLK" I L 10650 9050 60
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F13 "SPI_FLASH_CS#" I L 10650 8950 60
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F14 "SPI_DQ[0..3]" B L 10650 9150 60
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$EndSheet
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$Sheet
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S 10600 900 1100 1150
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U 4C5F1EDC
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F0 "USB" 60
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F1 "USB.sch" 60
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F2 "USBA_SPD" B L 10600 950 60
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F3 "USBA_OE_N" B L 10600 1050 60
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F4 "USBA_RCV" B L 10600 1150 60
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F5 "USBA_VP" B L 10600 1250 60
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F6 "USBA_VM" B L 10600 1350 60
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F7 "USBD_SPD" B L 10600 1550 60
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F8 "USBD_OE_N" B L 10600 1650 60
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F9 "USBD_RCV" B L 10600 1750 60
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F10 "USBD_VP" B L 10600 1850 60
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F11 "USBD_VM" B L 10600 1950 60
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$EndSheet
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Text Notes 12850 10750 0 60 ~ 0
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Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
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$Sheet
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S 10600 5300 1300 1800
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U 4C4320F3
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F0 "Ethernet Phy" 60
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F1 "eth_phy.sch" 60
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F2 "ETH_RXC" O L 10600 5550 60
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F3 "ETH_RST_N" I L 10600 5650 60
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F4 "ETH_CRS" O L 10600 5750 60
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F5 "ETH_COL" O L 10600 5850 60
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F6 "ETH_MDIO" B L 10600 5950 60
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F7 "ETH_MDC" I L 10600 6050 60
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F8 "ETH_RXD[0..3]" O L 10600 6250 60
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F9 "ETH_RXDV" O L 10600 6350 60
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F10 "ETH_RXER" O L 10600 6450 60
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F11 "ETH_TXC" B L 10600 6550 60
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F12 "ETH_TXD[0..3]" I L 10600 6650 60
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F13 "ETH_TXEN" I L 10600 6750 60
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F14 "ETH_TXER" I L 10600 6850 60
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F15 "ETH_CLK" I L 10600 6950 60
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F16 "ETH_INT" O L 10600 5400 60
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$EndSheet
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$Sheet
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S 3600 850 1100 4000
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U 4C421DD3
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F0 "DDR Banks" 60
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F1 "DRAM.sch" 60
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F2 "M0_BA[0..1]" I R 4700 3400 60
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F3 "M1_BA[0..1]" I R 4700 1300 60
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F4 "M0_WE#" I R 4700 4700 60
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F5 "M0_RAS#" I R 4700 4550 60
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F6 "M1_RAS#" I R 4700 2500 60
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F7 "M1_WE#" I R 4700 2650 60
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F8 "M0_CAS#" I R 4700 4450 60
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F9 "M0_CKE" I R 4700 4100 60
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F10 "M0_CLK" I R 4700 4200 60
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F11 "M0_CLK#" I R 4700 4300 60
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F12 "M0_CS#" I R 4700 3050 60
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F13 "M1_CLK#" I R 4700 2250 60
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F14 "M1_CLK" I R 4700 2150 60
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F15 "M1_CKE" I R 4700 2050 60
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F16 "M1_CAS#" I R 4700 2400 60
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F17 "M0_DQ[0..15]" B R 4700 3200 60
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F18 "M0_UDM" I R 4700 3850 60
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F19 "M0_LDQS" I R 4700 3650 60
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F20 "M0_A[0..12]" I R 4700 3300 60
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F21 "M0_LDM" I R 4700 3950 60
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F22 "M0_UDQS" I R 4700 3550 60
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F23 "M1_UDQS" I R 4700 1500 60
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F24 "M1_LDM" I R 4700 1900 60
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F25 "M1_LDQS" I R 4700 1600 60
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F26 "M1_UDM" I R 4700 1800 60
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F27 "M1_CS#" I R 4700 950 60
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F28 "M1_A[0..12]" I R 4700 1200 60
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F29 "M1_DQ[0..15]" B R 4700 1100 60
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$EndSheet
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$EndSCHEMATC
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