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180 lines
14 KiB
Systemverilog
180 lines
14 KiB
Systemverilog
/****************************************************************************************
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2005 Micron Technology, Inc. All rights reserved.
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*
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*
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* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
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* Added ROW_BITS & BA_BITS for compatibility w/our system.
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* Removed part size parameter.
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*
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****************************************************************************************/
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// Parameters current with 2048Mb LPDDR SDRAM
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// 04.26.10 - Based on Rev 0.7 04/09EN (DDS)
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// SYMBOL UNITS DESCRIPTION
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// ------ ----- -----------
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`ifdef sg5 // Timing Parameters for -5 (CL = 3)
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parameter tAC3_max = 4.8; // tAC ns Access window of DQ from CK/CK#
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parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
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parameter tCK = 4.8; // tCK ns Nominal Clock Cycle Time
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parameter tCK3_min = 4.8; // tCK ns Nominal Clock Cycle Time
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parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter tHZ3_max = 4.8; // tHZ ns Data-out high Z window from CK/CK#
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parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
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parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
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parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
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parameter tRCD = 14.4; // tRCD ns Active to Read/Write command time
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parameter tRP = 14.4; // tRP ns Precharge command period
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parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
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parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
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parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
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parameter tWR = 14.4; // tWR ns Write recovery time
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`else `ifdef sg54 // Timing Parameters for -6 (CL = 3)
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parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
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parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
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parameter tCK = 5.4; // tCK ns Nominal Clock Cycle Time
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parameter tCK3_min = 5.4; // tCK ns Nominal Clock Cycle Time
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parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
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parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
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parameter tRAS = 41.8; // tRAS ns Active to Precharge command time
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parameter tRC = 58.2; // tRC ns Active to Active/Auto Refresh command time
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parameter tRCD = 16.2; // tRCD ns Active to Read/Write command time
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parameter tRP = 16.2; // tRP ns Precharge command period
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parameter tRRD = 10.8; // tRRD ns Active bank a to Active bank b command time
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parameter tWTR = 2.0; // tWTR tCK Internal Write-to-Read command delay
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parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
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parameter tWR = 15.0; // tWR ns Write recovery time
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`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
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parameter tAC3_max = 5.5; // tAC ns Access window of DQ from CK/CK#
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parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
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parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
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parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
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parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter tHZ3_max = 5.5; // tHZ ns Data-out high Z window from CK/CK#
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parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
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parameter tRAS = 41.8; // tRAS ns Active to Precharge command time
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parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
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parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
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parameter tRP = 18.0; // tRP ns Precharge command period
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parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
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parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
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parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
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parameter tWR = 15.0; // tWR ns Write recovery time
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`else `define sg75 // Timing Parameters for -75 (CL = 3)
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parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
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parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
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parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
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parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
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parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
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parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
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parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
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parameter tRC = 67.5; // tRC ns Active to Active/Auto Refresh command time
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parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
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parameter tRP = 22.5; // tRP ns Precharge command period
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parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
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parameter tWTR = 1.0; // tWTR tCK Internal Write-to-Read command delay
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parameter tXP = 7.50; // tXP ns Exit power-down to first valid cmd Note: spec'd as 2 * tCK
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parameter tWR = 15.0; // tWR ns Write recovery time
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`endif `endif `endif
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parameter tAC2_min = 2.0; // tAC ns Access window of DQ from CK/CK#
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parameter tAC3_min = 2.0; // tAC ns Access window of DQ from CK/CK#
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parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
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parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
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parameter tRFC = 72.0; // tRFC ns Refresh to Refresh Command interval time
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parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command Note: model adds CL to this value
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parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command
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parameter tCH_MAX = 0.55; // Clk high level width
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parameter tCH_MIN = 0.45; // Clk high level width
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parameter tCL_MAX = 0.55; // Clk low level width
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parameter tCL_MIN = 0.45; // Clk low level width
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parameter tCKE = 1.0 ; // Minimum tCKE High/Low time (in tCK's)
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parameter CL_MAX = 3 ; // Maximum CAS Latency
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parameter BL_MAX = 16 ;
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// Size Parameters based on Part Width
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`ifdef x16
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`ifdef RP
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parameter ADDR_BITS = 15; // Set this parameter to control how many Address bits are used
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parameter ROW_BITS = 15; // Set this parameter to control how many Row bits are used
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parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
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parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
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parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
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parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
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parameter BA_BITS = 2; // Set this parameter to control how many Bank bits are used
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`else
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parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
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parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
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parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
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parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
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parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
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parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
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parameter BA_BITS = 2; // Set this parameter to control how many Bank bits are used
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`endif
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`else `define x32
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`ifdef RP // reduced page mode
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parameter ADDR_BITS = 15; // Set this parameter to control how many Address bits are used
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parameter ROW_BITS = 15; // Set this parameter to control how many Row bits are used
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parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
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parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
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parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
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parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
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parameter BA_BITS = 2; // Bank bits
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`else
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parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
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parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
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parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
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parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
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parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
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parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
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parameter BA_BITS = 2; // Bank bits
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`endif
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`endif
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// For use with the Multi Chip Package
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`ifdef DUAL_RANK
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parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
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parameter RANKS = 2; // Set this parameter to control how many Ranks on the mcp are used
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`else
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parameter CS_BITS = 2; // Set this parameter to control how many Chip Select bits are used
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parameter RANKS = 1; // Set this parameter to control how many Ranks on the mcp are used
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`endif
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parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
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parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
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parameter part_size = 2048; // Set this parameter to indicate part size(1024Mb, 512Mb, 256Mb, 128Mb)
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