mirror of
git://projects.qi-hardware.com/xue.git
synced 2024-11-09 17:46:14 +02:00
33 lines
875 B
Systemverilog
33 lines
875 B
Systemverilog
initial begin:test
|
|
//ck <= 1'b0;
|
|
cke <= 1'b0;
|
|
cs_n <= 1'bz;
|
|
ras_n <= 1'bz;
|
|
cas_n <= 1'bz;
|
|
we_n <= 1'bz;
|
|
a <= {ADDR_BITS{1'bz}};
|
|
ba <= {BA_BITS{1'bz}};
|
|
dq_en <= 1'b0;
|
|
dqs_en <= 1'b0;
|
|
power_up;
|
|
nop (10); // wait 10 clocks intead of 200 us for simulation purposes
|
|
precharge('h00000000, 1);
|
|
nop(trp);
|
|
refresh;
|
|
nop(trfc);
|
|
refresh;
|
|
nop(trfc);
|
|
load_mode('h0, 'h00000032);
|
|
nop(tmrd);
|
|
load_mode('h2, 'h00004000);
|
|
nop(tmrd);
|
|
activate('h00000000, 'h00000000);
|
|
nop(trcd-1);
|
|
write('h00000000, 'h00000000, 0, { {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}}, { 16'h3000, 16'h2000, 16'h1000, 16'h0});
|
|
nop(bl/2+twr);
|
|
read('h00000000, 'h00000000, 1);
|
|
nop(bl/2-1);
|
|
nop('h00000014);
|
|
test_done;
|
|
end
|