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Code
2db4e52026
xue/kicad/xue-rnc/xue-rnc.net
Juan64Bits 2db4e52026 Revition...
2010-11-01 17:50:49 -05:00

5317 lines
99 KiB
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# EESchema Netlist Version 1.1 created Mon 01 Nov 2010 04:33:08 PM COT
(
( /4CB0D95D/4CBAFE50 header25x2_smd_2mm P1 CONN_25X2 {Lib=CONN_25X2}
( 1 /FPGA_GPIOS/FPGA_BANK0_IO_8 )
( 2 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1 )
( 3 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_16 )
( 4 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9 )
( 5 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0 )
( 6 /FPGA_GPIOS/FPGA_BANK0_IO_14 )
( 7 /FPGA_GPIOS/FPGA_BANK0_IO_10 )
( 8 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_15 )
( 9 /FPGA_GPIOS/FPGA_BANK0_IO_11 )
( 10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_3 )
( 11 /FPGA_GPIOS/FPGA_BANK0_IO_5 )
( 12 /FPGA_GPIOS/FPGA_BANK0_IO_18 )
( 13 /FPGA_GPIOS/FPGA_BANK0_IO_17 )
( 14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21 )
( 15 /FPGA_GPIOS/FPGA_BANK0_IO_20 )
( 16 /FPGA_GPIOS/FPGA_BANK0_IO_24 )
( 17 /FPGA_GPIOS/FPGA_BANK0_IO_28 )
( 18 /FPGA_GPIOS/FPGA_BANK0_IO_29 )
( 19 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22 )
( 20 /FPGA_GPIOS/FPGA_BANK0_IO_30 )
( 21 /FPGA_GPIOS/FPGA_BANK0_IO_27 )
( 22 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_25 )
( 23 /FPGA_GPIOS/FPGA_BANK0_IO_39 )
( 24 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33 )
( 25 /FPGA_GPIOS/FPGA_BANK0_IO_2 )
( 26 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32 )
( 27 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_7 )
( 28 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6 )
( 29 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12 )
( 30 /FPGA_GPIOS/FPGA_BANK0_IO_36 )
( 31 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44 )
( 32 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40 )
( 33 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47 )
( 34 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43 )
( 35 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45 )
( 36 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46 )
( 37 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52 )
( 38 /FPGA_GPIOS/FPGA_BANK0_IO_50 )
( 39 /FPGA_GPIOS/FPGA_BANK0_IO_56 )
( 40 /FPGA_GPIOS/FPGA_BANK0_IO_48 )
( 41 ? )
( 42 ? )
( 43 ? )
( 44 ? )
( 45 ? )
( 46 ? )
( 47 ? )
( 48 ? )
( 49 ? )
( 50 ? )
)
( /4C9E2AF4/4CAF29D5 $noname MP1 M12-TU400A {Lib=M12-TU400A}
( 1 ? )
( 2 ? )
)
( /4C9E2AF4/4C9E3C76 $noname C140 100nF {Lib=C}
( 1 /Image_Sensor/+2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C71 $noname C142 100nF {Lib=C}
( 1 /Image_Sensor/+2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C70 $noname C144 10uF {Lib=CAPAPOL}
( 1 /Image_Sensor/+2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C6F $noname C143 100nF {Lib=C}
( 1 /Image_Sensor/+2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C6E $noname C141 100nF {Lib=C}
( 1 /Image_Sensor/+2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C65 $noname C136 100nF {Lib=C}
( 1 /Snesor_PSU/+1.8_VDD )
( 2 GND )
)
( /4C9E2AF4/4C9E3C5F $noname C138 100nF {Lib=C}
( 1 /Snesor_PSU/+1.8_VDD )
( 2 GND )
)
( /4C9E2AF4/4C9E3C5E $noname C139 10uF {Lib=CAPAPOL}
( 1 /Snesor_PSU/+1.8_VDD )
( 2 GND )
)
( /4C9E2AF4/4C9E3C5D $noname C137 100nF {Lib=C}
( 1 /Snesor_PSU/+1.8_VDD )
( 2 GND )
)
( /4C9E2AF4/4C9E3C32 $noname C133 100nF {Lib=C}
( 1 /Snesor_PSU/+2.8_VAA )
( 2 GND )
)
( /4C9E2AF4/4C9E3C2E $noname C135 10uF {Lib=CAPAPOL}
( 1 /Snesor_PSU/+2.8_VAA )
( 2 GND )
)
( /4C9E2AF4/4C9E3C2D $noname C134 100nF {Lib=C}
( 1 /Snesor_PSU/+2.8_VAA )
( 2 GND )
)
( /4C9E2AF4/4C9E3C27 $noname C131 100nF {Lib=C}
( 1 /Image_Sensor/+2.8_VAAPIX )
( 2 GND )
)
( /4C9E2AF4/4C9E3C26 $noname C132 10uF {Lib=CAPAPOL}
( 1 /Image_Sensor/+2.8_VAAPIX )
( 2 GND )
)
( /4C9E2AF4/4C9E3C04 $noname C130 10uF {Lib=CAPAPOL}
( 1 /Snesor_PSU/+2.8_VDDPLL )
( 2 GND )
)
( /4C9E2AF4/4C9E3C00 $noname C129 100nF {Lib=C}
( 1 /Snesor_PSU/+2.8_VDDPLL )
( 2 GND )
)
( /4C9E2AF4/4C9E3B7C $noname U24 MT9M033 {Lib=MT9M033}
( 1 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4 )
( 2 /Image_Sensor/IS_DOUT5 )
( 3 /Image_Sensor/IS_DOUT6 )
( 4 /Snesor_PSU/+2.8_VDDPLL )
( 5 /FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK )
( 6 GND )
( 7 /Image_Sensor/IS_DOUT7 )
( 8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8 )
( 9 /Image_Sensor/IS_DOUT9 )
( 10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10 )
( 11 /Image_Sensor/IS_DOUT11 )
( 12 /Image_Sensor/+2.8_VDDIO )
( 13 /Image_Sensor/IS_PIXEL )
( 14 /Snesor_PSU/+1.8_VDD )
( 15 /Image_Sensor/IS_SCL )
( 16 /FPGA,_Port0,_Port2,_PROG_IF/IS_SDA )
( 17 /Image_Sensor/IS_RESET_N )
( 18 /Image_Sensor/+2.8_VDDIO )
( 19 /Snesor_PSU/+1.8_VDD )
( 20 ? )
( 21 ? )
( 22 /Image_Sensor/IS_STANDBY )
( 23 /FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N )
( 24 /Image_Sensor/IS_I2C_ADDR )
( 25 /Image_Sensor/IS_TEST )
( 26 /Image_Sensor/IS_FLASH )
( 27 /Image_Sensor/IS_TRIGGER )
( 28 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME )
( 29 /Image_Sensor/IS_LINE )
( 30 GND )
( 31 ? )
( 32 ? )
( 33 ? )
( 34 /Snesor_PSU/+2.8_VAA )
( 35 GND )
( 36 /Snesor_PSU/+2.8_VAA )
( 37 /Image_Sensor/+2.8_VAAPIX )
( 38 /Image_Sensor/+2.8_VAAPIX )
( 39 GND )
( 40 /Snesor_PSU/+2.8_VAA )
( 41 ? )
( 42 ? )
( 43 ? )
( 44 GND )
( 45 /Image_Sensor/IS_DOUT0 )
( 46 /Image_Sensor/IS_DOUT1 )
( 47 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2 )
( 48 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3 )
)
( /4C9E2B0F/4C9E2BAA $noname C107 10uF {Lib=CAPAPOL}
( 1 +BATT )
( 2 GND )
)
( /4C9E2B0F/4C9E2BA9 $noname C110 10nF {Lib=C}
( 1 N-000472 )
( 2 GND )
)
( /4C9E2B0F/4C9E2BA8 $noname R64 R {Lib=R}
( 1 N-000469 )
( 2 GND )
)
( /4C9E2B0F/4C9E2BA7 $noname R63 R {Lib=R}
( 1 /Snesor_PSU/+1.8_VDD )
( 2 N-000469 )
)
( /4C9E2B0F/4C9E2BA6 $noname C116 10uF {Lib=CAPAPOL}
( 1 /Snesor_PSU/+1.8_VDD )
( 2 GND )
)
( /4C9E2B0F/4C9E2BA5 $noname C113 22pF {Lib=C}
( 1 /Snesor_PSU/+1.8_VDD )
( 2 N-000469 )
)
( /4C9E2B0F/4C9E2BA4 $noname U20 TPS793XX {Lib=TPS793XX}
( 1 +BATT )
( 2 GND )
( 3 +BATT )
( 4 N-000472 )
( 5 N-000469 )
( 6 /Snesor_PSU/+1.8_VDD )
)
( /4C9E2B0F/4C9E2B96 $noname U23 TPS793XX {Lib=TPS793XX}
( 1 +BATT )
( 2 GND )
( 3 +BATT )
( 4 N-000470 )
( 5 N-000471 )
( 6 /Snesor_PSU/+2.8_VDDPLL )
)
( /4C9E2B0F/4C9E2B95 $noname C125 22pF {Lib=C}
( 1 /Snesor_PSU/+2.8_VDDPLL )
( 2 N-000471 )
)
( /4C9E2B0F/4C9E2B94 $noname C128 10uF {Lib=CAPAPOL}
( 1 /Snesor_PSU/+2.8_VDDPLL )
( 2 GND )
)
( /4C9E2B0F/4C9E2B93 $noname R67 R {Lib=R}
( 1 /Snesor_PSU/+2.8_VDDPLL )
( 2 N-000471 )
)
( /4C9E2B0F/4C9E2B92 $noname R68 R {Lib=R}
( 1 N-000471 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B91 $noname C121 10nF {Lib=C}
( 1 N-000470 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B90 $noname C118 10uF {Lib=CAPAPOL}
( 1 +BATT )
( 2 GND )
)
( /4C9E2B0F/4C9E2B86 $noname C117 10uF {Lib=CAPAPOL}
( 1 +BATT )
( 2 GND )
)
( /4C9E2B0F/4C9E2B85 $noname C120 10nF {Lib=C}
( 1 N-000464 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B84 $noname R66 R {Lib=R}
( 1 N-000463 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B83 $noname R65 R {Lib=R}
( 1 /Image_Sensor/+2.8_VDDIO )
( 2 N-000463 )
)
( /4C9E2B0F/4C9E2B82 $noname C127 10uF {Lib=CAPAPOL}
( 1 /Image_Sensor/+2.8_VDDIO )
( 2 GND )
)
( /4C9E2B0F/4C9E2B81 $noname C124 22pF {Lib=C}
( 1 /Image_Sensor/+2.8_VDDIO )
( 2 N-000463 )
)
( /4C9E2B0F/4C9E2B80 $noname U22 TPS793XX {Lib=TPS793XX}
( 1 +BATT )
( 2 GND )
( 3 +BATT )
( 4 N-000464 )
( 5 N-000463 )
( 6 /Image_Sensor/+2.8_VDDIO )
)
( /4C9E2B0F/4C9E2B72 $noname U19 TPS793XX {Lib=TPS793XX}
( 1 +BATT )
( 2 GND )
( 3 +BATT )
( 4 N-000465 )
( 5 N-000468 )
( 6 /Image_Sensor/+2.8_VAAPIX )
)
( /4C9E2B0F/4C9E2B71 $noname C112 22pF {Lib=C}
( 1 /Image_Sensor/+2.8_VAAPIX )
( 2 N-000468 )
)
( /4C9E2B0F/4C9E2B70 $noname C115 10uF {Lib=CAPAPOL}
( 1 /Image_Sensor/+2.8_VAAPIX )
( 2 GND )
)
( /4C9E2B0F/4C9E2B6F $noname R61 R {Lib=R}
( 1 /Image_Sensor/+2.8_VAAPIX )
( 2 N-000468 )
)
( /4C9E2B0F/4C9E2B6E $noname R62 R {Lib=R}
( 1 N-000468 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B6D $noname C109 10nF {Lib=C}
( 1 N-000465 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B6C $noname C106 10uF {Lib=CAPAPOL}
( 1 +BATT )
( 2 GND )
)
( /4C9E2B0F/4C9E28CB $noname C105 10uF {Lib=CAPAPOL}
( 1 +BATT )
( 2 GND )
)
( /4C9E2B0F/4C9E28C1 $noname C108 10nF {Lib=C}
( 1 N-000467 )
( 2 GND )
)
( /4C9E2B0F/4C9E289D $noname R60 R {Lib=R}
( 1 N-000466 )
( 2 GND )
)
( /4C9E2B0F/4C9E287F $noname R59 R {Lib=R}
( 1 /Snesor_PSU/+2.8_VAA )
( 2 N-000466 )
)
( /4C9E2B0F/4C9E286D $noname C114 10uF {Lib=CAPAPOL}
( 1 /Snesor_PSU/+2.8_VAA )
( 2 GND )
)
( /4C9E2B0F/4C9E2857 $noname C111 22pF {Lib=C}
( 1 /Snesor_PSU/+2.8_VAA )
( 2 N-000466 )
)
( /4C9E2B0F/4C9E2848 $noname U18 TPS793XX {Lib=TPS793XX}
( 1 +BATT )
( 2 GND )
( 3 +BATT )
( 4 N-000467 )
( 5 N-000466 )
( 6 /Snesor_PSU/+2.8_VAA )
)
( /4C7BC2B2/4C749A0C 0402 C94 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C748EDB 0402 C92 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C748EDA 0402 C93 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C73D252 0402 C91 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C73D074 0402 C90 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C7168DD 0402 R30 330 {Lib=R}
( 1 +3.3V )
( 2 N-000417 )
)
( /4C7BC2B2/4C716877 0402 R29 4.7k {Lib=R}
( 1 +3.3V )
( 2 N-000420 )
)
( /4C7BC2B2/4C6B29DA 0402 C77 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C6B29A3 0402 C76 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C656D9D $noname C66 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D9A $noname C63 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D99 $noname C60 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D98 $noname C57 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D97 $noname C54 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D53 $noname C69 470nF {Lib=C}
( 1 /PSU/VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D49 $noname C67 470nF {Lib=C}
( 1 /PSU/VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D46 $noname C64 470nF {Lib=C}
( 1 /PSU/VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D45 $noname C61 470nF {Lib=C}
( 1 /PSU/VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D44 $noname C58 4.7uF {Lib=C}
( 1 /PSU/VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D43 $noname C55 100uF {Lib=C}
( 1 /PSU/VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D08 $noname C68 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CFC $noname C65 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CFB $noname C62 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CFA $noname C59 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CF9 $noname C56 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CBB $noname C50 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C656CBA $noname C47 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C656CB9 $noname C44 4.7uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C656CB7 $noname C41 100uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C656C49 $noname C53 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656C27 $noname C51 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656C24 $noname C49 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656C16 $noname C46 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656BFA $noname C52 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656BF9 $noname C43 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656BF8 $noname C40 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656AC2 $noname C48 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C656AC0 $noname C45 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C656ABD $noname C42 4.7uF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C656A80 $noname C39 100uF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
( F3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4 )
( E3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8 )
( D3 ? )
( C3 ? )
( B3 ? )
( Y2 ? )
( W2 +2.5V )
( V2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14 )
( T2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS )
( R2 +2.5V )
( P2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8 )
( M2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2 )
( L2 +2.5V )
( K2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6 )
( H2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0 )
( G2 +2.5V )
( F2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE# )
( D2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE )
( C2 +2.5V )
( B2 ? )
( A2 ? )
( Y1 ? )
( W1 ? )
( V1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15 )
( U1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13 )
( T1 ? )
( R1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11 )
( P1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9 )
( N1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1 )
( M1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3 )
( F5 ? )
( E5 ? )
( D5 ? )
( U4 ? )
( T4 ? )
( R4 ? )
( P4 ? )
( N4 ? )
( M4 ? )
( L4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM )
( K4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS# )
( J4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6 )
( H4 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK )
( G4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10 )
( F4 +2.5V )
( E4 ? )
( C4 ? )
( W3 ? )
( V3 ? )
( U3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12 )
( T3 ? )
( R3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10 )
( P3 ? )
( N3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0 )
( M3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM )
( L3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS )
( K3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5 )
( J3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4 )
( H3 /DDR_Banks/M0_CLK# )
( G3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0 )
( C13 ? )
( A13 /Non_volatile_memories/NF_D2 )
( C12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D0 )
( B12 /Non_volatile_memories/NF_D3 )
( A12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D4 )
( D11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D7 )
( C11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 )
( B11 +3.3V )
( A11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D6 )
( G10 +3.3V )
( D10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 )
( C10 /Ethernet_Phy/ETH_TXD2 )
( B10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS )
( A10 /Ethernet_Phy/ETH_INT )
( E9 +3.3V )
( D9 /Ethernet_Phy/ETH_TXEN )
( C9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1 )
( A9 /Ethernet_Phy/ETH_COL )
( D8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER )
( C8 /Ethernet_Phy/ETH_TXC )
( B8 /Ethernet_Phy/ETH_RXER )
( A8 /Ethernet_Phy/ETH_TXD3 )
( D7 /Ethernet_Phy/ETH_MDC )
( C7 /Ethernet_Phy/ETH_RST_N )
( B7 +3.3V )
( A7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC )
( D6 /Ethernet_Phy/ETH_MDIO )
( C6 /Ethernet_Phy/ETH_RXD2 )
( B6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 )
( A6 /Ethernet_Phy/ETH_RXDV )
( L1 ? )
( K1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7 )
( J1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5 )
( H1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1 )
( G1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1 )
( F1 ? )
( E1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9 )
( D1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12 )
( C1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11 )
( B1 ? )
( B19 +3.3V )
( B18 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT1 )
( A18 /Non_volatile_memories/SD_DAT0 )
( E17 +3.3V )
( D17 ? )
( C17 ? )
( A17 /Non_volatile_memories/SD_CLK )
( E16 ? )
( C16 /Non_volatile_memories/SD_CMD )
( B16 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3 )
( A16 /Non_volatile_memories/SD_DAT2 )
( D15 /Non_volatile_memories/NF_CS1_N )
( C15 /Non_volatile_memories/NF_RE_N )
( B15 +3.3V )
( A15 /Non_volatile_memories/NF_RNB )
( G14 +3.3V )
( D14 /FPGA,_Port0,_Port2,_PROG_IF/NF_D1 )
( C14 /Non_volatile_memories/NF_WE_N )
( B14 /FPGA,_Port0,_Port2,_PROG_IF/NF_CLE )
( A14 /FPGA,_Port0,_Port2,_PROG_IF/NF_ALE )
( E13 +3.3V )
( F17 /USB/USBA_RCV )
( N16 ? )
( M16 ? )
( L16 +2.5V )
( K16 ? )
( J16 ? )
( H16 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS# )
( G16 ? )
( F16 /USB/USBA_SPD )
( L15 ? )
( W22 ? )
( V22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15 )
( U22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13 )
( T22 ? )
( R22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11 )
( P22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9 )
( N22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1 )
( M22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3 )
( L22 ? )
( K22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7 )
( J22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5 )
( H22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS# )
( G22 ? )
( F22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1 )
( E22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2 )
( D22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12 )
( C22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9 )
( B22 /USB/USBD_VM )
( W21 +2.5V )
( V21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14 )
( U19 ? )
( T19 ? )
( R19 ? )
( P19 ? )
( N19 ? )
( M19 ? )
( L19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM )
( K19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6 )
( J19 /DDR_Banks/M1_CLK# )
( H19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE# )
( G19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10 )
( F19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11 )
( E19 +2.5V )
( D19 /USB/USBA_VP )
( C19 /USB/USBA_OE_N )
( U18 +2.5V )
( P18 ? )
( N18 +2.5V )
( M18 ? )
( K18 ? )
( J18 +2.5V )
( H18 ? )
( F18 ? )
( P17 ? )
( M17 ? )
( L17 ? )
( K17 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1 )
( J17 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0 )
( H17 ? )
( G17 ? )
( A20 /USB/USBD_RCV )
( P8 ? )
( M8 ? )
( K8 ? )
( H8 ? )
( P7 ? )
( N7 ? )
( M7 ? )
( L7 +2.5V )
( K7 ? )
( J7 ? )
( G7 ? )
( F7 ? )
( P6 ? )
( N6 ? )
( M6 ? )
( L6 ? )
( K6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3 )
( J6 ? )
( H6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7 )
( G6 ? )
( F6 +2.5V )
( E6 ? )
( U5 +2.5V )
( P5 ? )
( N5 +2.5V )
( M5 ? )
( K5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS# )
( J5 +2.5V )
( H5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2 )
( T21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS )
( R21 +2.5V )
( P21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8 )
( M21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2 )
( L21 +2.5V )
( K21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6 )
( H21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS# )
( G21 +2.5V )
( F21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0 )
( D21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE )
( C21 +2.5V )
( B21 /USB/USBD_VP )
( A21 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N )
( W20 ? )
( V20 ? )
( U20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12 )
( T20 ? )
( R20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10 )
( P20 ? )
( N20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0 )
( M20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM )
( L20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS )
( K20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5 )
( J20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4 )
( H20 /DDR_Banks/M1_CLK )
( G20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3 )
( F20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4 )
( E20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7 )
( D20 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM )
( C20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 )
( B20 /USB/USBD_SPD )
( J14 +1.2V )
( H14 ? )
( F14 ? )
( E14 ? )
( P13 +1.2V )
( N13 GND )
( M13 +1.2V )
( L13 GND )
( K13 +1.2V )
( J13 GND )
( H13 ? )
( G13 ? )
( F13 ? )
( D13 ? )
( B13 GND )
( Y22 N-000417 )
( A22 GND )
( R12 +2.5V )
( P12 GND )
( N12 +1.2V )
( M12 GND )
( L12 +1.2V )
( K12 GND )
( J12 +1.2V )
( H12 ? )
( G12 +2.5V )
( F12 ? )
( E12 ? )
( D12 ? )
( AB1 GND )
( A19 /FPGA,_Port0,_Port2,_PROG_IF/S6_TDO )
( R18 GND )
( L18 GND )
( G18 GND )
( E18 /DBG_PRG/FPGA_TDI )
( D18 GND )
( C18 /FPGA,_Port0,_Port2,_PROG_IF/S6_TMS )
( R17 ? )
( N17 GND )
( B17 GND )
( W16 GND )
( P16 ? )
( D16 +2.5V )
( AA5 GND )
( P15 ? )
( N15 GND )
( M15 +2.5V )
( K15 +2.5V )
( J15 GND )
( H15 +2.5V )
( G15 /DBG_PRG/FPGA_TCK )
( F15 ? )
( E15 GND )
( V14 GND )
( R14 +1.2V )
( P14 GND )
( N14 +1.2V )
( M14 GND )
( L14 +1.2V )
( K14 GND )
( L9 GND )
( K9 +1.2V )
( J9 GND )
( H9 +2.5V )
( G9 ? )
( F9 ? )
( B9 GND )
( N8 +2.5V )
( L8 +2.5V )
( J8 +1.2V )
( G8 ? )
( F8 ? )
( E8 ? )
( W7 GND )
( U7 GND )
( H7 GND )
( E7 GND )
( V6 +2.5V )
( R6 +2.5V )
( R5 GND )
( L5 GND )
( G5 GND )
( B5 GND )
( V4 GND )
( D4 GND )
( U2 GND )
( N2 GND )
( J2 GND )
( E2 GND )
( A1 GND )
( AA1 N-000420 )
( U21 GND )
( N21 GND )
( J21 GND )
( E21 GND )
( U11 +2.5V )
( P11 +1.2V )
( N11 GND )
( M11 +1.2V )
( L11 GND )
( K11 +1.2V )
( J11 GND )
( H11 ? )
( G11 ? )
( F11 +2.5V )
( E11 GND )
( Y20 +3.3V )
( V10 GND )
( R10 +2.5V )
( P10 GND )
( N10 +1.2V )
( M10 GND )
( L10 +1.2V )
( K10 GND )
( J10 +1.2V )
( H10 ? )
( F10 ? )
( E10 ? )
( P9 +1.2V )
( N9 GND )
( M9 +1.2V )
( V19 /FPGA_GPIOS/FPGA_BANK0_IO_10 )
( AB8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8 )
( AA8 /Image_Sensor/IS_DOUT7 )
( Y18 /FPGA_GPIOS/FPGA_BANK0_IO_5 )
( W18 ? )
( V18 /FPGA_GPIOS/FPGA_BANK0_IO_11 )
( T18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1 )
( AB7 /Image_Sensor/IS_DOUT11 )
( AA7 /PSU/VCCO2 )
( Y17 /FPGA_GPIOS/FPGA_BANK0_IO_20 )
( W17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_15 )
( V17 /FPGA_GPIOS/FPGA_BANK0_IO_14 )
( U17 /FPGA_GPIOS/FPGA_BANK0_IO_8 )
( T17 /FPGA_GPIOS/FPGA_BANK0_IO_2 )
( AB6 /Image_Sensor/IS_PIXEL )
( AA6 /FPGA,_Port0,_Port2,_PROG_IF/IS_SDA )
( Y16 /FPGA_GPIOS/FPGA_BANK0_IO_24 )
( V16 /PSU/VCCO2 )
( U16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9 )
( T16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6 )
( R16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12 )
( AB5 /Image_Sensor/IS_RESET_N )
( Y15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32 )
( W15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_25 )
( V15 /FPGA_GPIOS/FPGA_BANK0_IO_17 )
( U15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_16 )
( T15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_7 )
( R15 ? )
( AB4 /Image_Sensor/IS_I2C_ADDR )
( AA4 /Image_Sensor/IS_TEST )
( C5 /Ethernet_Phy/ETH_RXD3 )
( A5 /Ethernet_Phy/ETH_RXD1 )
( B4 +3.3V )
( A4 /Ethernet_Phy/ETH_CLK )
( A3 ? )
( AB19 ? )
( AA19 /PSU/VCCO2 )
( AB18 ? )
( AA18 /FPGA_GPIOS/FPGA_BANK0_IO_18 )
( AB17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21 )
( AB16 /FPGA_GPIOS/FPGA_BANK0_IO_29 )
( AA16 /FPGA_GPIOS/FPGA_BANK0_IO_28 )
( AB15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33 )
( AA15 /PSU/VCCO2 )
( AB14 ? )
( AA14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22 )
( AB13 /FPGA_GPIOS/FPGA_BANK0_IO_39 )
( AA22 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0 )
( AB12 /Image_Sensor/IS_DOUT0 )
( AA12 /Image_Sensor/IS_DOUT1 )
( AB21 ? )
( AA21 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK )
( AB11 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2 )
( AA11 /PSU/VCCO2 )
( AB20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0 )
( AA20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 )
( AB10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3 )
( AA10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4 )
( AB9 /Image_Sensor/IS_DOUT5 )
( Y19 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_3 )
( V9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52 )
( U9 ? )
( T9 /PSU/VCCO2 )
( R9 ? )
( Y8 /Image_Sensor/IS_DOUT6 )
( W8 /FPGA_GPIOS/FPGA_BANK0_IO_48 )
( V8 /PSU/VCCO2 )
( U8 ? )
( T8 ? )
( R8 ? )
( Y7 /Image_Sensor/IS_DOUT9 )
( V7 ? )
( T7 ? )
( R7 ? )
( Y6 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10 )
( W6 ? )
( U6 ? )
( T6 ? )
( Y5 /Image_Sensor/IS_STANDBY )
( W5 /PSU/VCCO2 )
( V5 ? )
( T5 /Non_volatile_memories/SPI_FLASH_CS# )
( Y4 /FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N )
( W4 ? )
( Y3 /Image_Sensor/IS_TRIGGER )
( AA17 GND )
( AA13 GND )
( AB22 GND )
( AA9 GND )
( W19 GND )
( Y14 ? )
( W14 /FPGA_GPIOS/FPGA_BANK0_IO_30 )
( U14 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 )
( T14 /FPGA_GPIOS/FPGA_BANK0_IO_36 )
( AB3 /Image_Sensor/IS_FLASH )
( AA3 /PSU/VCCO2 )
( Y13 ? )
( W13 /FPGA_GPIOS/FPGA_BANK0_IO_27 )
( V13 ? )
( U13 /Non_volatile_memories/SPI_DQ3 )
( T13 /PSU/VCCO2 )
( R13 ? )
( AB2 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME )
( AA2 /Image_Sensor/IS_LINE )
( Y12 /Image_Sensor/IS_SCL )
( W12 /FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK )
( V12 /PSU/VCCO2 )
( U12 ? )
( T12 ? )
( Y21 ? )
( Y11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40 )
( W11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44 )
( V11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43 )
( T11 ? )
( R11 ? )
( Y10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47 )
( W10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46 )
( U10 /FPGA_GPIOS/FPGA_BANK0_IO_56 )
( T10 ? )
( Y9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45 )
( W9 /FPGA_GPIOS/FPGA_BANK0_IO_50 )
)
( /4C7BC2A2/4CCF27AA 0402 R81 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM )
)
( /4C7BC2A2/4CCF27A9 0402 R80 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE# )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_WE# )
)
( /4C7BC2A2/4CCF27A8 0402 R82 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS )
)
( /4C7BC2A2/4CCF27A7 0402 R79 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS# )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS# )
)
( /4C7BC2A2/4CCF2733 0402 R83 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS# )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# )
)
( /4C7BC2A2/4CCF2730 0402 R86 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS )
)
( /4C7BC2A2/4CCF272F 0402 R84 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE# )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_WE# )
)
( /4C7BC2A2/4CCF272E 0402 R85 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM )
( 2 /DDR_Banks/M0_LDM )
)
( /4C7BC2A2/4C6B216E 0402 R23 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM )
( 2 /DDR_Banks/M0_UDM )
)
( /4C7BC2A2/4C6B216D 0402 R22 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS )
)
( /4C7BC2A2/4C6B216B 0402 R24 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE )
)
( /4C7BC2A2/4C6B1B90 0402 R21 120 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK )
( 2 /DDR_Banks/M0_CLK# )
)
( /4C7BC2A2/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A3 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A2 )
( 7 /DDR_Banks/M0_A1 )
( 8 /DDR_Banks/M0_A0 )
)
( /4C7BC2A2/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS# )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10 )
( 5 /DDR_Banks/M0_A10 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# )
)
( /4C7BC2A2/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4 )
( 5 /DDR_Banks/M0_A4 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A5 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A6 )
( 8 /DDR_Banks/M0_A7 )
)
( /4C7BC2A2/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8 )
( 5 /DDR_Banks/M0_A8 )
( 6 /DDR_Banks/M0_A9 )
( 7 /DDR_Banks/M0_A11 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A12 )
)
( /4C7BC2A2/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6 )
( 7 /DDR_Banks/M0_DQ5 )
( 8 /DDR_Banks/M0_DQ4 )
)
( /4C7BC2A2/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0 )
)
( /4C7BC2A2/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8 )
)
( /4C7BC2A2/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15 )
( 5 /DDR_Banks/M0_DQ15 )
( 6 /DDR_Banks/M0_DQ14 )
( 7 /DDR_Banks/M0_DQ13 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12 )
)
( /4C7BC2A2/4C69E7DD 0402 R19 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS )
)
( /4C7BC2A2/4C69E92D 0402 R20 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS# )
( 2 /DDR_Banks/M1_CS# )
)
( /4C7BC2A2/4C69E7F8 0402 R17 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE )
)
( /4C7BC2A2/4C69E7C2 0402 R18 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM )
( 2 /DDR_Banks/M1_UDM )
)
( /4C7BC2A2/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10 )
( 3 /DDR_Banks/M1_DQ9 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11 )
)
( /4C7BC2A2/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4}
( 1 /DDR_Banks/M1_DQ15 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14 )
( 3 /DDR_Banks/M1_DQ13 )
( 4 /DDR_Banks/M1_DQ12 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15 )
)
( /4C7BC2A2/4C69DF7A 0402 R16 120 {Lib=R}
( 1 /DDR_Banks/M1_CLK# )
( 2 /DDR_Banks/M1_CLK )
)
( /4C7BC2A2/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4}
( 1 /DDR_Banks/M1_A12 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A11 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12 )
)
( /4C7BC2A2/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A7 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A6 )
( 3 /DDR_Banks/M1_A5 )
( 4 /DDR_Banks/M1_A4 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7 )
)
( /4C7BC2A2/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3 )
( 5 /DDR_Banks/M1_DQ3 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0 )
)
( /4C7BC2A2/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4 )
)
( /4C7BC2A2/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS# )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A10 )
( 6 /DDR_Banks/M1_BA1 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS# )
)
( /4C7BC2A2/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3 )
( 5 /DDR_Banks/M1_A3 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A1 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A0 )
)
( /4C716A4D/4CB9E17F $noname FB2 FILTER {Lib=FILTER}
( 1 /DBG_PRG/5V_USB )
( 2 /DBG_PRG/VCC_USB )
)
( /4C716A4D/4CB9DE29 $noname C146 47pF {Lib=C}
( 1 N-000229 )
( 2 GND )
)
( /4C716A4D/4CB9DE25 $noname C147 47pF {Lib=C}
( 1 N-000210 )
( 2 GND )
)
( /4C716A4D/4CB9DDF8 $noname X1 6MHz {Lib=CRYSTAL}
( 1 N-000229 )
( 2 N-000210 )
)
( /4C716A4D/4CB9DDA3 $noname TP13 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DDA2 $noname TP14 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DDA1 $noname TP16 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DDA0 $noname TP15 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD9C $noname TP7 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD9B $noname TP8 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD9A $noname TP6 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD99 $noname TP5 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD95 $noname TP1 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD94 $noname TP2 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD93 $noname TP4 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD92 $noname TP3 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD7D $noname TP11 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD7C $noname TP12 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD67 $noname TP10 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9DD5B $noname TP9 CONN_1 {Lib=CONN_1}
( 1 ? )
)
( /4C716A4D/4CB9D9A7 $noname C150 10uF {Lib=CAPAPOL}
( 1 /DBG_PRG/VCC_USB )
( 2 GND )
)
( /4C716A4D/4CB9D313 $noname R69 1M {Lib=R}
( 1 /DBG_PRG/USB_CASE_FTDI )
( 2 GND )
)
( /4C716A4D/4CB9D312 $noname C145 4.7nF {Lib=C}
( 1 /DBG_PRG/USB_CASE_FTDI )
( 2 GND )
)
( /4C716A4D/4CB9D311 ZX62D-B-5P8 J8 ZX62D-B-5P8 {Lib=ZX62D-B-5P8}
( 1 /DBG_PRG/5V_USB )
( 2 /DBG_PRG/FTDI_USB_DM )
( 3 /DBG_PRG/FTDI_USB_DP )
( 4 N-000232 )
( 5 N-000232 )
( 6 /DBG_PRG/USB_CASE_FTDI )
( 7 /DBG_PRG/USB_CASE_FTDI )
( 8 /DBG_PRG/USB_CASE_FTDI )
( 9 /DBG_PRG/USB_CASE_FTDI )
)
( /4C716A4D/4CB9CA50 $noname FB1 FILTER {Lib=FILTER}
( 1 N-000232 )
( 2 GND )
)
( /4C716A4D/4CB9C9AD $noname C148 100nF {Lib=C}
( 1 /DBG_PRG/5V_USB )
( 2 GND )
)
( /4C716A4D/4CB9C9A3 $noname R74 470 {Lib=R}
( 1 /DBG_PRG/VCC_USB )
( 2 N-000211 )
)
( /4C716A4D/4CB9C996 $noname C151 100nF {Lib=C}
( 1 N-000211 )
( 2 GND )
)
( /4C716A4D/4CB9C965 $noname C149 33nF {Lib=C}
( 1 GND )
( 2 /DBG_PRG/3.3V_USB )
)
( /4C716A4D/4CB9C8F8 $noname R71 27 {Lib=R}
( 1 N-000239 )
( 2 /DBG_PRG/FTDI_USB_DP )
)
( /4C716A4D/4CB9C8F1 $noname R70 27 {Lib=R}
( 1 N-000238 )
( 2 /DBG_PRG/FTDI_USB_DM )
)
( /4C716A4D/4CB9C8E1 $noname R73 10K {Lib=R}
( 1 N-000236 )
( 2 /DBG_PRG/VCC_USB )
)
( /4C716A4D/4CB9C8D7 $noname R72 1.5K {Lib=R}
( 1 N-000237 )
( 2 N-000239 )
)
( /4C716A4D/4CB9C8AC $noname R76 10K {Lib=R}
( 1 /DBG_PRG/3.3V_USB )
( 2 N-000240 )
)
( /4C716A4D/4CB9C8A1 $noname R75 10K {Lib=R}
( 1 /DBG_PRG/3.3V_USB )
( 2 N-000235 )
)
( /4C716A4D/4CB9C4D7 ft2232c-LQFP IC1 FT2232D {Lib=FT2232C}
( 1 ? )
( 2 N-000236 )
( 3 /DBG_PRG/VCC_USB )
( 4 /DBG_PRG/VCC_USB )
( 5 N-000237 )
( 6 /DBG_PRG/3.3V_USB )
( 7 N-000239 )
( 8 N-000238 )
( 9 GND )
( 10 N-000235 )
( 11 ? )
( 12 ? )
( 13 ? )
( 14 /DBG_PRG/3.3V_USB )
( 15 ? )
( 16 ? )
( 17 ? )
( 18 GND )
( 19 ? )
( 20 ? )
( 21 /FPGA,_Port0,_Port2,_PROG_IF/S6_TMS )
( 22 /FPGA,_Port0,_Port2,_PROG_IF/S6_TDO )
( 23 /DBG_PRG/FPGA_TDI )
( 24 /DBG_PRG/FPGA_TCK )
( 25 GND )
( 26 N-000240 )
( 27 ? )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 /DBG_PRG/3.3V_USB )
( 32 ? )
( 33 ? )
( 34 GND )
( 35 ? )
( 36 ? )
( 37 /PSU/AVR_RST )
( 38 /DBG_PRG/AVR_MISO )
( 39 /PSU/AVR_MOSI )
( 40 /DBG_PRG/AVR_SCK )
( 41 ? )
( 42 /DBG_PRG/VCC_USB )
( 43 N-000229 )
( 44 N-000210 )
( 45 GND )
( 46 N-000211 )
( 47 GND )
( 48 ? )
)
( /4C69ED5F/4CC09483 $noname U25 TPS793XX {Lib=TPS793XX}
( 1 +BATT )
( 2 GND )
( 3 +BATT )
( 4 N-000177 )
( 5 N-000178 )
( 6 /PSU/VCCO2 )
)
( /4C69ED5F/4CC09482 $noname C154 22pF {Lib=C}
( 1 /PSU/VCCO2 )
( 2 N-000178 )
)
( /4C69ED5F/4CC09481 $noname C155 10uF {Lib=CAPAPOL}
( 1 /PSU/VCCO2 )
( 2 GND )
)
( /4C69ED5F/4CC09480 $noname R77 R {Lib=R}
( 1 /PSU/VCCO2 )
( 2 N-000178 )
)
( /4C69ED5F/4CC0947F $noname R78 R {Lib=R}
( 1 N-000178 )
( 2 GND )
)
( /4C69ED5F/4CC0947E $noname C153 10nF {Lib=C}
( 1 N-000177 )
( 2 GND )
)
( /4C69ED5F/4CC0947D $noname C152 10uF {Lib=CAPAPOL}
( 1 +BATT )
( 2 GND )
)
( /4C69ED5F/4C7FD266 0402 C104 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C69ED5F/4C7FD244 $noname R57 15K {Lib=R}
( 1 /PSU/AVR_RST )
( 2 +3.3V )
)
( /4C69ED5F/4C7FC13A $noname R56 R {Lib=R}
( 1 /PSU/3.3V_EN )
( 2 /PSU/VIN_DC-DC-3.3 )
)
( /4C69ED5F/4C7FC041 $noname R58 1M {Lib=R}
( 1 /PSU/1.2V_EN )
( 2 /PSU/VIN_DC-DC-1.2 )
)
( /4C69ED5F/4C7D02E3 MLP6 U17 FAN4010 {Lib=FAN4010}
( 1 +BATT )
( 2 ? )
( 3 /PSU/lout_2.5 )
( 5 GND )
( 6 /PSU/VIN_DC-DC-2.5 )
)
( /4C69ED5F/4C7D02E2 1206 R45 R {Lib=R}
( 1 /PSU/VIN_DC-DC-2.5 )
( 2 +BATT )
)
( /4C69ED5F/4C7D02E1 0402 R44 R {Lib=R}
( 1 /PSU/lout_2.5 )
( 2 GND )
)
( /4C69ED5F/4C7C4DAA $noname R41 160K {Lib=R}
( 1 /PSU/2.5V_EN )
( 2 GND )
)
( /4C69ED5F/4C7C4D9E $noname R40 47K {Lib=R}
( 1 N-000182 )
( 2 N-000173 )
)
( /4C69ED5F/4C7C4D94 $noname C100 220pF {Lib=C}
( 1 N-000173 )
( 2 GND )
)
( /4C69ED5F/4C7C4D8E $noname C99 22uF {Lib=C}
( 1 /PSU/VIN_DC-DC-2.5 )
( 2 GND )
)
( /4C69ED5F/4C7C4CF1 0402 C103 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C69ED5F/4C7C4CF0 1210 L11 2.2uH {Lib=INDUCTOR}
( 1 +2.5V )
( 2 /PSU/SW_2.5 )
)
( /4C69ED5F/4C7C4CEF 0402 R43 51K {Lib=R}
( 1 +2.5V )
( 2 /PSU/VFB2.5 )
)
( /4C69ED5F/4C7C4CEE 0402 R42 24K {Lib=R}
( 1 /PSU/VFB2.5 )
( 2 GND )
)
( /4C69ED5F/4C7C4CED 1206 C102 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C69ED5F/4C7C4CEC 0402 C101 22pF {Lib=CAP}
( 1 +2.5V )
( 2 /PSU/VFB2.5 )
)
( /4C69ED5F/4C79C99E 0805 C95 4.7uF {Lib=CAP}
( 1 /PSU/VIN_DC-DC-5.0 )
( 2 GND )
)
( /4C69ED5F/4C79C99C 0402 R35 R {Lib=R}
( 1 /PSU/lout_5.0 )
( 2 GND )
)
( /4C69ED5F/4C79C99B 1206 R36 R {Lib=R}
( 1 /PSU/VIN_DC-DC-5.0 )
( 2 +BATT )
)
( /4C69ED5F/4C79C99A MLP6 U16 FAN4010 {Lib=FAN4010}
( 1 +BATT )
( 2 ? )
( 3 /PSU/lout_5.0 )
( 5 GND )
( 6 /PSU/VIN_DC-DC-5.0 )
)
( /4C69ED5F/4C79C8B2 0402 C98 100nF {Lib=CAP}
( 1 +5V )
( 2 GND )
)
( /4C69ED5F/4C79C8B1 0402 R39 1.02M {Lib=R}
( 1 +5V )
( 2 /PSU/VFB5.0 )
)
( /4C69ED5F/4C79C8B0 0402 R38 332K {Lib=R}
( 1 /PSU/VFB5.0 )
( 2 GND )
)
( /4C69ED5F/4C79C8AF 1206 C97 10uF {Lib=CAP}
( 1 +5V )
( 2 GND )
)
( /4C69ED5F/4C79C8AE 0402 C96 22pF {Lib=CAP}
( 1 +5V )
( 2 /PSU/VFB5.0 )
)
( /4C69ED5F/4C79C828 1210 L10 4.7uH {Lib=INDUCTOR}
( 1 N-000170 )
( 2 /PSU/VIN_DC-DC-5.0 )
)
( /4C69ED5F/4C79C7C0 0402 R37 1M {Lib=R}
( 1 /PSU/5V_EN )
( 2 /PSU/VIN_DC-DC-5.0 )
)
( /4C69ED5F/4C79C65B SOT23_6 U15 A7117 {Lib=A7117}
( 1 N-000170 )
( 2 GND )
( 3 /PSU/VFB5.0 )
( 4 /PSU/5V_EN )
( 5 +5V )
( 6 /PSU/VIN_DC-DC-5.0 )
)
( /4C69ED5F/4C770714 MLP6 U14 FAN4010 {Lib=FAN4010}
( 1 +BATT )
( 2 ? )
( 3 /PSU/Iout_1.2 )
( 5 GND )
( 6 /PSU/VIN_DC-DC-1.2 )
)
( /4C69ED5F/4C770713 1206 R34 R {Lib=R}
( 1 /PSU/VIN_DC-DC-1.2 )
( 2 +BATT )
)
( /4C69ED5F/4C770712 0402 R33 R {Lib=R}
( 1 /PSU/Iout_1.2 )
( 2 GND )
)
( /4C69ED5F/4C77067B 0402 R31 R {Lib=R}
( 1 /PSU/lout_3.3 )
( 2 GND )
)
( /4C69ED5F/4C77060E 1206 R32 R {Lib=R}
( 1 /PSU/VIN_DC-DC-3.3 )
( 2 +BATT )
)
( /4C69ED5F/4C7705B0 MLP6 U13 FAN4010 {Lib=FAN4010}
( 1 +BATT )
( 2 ? )
( 3 /PSU/lout_3.3 )
( 5 GND )
( 6 /PSU/VIN_DC-DC-3.3 )
)
( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF {Lib=CAP}
( 1 /PSU/VIN_DC-DC-1.2 )
( 2 GND )
)
( /4C69ED5F/4C6D2FD6 0402 C83 22pF {Lib=CAP}
( 1 +1.2V )
( 2 /PSU/VFB1.2 )
)
( /4C69ED5F/4C6D2FD5 1206 C84 10uF {Lib=CAP}
( 1 +1.2V )
( 2 GND )
)
( /4C69ED5F/4C6D2FD3 0402 R27 200K {Lib=R}
( 1 /PSU/VFB1.2 )
( 2 GND )
)
( /4C69ED5F/4C6D2FD2 0402 R28 200K {Lib=R}
( 1 +1.2V )
( 2 /PSU/VFB1.2 )
)
( /4C69ED5F/4C6D2FD1 1210 L9 2.2uH {Lib=INDUCTOR}
( 1 +1.2V )
( 2 /PSU/SW_1.2 )
)
( /4C69ED5F/4C6D2FD0 0402 C85 100nF {Lib=CAP}
( 1 +1.2V )
( 2 GND )
)
( /4C69ED5F/4C6D2F0B 0402 C81 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C69ED5F/4C6D2E6A 1210 L8 2.2uH {Lib=INDUCTOR}
( 1 +3.3V )
( 2 /PSU/SW_3.3 )
)
( /4C69ED5F/4C6D2DDD 0402 R26 900K {Lib=R}
( 1 +3.3V )
( 2 /PSU/VFB3.3 )
)
( /4C69ED5F/4C6D2DBC 0402 R25 200K {Lib=R}
( 1 /PSU/VFB3.3 )
( 2 GND )
)
( /4C69ED5F/4C6D2C83 1206 C80 10uF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C69ED5F/4C6D2C7F 0402 C79 22pF {Lib=CAP}
( 1 +3.3V )
( 2 /PSU/VFB3.3 )
)
( /4C69ED5F/4C6D2C7C 0805 C78 4.7uF {Lib=CAP}
( 1 /PSU/VIN_DC-DC-3.3 )
( 2 GND )
)
( /4C69ED5F/4C6D2AE0 SOT23-5 U12 A7108 {Lib=A7108}
( 1 /PSU/1.2V_EN )
( 2 GND )
( 3 /PSU/SW_1.2 )
( 4 /PSU/VIN_DC-DC-1.2 )
( 5 /PSU/VFB1.2 )
)
( /4C69ED5F/4C6D2AA5 SOT23-5 U11 A7108 {Lib=A7108}
( 1 /PSU/3.3V_EN )
( 2 GND )
( 3 /PSU/SW_3.3 )
( 4 /PSU/VIN_DC-DC-3.3 )
( 5 /PSU/VFB3.3 )
)
( /4C69ED5F/4C6C9DB9 DFN10 U10 A7130 {Lib=A7130}
( PAD GND )
( 1 /PSU/2.5V_EN )
( 2 GND )
( 3 /PSU/SW_2.5 )
( 4 /PSU/SW_2.5 )
( 5 GND )
( 6 /PSU/VIN_DC-DC-2.5 )
( 7 /PSU/VIN_DC-DC-2.5 )
( 8 /PSU/VIN_DC-DC-2.5 )
( 9 /PSU/VFB2.5 )
( 10 N-000182 )
)
( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF}
( PAD GND )
( 1 /DBG_PRG/AVR_SCK )
( 2 /PSU/Iout_1.2 )
( 3 /PSU/1.2V_EN )
( 4 /PSU/lout_3.3 )
( 5 /PSU/3.3V_EN )
( 6 ? )
( 7 ? )
( 8 GND )
( 9 +3.3V )
( 10 ? )
( 11 /PSU/lout_2.5 )
( 12 /PSU/2.5V_EN )
( 13 /PSU/AVR_RST )
( 14 /PSU/lout_5.0 )
( 15 /PSU/5V_EN )
( 16 /PSU/AVR_MOSI )
( 17 ? )
( 18 ? )
( 19 ? )
( 20 /DBG_PRG/AVR_MISO )
)
( /4C4227FE/4C6969AB $noname C75 100nF {Lib=C}
( 1 GND )
( 2 +3.3V )
)
( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D67C 0402 C73 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D661 0402 C72 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB}
( 1 /Non_volatile_memories/SPI_FLASH_CS# )
( 2 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 )
( 3 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 )
( 4 GND )
( 5 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0 )
( 6 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK )
( 7 /Non_volatile_memories/SPI_DQ3 )
( 8 /PSU/VCCO2 )
)
( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD}
( CASE GND )
( COM GND )
( CD ? )
( 1 /Non_volatile_memories/SD_DAT2 )
( 2 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3 )
( 3 /Non_volatile_memories/SD_CMD )
( 4 +3.3V )
( 5 /Non_volatile_memories/SD_CLK )
( 6 GND )
( 7 /Non_volatile_memories/SD_DAT0 )
( 8 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT1 )
)
( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M}
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 /Non_volatile_memories/NF_RNB )
( 7 /Non_volatile_memories/NF_RNB )
( 8 /Non_volatile_memories/NF_RE_N )
( 9 /Non_volatile_memories/NF_CS1_N )
( 10 ? )
( 11 ? )
( 12 +3.3V )
( 13 GND )
( 14 ? )
( 15 ? )
( 16 /FPGA,_Port0,_Port2,_PROG_IF/NF_CLE )
( 17 /FPGA,_Port0,_Port2,_PROG_IF/NF_ALE )
( 18 /Non_volatile_memories/NF_WE_N )
( 19 +3.3V )
( 20 ? )
( 21 ? )
( 22 ? )
( 23 ? )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 ? )
( 29 /FPGA,_Port0,_Port2,_PROG_IF/NF_D0 )
( 30 /FPGA,_Port0,_Port2,_PROG_IF/NF_D1 )
( 31 /Non_volatile_memories/NF_D2 )
( 32 /Non_volatile_memories/NF_D3 )
( 33 ? )
( 34 ? )
( 35 ? )
( 36 GND )
( 37 +3.3V )
( 38 ? )
( 39 ? )
( 40 ? )
( 41 /FPGA,_Port0,_Port2,_PROG_IF/NF_D4 )
( 42 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 )
( 43 /FPGA,_Port0,_Port2,_PROG_IF/NF_D6 )
( 44 /FPGA,_Port0,_Port2,_PROG_IF/NF_D7 )
( 45 ? )
( 46 ? )
( 47 ? )
( 48 ? )
)
( /4C5F1EDC/4C7D3661 $noname R53 15k {Lib=R}
( 1 GND )
( 2 /USB/USBD_D+ )
)
( /4C5F1EDC/4C7D3660 $noname R54 15k {Lib=R}
( 1 GND )
( 2 /USB/USBD_D- )
)
( /4C5F1EDC/4C7D365F $noname R55 15k {Lib=R}
( 1 +3.3V )
( 2 /USB/USBD_D+ )
)
( /4C5F1EDC/4C7D354D $noname R49 24 {Lib=R}
( 1 /USB/USBD_D+ )
( 2 N-000155 )
)
( /4C5F1EDC/4C7D354C $noname R50 24 {Lib=R}
( 1 /USB/USBD_D- )
( 2 N-000152 )
)
( /4C5F1EDC/4C7D350E $noname R52 24 {Lib=R}
( 1 /USB/USBA_D- )
( 2 N-000154 )
)
( /4C5F1EDC/4C7D3508 $noname R51 24 {Lib=R}
( 1 /USB/USBA_D+ )
( 2 N-000153 )
)
( /4C5F1EDC/4C7D32A3 $noname R48 15k {Lib=R}
( 1 +3.3V )
( 2 /USB/USBA_D+ )
)
( /4C5F1EDC/4C7D3098 $noname R47 15k {Lib=R}
( 1 GND )
( 2 /USB/USBA_D+ )
)
( /4C5F1EDC/4C7D3075 $noname R46 15k {Lib=R}
( 1 GND )
( 2 /USB/USBA_D- )
)
( /4C5F1EDC/4C75F027 ZX62D-B-5P8 J7 ZX62D-B-5P8 {Lib=ZX62D-B-5P8}
( 1 N-000162 )
( 2 /USB/USBD_D- )
( 3 /USB/USBD_D+ )
( 4 N-000156 )
( 5 N-000156 )
( 6 /USB/USB_CASE_DEV )
( 7 /USB/USB_CASE_DEV )
( 8 /USB/USB_CASE_DEV )
( 9 /USB/USB_CASE_DEV )
)
( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF {Lib=MIC2550-MLF}
( 1 /USB/USBD_SPD )
( 2 /USB/USBD_RCV )
( 3 /USB/USBD_VP )
( 4 /USB/USBD_VM )
( 6 GND )
( 7 GND )
( 9 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N )
( 10 N-000152 )
( 11 N-000155 )
( 12 +3.3V )
( 14 +3.3V )
( 15 +2.5V )
)
( /4C5F1EDC/4C71BA1D MLF16 U6 MIC2550-MLF {Lib=MIC2550-MLF}
( 1 /USB/USBA_SPD )
( 2 /USB/USBA_RCV )
( 3 /USB/USBA_VP )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM )
( 6 GND )
( 7 GND )
( 9 /USB/USBA_OE_N )
( 10 N-000154 )
( 11 N-000153 )
( 12 +3.3V )
( 14 +3.3V )
( 15 +2.5V )
)
( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BD 0402 C36 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BC 0402 C37 100nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03}
( 1 /USB/USBD_D- )
( 2 GND )
)
( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03}
( 1 /USB/USBD_D+ )
( 2 GND )
)
( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C}
( 1 /USB/USB_CASE_DEV )
( 2 GND )
)
( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R}
( 1 /USB/USB_CASE_DEV )
( 2 GND )
)
( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR}
( 1 N-000162 )
( 2 GND )
)
( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR}
( 1 N-000160 )
( 2 N-000159 )
)
( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR}
( 1 N-000158 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R}
( 1 /USB/USB_CASE_HOST )
( 2 GND )
)
( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C}
( 1 /USB/USB_CASE_HOST )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 {Lib=V0402MHS03}
( 1 /USB/USBA_D+ )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 {Lib=V0402MHS03}
( 1 /USB/USBA_D- )
( 2 GND )
)
( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F}
( 1 N-000160 )
( 2 +5V )
)
( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001}
( S1 /USB/USB_CASE_HOST )
( S2 /USB/USB_CASE_HOST )
( S3 /USB/USB_CASE_HOST )
( S4 /USB/USB_CASE_HOST )
( 1 N-000159 )
( 2 /USB/USBA_D- )
( 3 /USB/USBA_D+ )
( 4 N-000158 )
)
( /4C5F1EDC/4C5F2039 $noname C15 100nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C5F2037 0402 C14 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D8114 $noname C9 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_PLL1.8V )
( 2 GND )
)
( /4C4320F3/4C5D810A 0402 L3 FB {Lib=INDUCTOR}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 /Ethernet_Phy/ETH_PLL1.8V )
)
( /4C4320F3/4C5D8104 $noname C6 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 GND )
)
( /4C4320F3/4C5D80F3 0402 L1 FB {Lib=INDUCTOR}
( 1 /Ethernet_Phy/ETH_1.8V )
( 2 /Ethernet_Phy/ETH_A1.8V )
)
( /4C4320F3/4C5D80F0 $noname C4 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_1.8V )
( 2 GND )
)
( /4C4320F3/4C5D80ED $noname C2 1uF {Lib=C}
( 1 /Ethernet_Phy/ETH_1.8V )
( 2 GND )
)
( /4C4320F3/4C5D7FB7 0402 L2 FB {Lib=INDUCTOR}
( 1 +3.3V )
( 2 /Ethernet_Phy/ETH_A3.3V )
)
( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R}
( 1 /Ethernet_Phy/ETH_MDIO )
( 2 +3.3V )
)
( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R}
( 1 N-000138 )
( 2 GND )
)
( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C}
( 1 /Ethernet_Phy/MAG_SHIELD )
( 2 GND )
)
( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R}
( 1 /Ethernet_Phy/MAG_SHIELD )
( 2 GND )
)
( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001}
( 1 /Ethernet_Phy/ETH_MDIO )
( 2 /Ethernet_Phy/ETH_MDC )
( 3 /Ethernet_Phy/ETH_RXD3 )
( 4 /Ethernet_Phy/ETH_RXD2 )
( 5 /Ethernet_Phy/ETH_RXD1 )
( 6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 )
( 7 +3.3V )
( 8 GND )
( 9 /Ethernet_Phy/ETH_RXDV )
( 10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC )
( 11 /Ethernet_Phy/ETH_RXER )
( 12 GND )
( 13 /Ethernet_Phy/ETH_1.8V )
( 14 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER )
( 15 /Ethernet_Phy/ETH_TXC )
( 16 /Ethernet_Phy/ETH_TXEN )
( 17 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 )
( 18 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1 )
( 19 /Ethernet_Phy/ETH_TXD2 )
( 20 /Ethernet_Phy/ETH_TXD3 )
( 21 /Ethernet_Phy/ETH_COL )
( 22 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS )
( 23 GND )
( 24 +3.3V )
( 25 /Ethernet_Phy/ETH_INT )
( 26 /Ethernet_Phy/ETH_LED0 )
( 27 /Ethernet_Phy/ETH_LED1 )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 /Ethernet_Phy/ETH_A1.8V )
( 32 /Ethernet_Phy/MAG_RX- )
( 33 /Ethernet_Phy/MAG_RX+ )
( 34 ? )
( 35 GND )
( 36 GND )
( 37 N-000138 )
( 38 /Ethernet_Phy/ETH_A3.3V )
( 39 GND )
( 40 /Ethernet_Phy/MAG_TX- )
( 41 /Ethernet_Phy/MAG_TX+ )
( 42 ? )
( 43 ? )
( 44 GND )
( 45 ? )
( 46 /Ethernet_Phy/ETH_CLK )
( 47 /Ethernet_Phy/ETH_PLL1.8V )
( 48 /Ethernet_Phy/ETH_RST_N )
)
( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R}
( 1 +3.3V )
( 2 /Ethernet_Phy/MAG_TX+ )
)
( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R}
( 1 +3.3V )
( 2 /Ethernet_Phy/MAG_TX- )
)
( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R}
( 1 +3.3V )
( 2 /Ethernet_Phy/MAG_RX- )
)
( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R}
( 1 +3.3V )
( 2 /Ethernet_Phy/MAG_RX+ )
)
( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R}
( 1 N-000149 )
( 2 /Ethernet_Phy/ETH_LED1 )
)
( /4C4320F3/4C5D719D $noname R7 220 {Lib=R}
( 1 N-000148 )
( 2 /Ethernet_Phy/ETH_LED0 )
)
( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025}
( 1 /Ethernet_Phy/MAG_TX+ )
( 2 /Ethernet_Phy/MAG_TX- )
( 3 +3.3V )
( 4 GND )
( 5 GND )
( 6 +3.3V )
( 7 /Ethernet_Phy/MAG_RX+ )
( 8 /Ethernet_Phy/MAG_RX- )
( 9 +3.3V )
( 10 N-000148 )
( 11 +3.3V )
( 12 N-000149 )
( 13 /Ethernet_Phy/MAG_SHIELD )
( 14 /Ethernet_Phy/MAG_SHIELD )
)
( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0 )
( 3 +2.5V )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2 )
( 6 GND )
( 7 /DDR_Banks/M1_DQ3 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4 )
( 9 +2.5V )
( 10 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 )
( 11 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 )
( 12 GND )
( 13 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM )
( 21 /FPGA_Port_1,_Port_3_DDR,_USB/M1_WE# )
( 22 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS# )
( 23 /FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS# )
( 24 /DDR_Banks/M1_CS# )
( 25 ? )
( 26 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0 )
( 27 /DDR_Banks/M1_BA1 )
( 28 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A10 )
( 29 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A0 )
( 30 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A1 )
( 31 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 )
( 32 /DDR_Banks/M1_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /DDR_Banks/M1_A4 )
( 36 /DDR_Banks/M1_A5 )
( 37 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A6 )
( 38 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A7 )
( 39 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 )
( 40 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 )
( 41 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A11 )
( 42 /DDR_Banks/M1_A12 )
( 43 ? )
( 44 /DDR_Banks/M1_CLK# )
( 45 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE )
( 46 /DDR_Banks/M1_CLK )
( 47 /DDR_Banks/M1_UDM )
( 48 GND )
( 49 /DDR_Banks/M1_VREF )
( 50 ? )
( 51 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS )
( 52 GND )
( 53 ? )
( 54 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 )
( 55 +2.5V )
( 56 /DDR_Banks/M1_DQ9 )
( 57 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10 )
( 58 GND )
( 59 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 )
( 60 /DDR_Banks/M1_DQ12 )
( 61 +2.5V )
( 62 /DDR_Banks/M1_DQ13 )
( 63 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14 )
( 64 GND )
( 65 /DDR_Banks/M1_DQ15 )
( 66 GND )
)
( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D151 1206 C33 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R}
( 1 +2.5V )
( 2 /DDR_Banks/M1_VREF )
)
( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R}
( 1 /DDR_Banks/M1_VREF )
( 2 GND )
)
( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R}
( 1 /DDR_Banks/M0_VREF )
( 2 GND )
)
( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R}
( 1 +2.5V )
( 2 /DDR_Banks/M0_VREF )
)
( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP}
( 1 +2.5V )
( 2 /DDR_Banks/M1_VREF )
)
( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP}
( 1 /DDR_Banks/M1_VREF )
( 2 GND )
)
( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP}
( 1 /DDR_Banks/M0_VREF )
( 2 GND )
)
( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP}
( 1 +2.5V )
( 2 /DDR_Banks/M0_VREF )
)
( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0 )
( 3 +2.5V )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2 )
( 6 GND )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 )
( 8 /DDR_Banks/M0_DQ4 )
( 9 +2.5V )
( 10 /DDR_Banks/M0_DQ5 )
( 11 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6 )
( 12 GND )
( 13 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /DDR_Banks/M0_LDM )
( 21 /FPGA_Port_1,_Port_3_DDR,_USB/M0_WE# )
( 22 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# )
( 23 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# )
( 24 GND )
( 25 ? )
( 26 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0 )
( 27 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1 )
( 28 /DDR_Banks/M0_A10 )
( 29 /DDR_Banks/M0_A0 )
( 30 /DDR_Banks/M0_A1 )
( 31 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A2 )
( 32 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /DDR_Banks/M0_A4 )
( 36 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A5 )
( 37 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A6 )
( 38 /DDR_Banks/M0_A7 )
( 39 /DDR_Banks/M0_A8 )
( 40 /DDR_Banks/M0_A9 )
( 41 /DDR_Banks/M0_A11 )
( 42 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A12 )
( 43 ? )
( 44 /DDR_Banks/M0_CLK# )
( 45 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE )
( 46 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK )
( 47 /DDR_Banks/M0_UDM )
( 48 GND )
( 49 /DDR_Banks/M0_VREF )
( 50 ? )
( 51 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS )
( 52 GND )
( 53 ? )
( 54 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8 )
( 55 +2.5V )
( 56 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 )
( 57 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10 )
( 58 GND )
( 59 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11 )
( 60 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12 )
( 61 +2.5V )
( 62 /DDR_Banks/M0_DQ13 )
( 63 /DDR_Banks/M0_DQ14 )
( 64 GND )
( 65 /DDR_Banks/M0_DQ15 )
( 66 GND )
)
)
*
{ Allowed footprints by component:
$component C140
SM*
C?
C1-1
$endlist
$component C142
SM*
C?
C1-1
$endlist
$component C144
CP*
SM*
$endlist
$component C143
SM*
C?
C1-1
$endlist
$component C141
SM*
C?
C1-1
$endlist
$component C136
SM*
C?
C1-1
$endlist
$component C138
SM*
C?
C1-1
$endlist
$component C139
CP*
SM*
$endlist
$component C137
SM*
C?
C1-1
$endlist
$component C133
SM*
C?
C1-1
$endlist
$component C135
CP*
SM*
$endlist
$component C134
SM*
C?
C1-1
$endlist
$component C131
SM*
C?
C1-1
$endlist
$component C132
CP*
SM*
$endlist
$component C130
CP*
SM*
$endlist
$component C129
SM*
C?
C1-1
$endlist
$component C107
CP*
SM*
$endlist
$component C110
SM*
C?
C1-1
$endlist
$component R64
R?
SM0603
SM0805
$endlist
$component R63
R?
SM0603
SM0805
$endlist
$component C116
CP*
SM*
$endlist
$component C113
SM*
C?
C1-1
$endlist
$component C125
SM*
C?
C1-1
$endlist
$component C128
CP*
SM*
$endlist
$component R67
R?
SM0603
SM0805
$endlist
$component R68
R?
SM0603
SM0805
$endlist
$component C121
SM*
C?
C1-1
$endlist
$component C118
CP*
SM*
$endlist
$component C117
CP*
SM*
$endlist
$component C120
SM*
C?
C1-1
$endlist
$component R66
R?
SM0603
SM0805
$endlist
$component R65
R?
SM0603
SM0805
$endlist
$component C127
CP*
SM*
$endlist
$component C124
SM*
C?
C1-1
$endlist
$component C112
SM*
C?
C1-1
$endlist
$component C115
CP*
SM*
$endlist
$component R61
R?
SM0603
SM0805
$endlist
$component R62
R?
SM0603
SM0805
$endlist
$component C109
SM*
C?
C1-1
$endlist
$component C106
CP*
SM*
$endlist
$component C105
CP*
SM*
$endlist
$component C108
SM*
C?
C1-1
$endlist
$component R60
R?
SM0603
SM0805
$endlist
$component R59
R?
SM0603
SM0805
$endlist
$component C114
CP*
SM*
$endlist
$component C111
SM*
C?
C1-1
$endlist
$component C94
SM*
C?
C1-1
$endlist
$component C92
SM*
C?
C1-1
$endlist
$component C93
SM*
C?
C1-1
$endlist
$component C91
SM*
C?
C1-1
$endlist
$component C90
SM*
C?
C1-1
$endlist
$component R30
R?
SM0603
SM0805
$endlist
$component R29
R?
SM0603
SM0805
$endlist
$component C77
SM*
C?
C1-1
$endlist
$component C76
SM*
C?
C1-1
$endlist
$component C66
SM*
C?
C1-1
$endlist
$component C63
SM*
C?
C1-1
$endlist
$component C60
SM*
C?
C1-1
$endlist
$component C57
SM*
C?
C1-1
$endlist
$component C54
SM*
C?
C1-1
$endlist
$component C69
SM*
C?
C1-1
$endlist
$component C67
SM*
C?
C1-1
$endlist
$component C64
SM*
C?
C1-1
$endlist
$component C61
SM*
C?
C1-1
$endlist
$component C58
SM*
C?
C1-1
$endlist
$component C55
SM*
C?
C1-1
$endlist
$component C68
SM*
C?
C1-1
$endlist
$component C65
SM*
C?
C1-1
$endlist
$component C62
SM*
C?
C1-1
$endlist
$component C59
SM*
C?
C1-1
$endlist
$component C56
SM*
C?
C1-1
$endlist
$component C50
SM*
C?
C1-1
$endlist
$component C47
SM*
C?
C1-1
$endlist
$component C44
SM*
C?
C1-1
$endlist
$component C41
SM*
C?
C1-1
$endlist
$component C53
SM*
C?
C1-1
$endlist
$component C51
SM*
C?
C1-1
$endlist
$component C49
SM*
C?
C1-1
$endlist
$component C46
SM*
C?
C1-1
$endlist
$component C52
SM*
C?
C1-1
$endlist
$component C43
SM*
C?
C1-1
$endlist
$component C40
SM*
C?
C1-1
$endlist
$component C48
SM*
C?
C1-1
$endlist
$component C45
SM*
C?
C1-1
$endlist
$component C42
SM*
C?
C1-1
$endlist
$component C39
SM*
C?
C1-1
$endlist
$component R81
R?
SM0603
SM0805
$endlist
$component R80
R?
SM0603
SM0805
$endlist
$component R82
R?
SM0603
SM0805
$endlist
$component R79
R?
SM0603
SM0805
$endlist
$component R83
R?
SM0603
SM0805
$endlist
$component R86
R?
SM0603
SM0805
$endlist
$component R84
R?
SM0603
SM0805
$endlist
$component R85
R?
SM0603
SM0805
$endlist
$component R23
R?
SM0603
SM0805
$endlist
$component R22
R?
SM0603
SM0805
$endlist
$component R24
R?
SM0603
SM0805
$endlist
$component R21
R?
SM0603
SM0805
$endlist
$component R19
R?
SM0603
SM0805
$endlist
$component R20
R?
SM0603
SM0805
$endlist
$component R17
R?
SM0603
SM0805
$endlist
$component R18
R?
SM0603
SM0805
$endlist
$component R16
R?
SM0603
SM0805
$endlist
$component C146
SM*
C?
C1-1
$endlist
$component C147
SM*
C?
C1-1
$endlist
$component C150
CP*
SM*
$endlist
$component R69
R?
SM0603
SM0805
$endlist
$component C145
SM*
C?
C1-1
$endlist
$component C148
SM*
C?
C1-1
$endlist
$component R74
R?
SM0603
SM0805
$endlist
$component C151
SM*
C?
C1-1
$endlist
$component C149
SM*
C?
C1-1
$endlist
$component R71
R?
SM0603
SM0805
$endlist
$component R70
R?
SM0603
SM0805
$endlist
$component R73
R?
SM0603
SM0805
$endlist
$component R72
R?
SM0603
SM0805
$endlist
$component R76
R?
SM0603
SM0805
$endlist
$component R75
R?
SM0603
SM0805
$endlist
$component C154
SM*
C?
C1-1
$endlist
$component C155
CP*
SM*
$endlist
$component R77
R?
SM0603
SM0805
$endlist
$component R78
R?
SM0603
SM0805
$endlist
$component C153
SM*
C?
C1-1
$endlist
$component C152
CP*
SM*
$endlist
$component C104
SM*
C?
C1-1
$endlist
$component R57
R?
SM0603
SM0805
$endlist
$component R56
R?
SM0603
SM0805
$endlist
$component R58
R?
SM0603
SM0805
$endlist
$component R45
R?
SM0603
SM0805
$endlist
$component R44
R?
SM0603
SM0805
$endlist
$component R41
R?
SM0603
SM0805
$endlist
$component R40
R?
SM0603
SM0805
$endlist
$component C100
SM*
C?
C1-1
$endlist
$component C99
SM*
C?
C1-1
$endlist
$component C103
SM*
C?
C1-1
$endlist
$component R43
R?
SM0603
SM0805
$endlist
$component R42
R?
SM0603
SM0805
$endlist
$component C102
SM*
C?
C1-1
$endlist
$component C101
SM*
C?
C1-1
$endlist
$component C95
SM*
C?
C1-1
$endlist
$component R35
R?
SM0603
SM0805
$endlist
$component R36
R?
SM0603
SM0805
$endlist
$component C98
SM*
C?
C1-1
$endlist
$component R39
R?
SM0603
SM0805
$endlist
$component R38
R?
SM0603
SM0805
$endlist
$component C97
SM*
C?
C1-1
$endlist
$component C96
SM*
C?
C1-1
$endlist
$component R37
R?
SM0603
SM0805
$endlist
$component R34
R?
SM0603
SM0805
$endlist
$component R33
R?
SM0603
SM0805
$endlist
$component R31
R?
SM0603
SM0805
$endlist
$component R32
R?
SM0603
SM0805
$endlist
$component C82
SM*
C?
C1-1
$endlist
$component C83
SM*
C?
C1-1
$endlist
$component C84
SM*
C?
C1-1
$endlist
$component R27
R?
SM0603
SM0805
$endlist
$component R28
R?
SM0603
SM0805
$endlist
$component C85
SM*
C?
C1-1
$endlist
$component C81
SM*
C?
C1-1
$endlist
$component R26
R?
SM0603
SM0805
$endlist
$component R25
R?
SM0603
SM0805
$endlist
$component C80
SM*
C?
C1-1
$endlist
$component C79
SM*
C?
C1-1
$endlist
$component C78
SM*
C?
C1-1
$endlist
$component C75
SM*
C?
C1-1
$endlist
$component C74
SM*
C?
C1-1
$endlist
$component C73
SM*
C?
C1-1
$endlist
$component C72
SM*
C?
C1-1
$endlist
$component R53
R?
SM0603
SM0805
$endlist
$component R54
R?
SM0603
SM0805
$endlist
$component R55
R?
SM0603
SM0805
$endlist
$component R49
R?
SM0603
SM0805
$endlist
$component R50
R?
SM0603
SM0805
$endlist
$component R52
R?
SM0603
SM0805
$endlist
$component R51
R?
SM0603
SM0805
$endlist
$component R48
R?
SM0603
SM0805
$endlist
$component R47
R?
SM0603
SM0805
$endlist
$component R46
R?
SM0603
SM0805
$endlist
$component C35
SM*
C?
C1-1
$endlist
$component C36
SM*
C?
C1-1
$endlist
$component C37
SM*
C?
C1-1
$endlist
$component C38
SM*
C?
C1-1
$endlist
$component R15
R?
SM0603
SM0805
$endlist
$component R10
R?
SM0603
SM0805
$endlist
$component C16
SM*
C?
C1-1
$endlist
$component C15
SM*
C?
C1-1
$endlist
$component C14
SM*
C?
C1-1
$endlist
$component C13
SM*
C?
C1-1
$endlist
$component C9
SM*
C?
C1-1
$endlist
$component C6
SM*
C?
C1-1
$endlist
$component C4
SM*
C?
C1-1
$endlist
$component C2
SM*
C?
C1-1
$endlist
$component C8
SM*
C?
C1-1
$endlist
$component C7
SM*
C?
C1-1
$endlist
$component C5
SM*
C?
C1-1
$endlist
$component C3
SM*
C?
C1-1
$endlist
$component C1
SM*
C?
C1-1
$endlist
$component R1
R?
SM0603
SM0805
$endlist
$component R2
R?
SM0603
SM0805
$endlist
$component C11
SM*
C?
C1-1
$endlist
$component C10
SM*
C?
C1-1
$endlist
$component C12
SM*
C?
C1-1
$endlist
$component R9
R?
SM0603
SM0805
$endlist
$component R3
R?
SM0603
SM0805
$endlist
$component R4
R?
SM0603
SM0805
$endlist
$component R6
R?
SM0603
SM0805
$endlist
$component R5
R?
SM0603
SM0805
$endlist
$component R8
R?
SM0603
SM0805
$endlist
$component R7
R?
SM0603
SM0805
$endlist
$component C70
SM*
C?
C1-1
$endlist
$component C71
SM*
C?
C1-1
$endlist
$component C34
SM*
C?
C1-1
$endlist
$component C33
SM*
C?
C1-1
$endlist
$component C28
SM*
C?
C1-1
$endlist
$component C29
SM*
C?
C1-1
$endlist
$component C31
SM*
C?
C1-1
$endlist
$component C30
SM*
C?
C1-1
$endlist
$component C32
SM*
C?
C1-1
$endlist
$component C27
SM*
C?
C1-1
$endlist
$component C21
SM*
C?
C1-1
$endlist
$component C26
SM*
C?
C1-1
$endlist
$component C24
SM*
C?
C1-1
$endlist
$component C25
SM*
C?
C1-1
$endlist
$component C23
SM*
C?
C1-1
$endlist
$component C22
SM*
C?
C1-1
$endlist
$component R13
R?
SM0603
SM0805
$endlist
$component R14
R?
SM0603
SM0805
$endlist
$component R12
R?
SM0603
SM0805
$endlist
$component R11
R?
SM0603
SM0805
$endlist
$component C19
SM*
C?
C1-1
$endlist
$component C20
SM*
C?
C1-1
$endlist
$component C18
SM*
C?
C1-1
$endlist
$component C17
SM*
C?
C1-1
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 1 "/FPGA, Port0, Port2, PROG IF/S6_TDO" "S6_TDO"
U1 A19
IC1 22
Net 2 "/DBG_PRG/FPGA_TDI" "FPGA_TDI"
IC1 23
U1 E18
Net 3 "/FPGA, Port0, Port2, PROG IF/S6_TMS" "S6_TMS"
U1 C18
IC1 21
Net 4 "/DBG_PRG/FPGA_TCK" "FPGA_TCK"
IC1 24
U1 G15
Net 5 "/DBG_PRG/AVR_SCK" "AVR_SCK"
IC1 40
U9 1
Net 6 "/DDR Banks/M0_UDM" "M0_UDM"
U2 47
R23 2
Net 7 "/FPGA Port 1, Port 3 DDR, USB/M0_LDQS" "M0_LDQS"
R86 2
U2 16
Net 8 "/FPGA Port 1, Port 3 DDR, USB/M0_CLK" "M0_CLK"
U1 H4
R21 1
U2 46
Net 9 "/DDR Banks/M0_CLK#" "M0_CLK#"
U1 H3
U2 44
R21 2
Net 10 "GND" "GND"
U4 44
J1 CASE
J1 CASE
U4 36
U4 35
U4 39
U4 8
U4 12
U4 23
R2 2
C11 2
C10 2
C12 2
R9 2
C1 2
U2 58
U2 48
C3 2
C9 2
C6 2
C4 2
C2 2
C5 2
C7 2
C8 2
C75 1
C43 2
U2 6
C40 2
C92 2
C93 2
C72 2
C73 2
C74 2
C39 2
C47 2
C44 2
C41 2
U8 4
C53 2
C51 2
C49 2
C46 2
C52 2
U3 58
C27 2
C21 2
C94 2
C26 2
C24 2
C25 2
C23 2
C33 2
C28 2
C29 2
C31 2
C30 2
C32 2
C91 2
C22 2
R14 2
R12 2
C20 2
C18 2
U2 64
C90 2
U2 66
C76 2
U2 12
U2 52
U2 24
U2 34
C70 2
C71 2
C34 2
C66 2
U5 13
C63 2
C60 2
U5 36
J1 CASE
J1 COM
C61 2
J1 6
C58 2
C55 2
C68 2
C65 2
C62 2
C59 2
C56 2
C50 2
C77 2
C48 2
C45 2
C42 2
C57 2
C54 2
C69 2
C67 2
C64 2
U25 2
IC1 9
C155 2
R78 2
IC1 18
IC1 47
IC1 45
IC1 25
IC1 34
C145 2
R69 2
C150 2
C153 2
C152 2
U1 R18
U1 L18
U1 G18
C149 1
C151 2
FB1 2
C148 2
C97 2
U11 2
U12 2
U15 2
C78 2
C82 2
U17 5
C84 2
R27 2
C85 2
U13 5
C104 2
U10 2
U9 PAD
U10 5
U9 8
C80 2
U10 PAD
R25 2
U14 5
C81 2
R33 2
R31 2
R44 2
C102 2
R42 2
C103 2
C99 2
C147 2
C146 2
U16 5
R35 2
C95 2
R38 2
C98 2
C100 2
R41 2
U1 M12
U1 K12
U1 AB1
U1 U21
R47 1
R46 1
C35 2
U6 6
U6 7
U1 W19
U1 N15
U1 J15
U1 E15
U1 V14
U1 P14
C15 2
U1 J11
C14 2
C13 2
U1 E11
R10 2
C16 2
U1 V10
V1 2
U1 P10
U1 M10
U1 K10
U1 N9
U1 L9
U7 6
U7 7
U1 AA17
J4 4
J4 5
U1 N21
U1 J21
U1 E21
U1 N11
U1 L11
U1 AA9
U1 AB22
U1 AA13
U1 J9
U1 B9
U1 W7
U1 U7
R53 1
U1 H7
R54 1
U1 E7
U1 R5
U1 L5
U1 G5
U1 B5
U1 V4
U1 D4
U1 U2
U1 N2
U1 J2
U1 E2
U1 A1
U1 P12
U1 D18
U1 N17
U1 B17
L7 2
L5 2
C36 2
C37 2
V4 2
V3 2
C38 2
U1 W16
R15 2
V2 2
U1 AA5
U1 M14
U1 K14
U1 N13
U1 L13
U1 J13
U1 B13
U1 A22
C144 2
C143 2
C141 2
C136 2
C138 2
C139 2
C116 2
C121 2
C118 2
U3 66
C117 2
C120 2
R66 2
C127 2
U3 6
C106 2
C105 2
C108 2
R60 2
C114 2
U18 2
U22 2
U19 2
C115 2
R62 2
C109 2
C137 2
C133 2
C135 2
C134 2
C131 2
C132 2
C130 2
C129 2
U20 2
U23 2
C128 2
U24 30
R68 2
U24 35
U3 64
U3 34
U24 44
U3 52
U3 12
U3 48
U24 6
U24 39
C142 2
C140 2
C110 2
C107 2
R64 2
Net 11 "/DDR Banks/M1_CLK#" "M1_CLK#"
U3 44
U1 J19
R16 1
Net 12 "/DDR Banks/M1_CLK" "M1_CLK"
R16 2
U1 H20
U3 46
Net 13 "/FPGA Port 1, Port 3 DDR, USB/M1_CKE" "M1_CKE"
R17 2
U3 45
Net 14 "/FPGA Port 1, Port 3 DDR, USB/M1_CAS#" "M1_CAS#"
R79 2
U3 22
Net 15 "/DDR Banks/M0_LDM" "M0_LDM"
R85 2
U2 20
Net 16 "/FPGA Port 1, Port 3 DDR, USB/M0_UDQS" "M0_UDQS"
U2 51
R22 2
Net 17 "/FPGA Port 1, Port 3 DDR, USB/M1_UDQS" "M1_UDQS"
U3 51
R19 2
Net 18 "/FPGA Port 1, Port 3 DDR, USB/M1_LDM" "M1_LDM"
U3 20
R81 2
Net 19 "/FPGA Port 1, Port 3 DDR, USB/M1_LDQS" "M1_LDQS"
U3 16
R82 2
Net 20 "/DDR Banks/M1_UDM" "M1_UDM"
U3 47
R18 2
Net 21 "/DDR Banks/M1_CS#" "M1_CS#"
R20 2
U3 24
Net 22 "/FPGA, Port0, Port2, PROG IF/NF_ALE" "NF_ALE"
U5 17
U1 A14
Net 23 "/FPGA, Port0, Port2, PROG IF/NF_CLE" "NF_CLE"
U1 B14
U5 16
Net 24 "/Non volatile memories/NF_WE_N" "NF_WE_N"
U1 C14
U5 18
Net 25 "/Non volatile memories/NF_CS1_N" "NF_CS1_N"
U5 9
U1 D15
Net 26 "/Non volatile memories/NF_RE_N" "NF_RE_N"
U1 C15
U5 8
Net 27 "/Non volatile memories/NF_RNB" "NF_RNB"
U1 A15
U5 7
U5 6
Net 28 "/FPGA, Port0, Port2, PROG IF/PROG_CCLK" "PROG_CCLK"
U1 AA21
U8 6
Net 29 "/Non volatile memories/SPI_FLASH_CS#" "SPI_FLASH_CS#"
U1 T5
U8 1
Net 30 "/USB/USBA_SPD" "USBA_SPD"
U6 1
U1 F16
Net 31 "/USB/USBA_OE_N" "USBA_OE_N"
U6 9
U1 C19
Net 32 "/USB/USBA_RCV" "USBA_RCV"
U6 2
U1 F17
Net 33 "/USB/USBA_VP" "USBA_VP"
U1 D19
U6 3
Net 34 "/DBG_PRG/AVR_MISO" "AVR_MISO"
IC1 38
U9 20
Net 35 "/PSU/AVR_MOSI" "AVR_MOSI"
U9 16
IC1 39
Net 36 "/PSU/AVR_RST" "AVR_RST"
R57 1
U9 13
IC1 37
Net 37 "/Non volatile memories/SD_CMD" "SD_CMD"
J1 3
U1 C16
Net 38 "/Non volatile memories/SD_CLK" "SD_CLK"
U1 A17
J1 5
Net 39 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN"
U1 D9
U4 16
Net 40 "/FPGA, Port0, Port2, PROG IF/ETH_TXER" "ETH_TXER"
U1 D8
U4 14
Net 41 "/Ethernet Phy/ETH_CLK" "ETH_CLK"
U1 A4
U4 46
Net 42 "/Ethernet Phy/ETH_INT" "ETH_INT"
U4 25
U1 A10
Net 43 "/FPGA Port 1, Port 3 DDR, USB/M0_WE#" "M0_WE#"
U2 21
R84 2
Net 44 "/FPGA Port 1, Port 3 DDR, USB/M0_RAS#" "M0_RAS#"
U2 23
RP15 8
Net 45 "/FPGA Port 1, Port 3 DDR, USB/M1_RAS#" "M1_RAS#"
U3 23
RP2 8
Net 46 "/FPGA Port 1, Port 3 DDR, USB/M1_WE#" "M1_WE#"
U3 21
R80 2
Net 47 "/FPGA Port 1, Port 3 DDR, USB/M0_CAS#" "M0_CAS#"
R83 2
U2 22
Net 48 "/FPGA Port 1, Port 3 DDR, USB/M0_CKE" "M0_CKE"
U2 45
R24 2
Net 49 "/FPGA Port 1, Port 3 DDR, USB/USBA_VM" "USBA_VM"
U6 4
U1 D20
Net 50 "/USB/USBD_SPD" "USBD_SPD"
U7 1
U1 B20
Net 51 "/FPGA Port 1, Port 3 DDR, USB/USBD_OE_N" "USBD_OE_N"
U7 9
U1 A21
Net 52 "/USB/USBD_RCV" "USBD_RCV"
U1 A20
U7 2
Net 53 "/USB/USBD_VP" "USBD_VP"
U1 B21
U7 3
Net 54 "/USB/USBD_VM" "USBD_VM"
U7 4
U1 B22
Net 55 "/FPGA, Port0, Port2, PROG IF/ETH_RXC" "ETH_RXC"
U1 A7
U4 10
Net 56 "/Ethernet Phy/ETH_RST_N" "ETH_RST_N"
U4 48
U1 C7
Net 57 "/FPGA, Port0, Port2, PROG IF/ETH_CRS" "ETH_CRS"
U1 B10
U4 22
Net 58 "/Ethernet Phy/ETH_COL" "ETH_COL"
U4 21
U1 A9
Net 59 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO"
R1 1
U4 1
U1 D6
Net 60 "/Ethernet Phy/ETH_MDC" "ETH_MDC"
U1 D7
U4 2
Net 61 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV"
U4 9
U1 A6
Net 62 "/Ethernet Phy/ETH_RXER" "ETH_RXER"
U1 B8
U4 11
Net 63 "/Ethernet Phy/ETH_TXC" "ETH_TXC"
U4 15
U1 C8
Net 64 "/Image Sensor/IS_STANDBY" "IS_STANDBY"
U1 Y5
U24 22
Net 65 "/Image Sensor/IS_TRIGGER" "IS_TRIGGER"
U24 27
U1 Y3
Net 66 "/Image Sensor/IS_PIXEL" "IS_PIXEL"
U1 AB6
U24 13
Net 67 "/FPGA, Port0, Port2, PROG IF/IS_FRAME" "IS_FRAME"
U1 AB2
U24 28
Net 68 "/Image Sensor/+2.8_VDDIO" "+2.8_VDDIO"
C124 1
C140 1
C142 1
C144 1
U22 6
C143 1
C141 1
R65 1
U24 18
C127 1
U24 12
Net 69 "/Image Sensor/+2.8_VAAPIX" "+2.8_VAAPIX"
C132 1
C131 1
U24 38
U24 37
U19 6
C112 1
C115 1
R61 1
Net 70 "/FPGA, Port0, Port2, PROG IF/IS_SDA" "IS_SDA"
U24 16
U1 AA6
Net 71 "/Image Sensor/IS_I2C_ADDR" "IS_I2C_ADDR"
U24 24
U1 AB4
Net 72 "/Image Sensor/IS_RESET_N" "IS_RESET_N"
U24 17
U1 AB5
Net 73 "/Image Sensor/IS_LINE" "IS_LINE"
U24 29
U1 AA2
Net 74 "/Image Sensor/IS_FLASH" "IS_FLASH"
U24 26
U1 AB3
Net 75 "/Image Sensor/IS_TEST" "IS_TEST"
U24 25
U1 AA4
Net 76 "/FPGA, Port0, Port2, PROG IF/IS_OE_N" "IS_OE_N"
U24 23
U1 Y4
Net 77 "/FPGA, Port0, Port2, PROG IF/IS_EXTCLK" "IS_EXTCLK"
U1 W12
U24 5
Net 78 "/Image Sensor/IS_SCL" "IS_SCL"
U24 15
U1 Y12
Net 79 "/Snesor PSU/+2.8_VAA" "+2.8_VAA"
U24 40
U24 36
U24 34
C133 1
C135 1
U18 6
C111 1
C114 1
R59 1
C134 1
Net 80 "/Snesor PSU/+1.8_VDD" "+1.8_VDD"
C116 1
C113 1
R63 1
U20 6
U24 14
U24 19
C136 1
C138 1
C139 1
C137 1
Net 81 "/Snesor PSU/+2.8_VDDPLL" "+2.8_VDDPLL"
C125 1
U23 6
U24 4
C129 1
C130 1
C128 1
R67 1
Net 86 "+2.5V" "+2.5V"
C40 1
U2 3
C17 1
U2 1
C43 1
U3 61
C57 1
C60 1
C63 1
U3 1
C66 1
U3 55
C56 1
C59 1
C62 1
C52 1
C46 1
C49 1
C51 1
C53 1
U3 3
C54 1
U3 9
C22 1
C23 1
C25 1
C24 1
C26 1
C21 1
C101 1
C102 1
R43 1
L11 1
C103 1
C94 1
C77 1
C27 1
C32 1
C30 1
C31 1
C29 1
C28 1
C33 1
U2 55
U2 15
C19 1
R11 1
R13 1
U2 9
C34 1
C71 1
C70 1
U2 33
U2 61
U2 18
U6 15
U1 L16
U1 V6
U1 R6
U1 N18
U1 U18
U7 15
U1 E19
U1 L7
U1 C21
U1 J18
U1 J5
U1 N5
U1 U5
U1 F6
U1 F4
U1 R12
U1 U11
U1 F11
C65 1
U3 18
C68 1
C15 1
U1 R10
U1 W2
U1 R2
U3 33
U3 15
U1 H15
U1 L2
U1 K15
U1 M15
U1 G2
U1 C2
U1 G12
U1 D16
U1 H9
U1 L21
U1 N8
U1 R21
U1 W21
U1 L8
C37 1
U1 G21
Net 89 "/DDR Banks/M0_VREF" "M0_VREF"
R12 1
C18 1
C17 2
U2 49
R11 2
Net 90 "/DDR Banks/M1_VREF" "M1_VREF"
U3 49
C20 1
C19 2
R13 2
R14 1
Net 99 "/PSU/VCCO2" "VCCO2"
U1 AA3
C55 1
U8 8
U1 AA15
U1 AA19
C58 1
C69 1
C67 1
C64 1
U1 V8
U1 T9
C61 1
U25 6
C154 1
C155 1
R77 1
U1 T13
U1 V12
U1 AA7
U1 V16
U1 W5
U1 AA11
Net 100 "+3.3V" "+3.3V"
U9 9
C79 1
C80 1
R26 1
L8 1
C81 1
R57 2
C104 1
U1 B11
U1 G10
U1 E9
U1 B19
U1 E17
U1 B15
U1 G14
U1 E13
U1 B7
U1 B4
U1 Y20
C10 1
C11 1
U4 7
L2 1
R1 2
C1 1
C3 1
C5 1
J4 11
R5 1
R6 1
R4 1
R3 1
J4 9
J4 6
J4 3
U5 37
U5 19
U5 12
C47 1
C50 1
J1 4
U4 24
R55 1
C13 1
C14 1
U7 12
U7 14
R48 1
C35 1
C36 1
U6 12
U6 14
R29 1
C90 1
R30 1
C74 1
C75 2
C91 1
C72 1
C73 1
C44 1
C41 1
Net 133 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V"
U4 13
L1 1
C4 1
C2 1
Net 134 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
U4 47
L3 2
C9 1
Net 135 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
U4 31
L3 1
C6 1
L1 2
Net 136 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD"
J4 13
J4 14
R9 1
C12 1
Net 137 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
R7 2
U4 26
Net 138 "" ""
U4 37
R2 1
Net 144 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
U4 38
L2 2
C8 1
C7 1
Net 145 "/Ethernet Phy/MAG_RX-" "MAG_RX-"
J4 8
R6 2
U4 32
Net 146 "/Ethernet Phy/MAG_TX-" "MAG_TX-"
J4 2
R4 2
U4 40
Net 147 "/Ethernet Phy/MAG_TX+" "MAG_TX+"
J4 1
R3 2
U4 41
Net 148 "" ""
J4 10
R7 1
Net 149 "" ""
R8 1
J4 12
Net 150 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
R8 2
U4 27
Net 151 "/Ethernet Phy/MAG_RX+" "MAG_RX+"
J4 7
U4 33
R5 2
Net 152 "" ""
R50 2
U7 10
Net 153 "" ""
R51 2
U6 11
Net 154 "" ""
U6 10
R52 2
Net 155 "" ""
R49 2
U7 11
Net 156 "" ""
J7 5
J7 4
Net 157 "/USB/USBD_D+" "USBD_D+"
R53 2
R55 2
V3 1
V3 1
J7 3
R49 1
Net 158 "" ""
L5 1
J5 4
Net 159 "" ""
J5 1
L4 2
Net 160 "" ""
F1 1
L4 1
Net 161 "+5V" "+5V"
C98 1
R39 1
F1 2
U15 5
C97 1
C96 1
Net 162 "" ""
J7 1
L7 1
Net 163 "/USB/USBD_D-" "USBD_D-"
R50 1
R54 2
V4 1
V4 1
J7 2
Net 164 "/USB/USBA_D-" "USBA_D-"
R46 2
R52 1
J5 2
V2 1
V2 1
Net 165 "/USB/USBA_D+" "USBA_D+"
V1 1
R51 1
V1 1
R47 2
R48 2
J5 3
Net 166 "/USB/USB_CASE_HOST" "USB_CASE_HOST"
C16 1
J5 S4
J5 S3
R10 1
J5 S2
J5 S1
Net 167 "/USB/USB_CASE_DEV" "USB_CASE_DEV"
J7 6
R15 1
C38 1
J7 7
J7 8
J7 9
Net 168 "/PSU/VFB3.3" "VFB3.3"
U11 5
R26 2
R25 1
C79 2
Net 169 "/PSU/Iout_1.2" "Iout_1.2"
R33 1
U14 3
U9 2
Net 170 "" ""
U15 1
L10 1
Net 171 "+1.2V" "+1.2V"
U1 K13
U1 M13
U1 P13
U1 J14
U1 L14
U1 J8
U1 R14
U1 N14
U1 K11
U1 M11
U1 P11
L9 1
C39 1
C92 1
C93 1
C85 1
C42 1
C45 1
C48 1
R28 1
C84 1
C83 1
C76 1
U1 J12
U1 L12
U1 N12
U1 K9
U1 M9
U1 P9
U1 J10
U1 L10
U1 N10
Net 172 "/PSU/VFB1.2" "VFB1.2"
R28 2
U12 5
R27 1
C83 2
Net 173 "" ""
C100 1
R40 2
Net 174 "/PSU/lout_2.5" "lout_2.5"
U17 3
R44 1
U9 11
Net 175 "/PSU/1.2V_EN" "1.2V_EN"
U9 3
R58 1
U12 1
Net 176 "/PSU/VFB2.5" "VFB2.5"
C101 2
R42 1
U10 9
R43 2
Net 177 "" ""
C153 1
U25 4
Net 178 "" ""
R78 1
R77 2
C154 2
U25 5
Net 179 "/PSU/2.5V_EN" "2.5V_EN"
U9 12
U10 1
R41 1
Net 180 "+BATT" "+BATT"
U23 1
C152 1
U25 1
U25 3
U14 1
R34 2
U17 1
R45 2
R36 2
R32 2
U16 1
U13 1
U20 3
U20 1
U22 1
C118 1
C117 1
U23 3
C106 1
C105 1
U18 1
U18 3
U22 3
U19 1
U19 3
C107 1
Net 181 "/PSU/SW_2.5" "SW_2.5"
L11 2
U10 3
U10 4
Net 182 "" ""
R40 1
U10 10
Net 183 "/PSU/VFB5.0" "VFB5.0"
U15 3
R38 1
R39 2
C96 2
Net 184 "/PSU/lout_3.3" "lout_3.3"
U9 4
U13 3
R31 1
Net 185 "/PSU/SW_3.3" "SW_3.3"
L8 2
U11 3
Net 186 "/PSU/5V_EN" "5V_EN"
R37 1
U15 4
U9 15
Net 187 "/PSU/VIN_DC-DC-1.2" "VIN_DC-DC-1.2"
C82 1
R34 1
U12 4
U14 6
R58 2
Net 188 "/PSU/VIN_DC-DC-3.3" "VIN_DC-DC-3.3"
R32 1
C78 1
U11 4
R56 2
U13 6
Net 191 "/PSU/SW_1.2" "SW_1.2"
L9 2
U12 3
Net 200 "/PSU/lout_5.0" "lout_5.0"
R35 1
U9 14
U16 3
Net 203 "/PSU/3.3V_EN" "3.3V_EN"
U11 1
R56 1
U9 5
Net 205 "/PSU/VIN_DC-DC-5.0" "VIN_DC-DC-5.0"
U16 6
C95 1
U15 6
R37 2
R36 1
L10 2
Net 207 "/PSU/VIN_DC-DC-2.5" "VIN_DC-DC-2.5"
R45 1
U10 8
U10 6
U17 6
U10 7
C99 1
Net 208 "/DBG_PRG/5V_USB" "5V_USB"
C148 1
FB2 1
J8 1
Net 209 "/DBG_PRG/FTDI_USB_DP" "FTDI_USB_DP"
R71 2
J8 3
Net 210 "" ""
C147 1
X1 2
IC1 44
Net 211 "" ""
IC1 46
R74 2
C151 1
Net 229 "" ""
IC1 43
C146 1
X1 1
Net 230 "/DBG_PRG/VCC_USB" "VCC_USB"
FB2 2
R73 2
IC1 3
IC1 4
C150 1
IC1 42
R74 1
Net 231 "/DBG_PRG/USB_CASE_FTDI" "USB_CASE_FTDI"
R69 1
C145 1
J8 6
J8 7
J8 8
J8 9
Net 232 "" ""
FB1 1
J8 4
J8 5
Net 233 "/DBG_PRG/FTDI_USB_DM" "FTDI_USB_DM"
J8 2
R70 2
Net 234 "/DBG_PRG/3.3V_USB" "3.3V_USB"
R75 1
IC1 6
R76 1
IC1 14
C149 2
IC1 31
Net 235 "" ""
R75 2
IC1 10
Net 236 "" ""
R73 1
IC1 2
Net 237 "" ""
R72 1
IC1 5
Net 238 "" ""
R70 1
IC1 8
Net 239 "" ""
R72 2
IC1 7
R71 1
Net 240 "" ""
R76 2
IC1 26
Net 259 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A10" "R_M1_A10"
RP2 4
U1 G19
Net 260 "/FPGA Port 1, Port 3 DDR, USB/R_M1_RAS#" "R_M1_RAS#"
U1 H21
RP2 1
Net 261 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA1" "R_M1_BA1"
RP2 3
U1 K17
Net 262 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA0" "R_M1_BA0"
RP2 2
U1 J17
Net 263 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A3" "R_M1_A3"
RP1 4
U1 G20
Net 264 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A2" "R_M1_A2"
RP1 3
U1 E22
Net 265 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A1" "R_M1_A1"
RP1 2
U1 F22
Net 266 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A0" "R_M1_A0"
U1 F21
RP1 1
Net 267 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CKE" "R_M1_CKE"
R17 1
U1 D21
Net 268 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDM" "R_M1_UDM"
R18 1
U1 M20
Net 269 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDQS" "R_M1_UDQS"
R19 1
U1 T21
Net 270 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CS#" "R_M1_CS#"
U1 H16
R20 1
Net 271 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CAS#" "R_M1_CAS#"
R79 1
U1 H22
Net 272 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A7" "R_M1_A7"
RP6 8
U1 E20
Net 273 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A6" "R_M1_A6"
U1 K19
RP6 7
Net 274 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A5" "R_M1_A5"
U1 K20
RP6 6
Net 275 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A4" "R_M1_A4"
U1 F20
RP6 5
Net 276 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A12" "R_M1_A12"
U1 D22
RP7 8
Net 277 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A11" "R_M1_A11"
U1 F19
RP7 7
Net 278 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A9" "R_M1_A9"
U1 C22
RP7 6
Net 279 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A8" "R_M1_A8"
RP7 5
U1 C20
Net 280 "/FPGA Port 1, Port 3 DDR, USB/R_M1_WE#" "R_M1_WE#"
R80 1
U1 H19
Net 281 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDM" "R_M1_LDM"
U1 L19
R81 1
Net 282 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDQS" "R_M1_LDQS"
R82 1
U1 L20
Net 296 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ12" "R_M1_DQ12"
U1 U20
RP8 5
Net 298 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ10" "R_M1_DQ10"
RP9 7
U1 R20
Net 300 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ0" "R_M1_DQ0"
RP5 1
U1 N20
Net 301 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ4" "R_M1_DQ4"
RP4 1
U1 J20
Net 342 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ14" "R_M1_DQ14"
U1 V21
RP8 7
Net 343 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ8" "R_M1_DQ8"
RP9 5
U1 P21
Net 344 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ2" "R_M1_DQ2"
U1 M21
RP5 3
Net 345 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ6" "R_M1_DQ6"
U1 K21
RP4 3
Net 350 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ15" "R_M1_DQ15"
U1 V22
RP8 8
Net 351 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ13" "R_M1_DQ13"
RP8 6
U1 U22
Net 353 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ11" "R_M1_DQ11"
U1 R22
RP9 8
Net 354 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ9" "R_M1_DQ9"
RP9 6
U1 P22
Net 355 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ1" "R_M1_DQ1"
U1 N22
RP5 2
Net 356 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ3" "R_M1_DQ3"
RP5 4
U1 M22
Net 358 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ7" "R_M1_DQ7"
RP4 4
U1 K22
Net 359 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ5" "R_M1_DQ5"
RP4 2
U1 J22
Net 361 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A3" "R_M0_A3"
RP14 4
U1 K6
Net 362 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A10" "R_M0_A10"
RP15 4
U1 G4
Net 363 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A7" "R_M0_A7"
U1 H6
RP17 1
Net 364 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A2" "R_M0_A2"
U1 H5
RP14 3
Net 365 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A6" "R_M0_A6"
RP17 2
U1 J4
Net 366 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ14" "R_M0_DQ14"
RP10 3
U1 V2
Net 367 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ8" "R_M0_DQ8"
U1 P2
RP11 1
Net 368 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ2" "R_M0_DQ2"
U1 M2
RP13 3
Net 369 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ6" "R_M0_DQ6"
U1 K2
RP12 3
Net 370 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A0" "R_M0_A0"
U1 H2
RP14 1
Net 376 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ12" "R_M0_DQ12"
RP10 1
U1 U3
Net 378 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ10" "R_M0_DQ10"
U1 R3
RP11 3
Net 380 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ0" "R_M0_DQ0"
U1 N3
RP13 1
Net 381 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A5" "R_M0_A5"
U1 K3
RP17 3
Net 382 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ4" "R_M0_DQ4"
RP12 1
U1 J3
Net 383 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA0" "R_M0_BA0"
RP15 2
U1 G3
Net 384 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A4" "R_M0_A4"
RP17 4
U1 F3
Net 385 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A8" "R_M0_A8"
RP18 4
U1 E3
Net 390 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ15" "R_M0_DQ15"
RP10 4
U1 V1
Net 391 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ13" "R_M0_DQ13"
RP10 2
U1 U1
Net 393 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ11" "R_M0_DQ11"
RP11 4
U1 R1
Net 394 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ9" "R_M0_DQ9"
U1 P1
RP11 2
Net 395 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ1" "R_M0_DQ1"
RP13 2
U1 N1
Net 396 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ3" "R_M0_DQ3"
RP13 4
U1 M1
Net 398 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ7" "R_M0_DQ7"
U1 K1
RP12 4
Net 399 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ5" "R_M0_DQ5"
RP12 2
U1 J1
Net 400 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A1" "R_M0_A1"
U1 H1
RP14 2
Net 401 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA1" "R_M0_BA1"
U1 G1
RP15 3
Net 403 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A9" "R_M0_A9"
RP18 3
U1 E1
Net 404 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A12" "R_M0_A12"
RP18 1
U1 D1
Net 405 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A11" "R_M0_A11"
U1 C1
RP18 2
Net 407 "/FPGA Port 1, Port 3 DDR, USB/R_M0_RAS#" "R_M0_RAS#"
U1 K5
RP15 1
Net 408 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDM" "R_M0_LDM"
U1 L4
R85 1
Net 409 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CAS#" "R_M0_CAS#"
U1 K4
R83 1
Net 410 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDM" "R_M0_UDM"
R23 1
U1 M3
Net 411 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CKE" "R_M0_CKE"
R24 1
U1 D2
Net 412 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDQS" "R_M0_UDQS"
R22 1
U1 T2
Net 413 "/FPGA Port 1, Port 3 DDR, USB/R_M0_WE#" "R_M0_WE#"
R84 1
U1 F2
Net 414 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDQS" "R_M0_LDQS"
R86 1
U1 L3
Net 417 "" ""
U1 Y22
R30 2
Net 420 "" ""
R29 2
U1 AA1
Net 463 "" ""
R66 1
R65 2
C124 2
U22 5
Net 464 "" ""
C120 1
U22 4
Net 465 "" ""
U19 4
C109 1
Net 466 "" ""
R60 1
U18 5
R59 2
C111 2
Net 467 "" ""
U18 4
C108 1
Net 468 "" ""
U19 5
C112 2
R61 2
R62 1
Net 469 "" ""
C113 2
R63 2
R64 1
U20 5
Net 470 "" ""
C121 1
U23 4
Net 471 "" ""
R68 1
R67 2
C125 2
U23 5
Net 472 "" ""
C110 1
U20 4
Net 501 "/DDR Banks/M1_DQ13" "M1_DQ13"
U3 62
RP8 3
Net 502 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ14" "M1_DQ14"
RP8 2
U3 63
Net 503 "/DDR Banks/M1_DQ15" "M1_DQ15"
RP8 1
U3 65
Net 504 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ0" "M0_DQ0"
U2 2
RP13 8
Net 505 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ1" "M0_DQ1"
RP13 7
U2 4
Net 506 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ2" "M0_DQ2"
U2 5
RP13 6
Net 507 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ3" "M0_DQ3"
RP13 5
U2 7
Net 508 "/DDR Banks/M0_DQ4" "M0_DQ4"
RP12 8
U2 8
Net 509 "/DDR Banks/M0_DQ5" "M0_DQ5"
RP12 7
U2 10
Net 510 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ6" "M0_DQ6"
U2 11
RP12 6
Net 511 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ7" "M0_DQ7"
U2 13
RP12 5
Net 512 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ8" "M0_DQ8"
RP11 8
U2 54
Net 513 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ9" "M0_DQ9"
U2 56
RP11 7
Net 514 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ10" "M0_DQ10"
RP11 6
U2 57
Net 515 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ11" "M0_DQ11"
RP11 5
U2 59
Net 516 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ12" "M0_DQ12"
RP10 8
U2 60
Net 517 "/DDR Banks/M0_DQ13" "M0_DQ13"
RP10 7
U2 62
Net 518 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ0" "M1_DQ0"
RP5 8
U3 2
Net 519 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ1" "M1_DQ1"
RP5 7
U3 4
Net 520 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ2" "M1_DQ2"
RP5 6
U3 5
Net 521 "/DDR Banks/M1_DQ3" "M1_DQ3"
U3 7
RP5 5
Net 522 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ4" "M1_DQ4"
U3 8
RP4 8
Net 523 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ5" "M1_DQ5"
U3 10
RP4 7
Net 524 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ6" "M1_DQ6"
RP4 6
U3 11
Net 525 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ7" "M1_DQ7"
U3 13
RP4 5
Net 526 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ8" "M1_DQ8"
RP9 4
U3 54
Net 527 "/DDR Banks/M1_DQ9" "M1_DQ9"
RP9 3
U3 56
Net 528 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ10" "M1_DQ10"
RP9 2
U3 57
Net 529 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ11" "M1_DQ11"
RP9 1
U3 59
Net 530 "/DDR Banks/M1_DQ12" "M1_DQ12"
RP8 4
U3 60
Net 531 "/DDR Banks/M1_A4" "M1_A4"
RP6 4
U3 35
Net 532 "/DDR Banks/M1_A5" "M1_A5"
U3 36
RP6 3
Net 533 "/FPGA Port 1, Port 3 DDR, USB/M1_A6" "M1_A6"
U3 37
RP6 2
Net 534 "/FPGA Port 1, Port 3 DDR, USB/M1_A7" "M1_A7"
U3 38
RP6 1
Net 535 "/FPGA Port 1, Port 3 DDR, USB/M1_A8" "M1_A8"
U3 39
RP7 4
Net 536 "/FPGA Port 1, Port 3 DDR, USB/M1_A9" "M1_A9"
U3 40
RP7 3
Net 537 "/FPGA Port 1, Port 3 DDR, USB/M1_A10" "M1_A10"
U3 28
RP2 5
Net 538 "/FPGA Port 1, Port 3 DDR, USB/M1_A11" "M1_A11"
U3 41
RP7 2
Net 539 "/DDR Banks/M1_A12" "M1_A12"
RP7 1
U3 42
Net 540 "/DDR Banks/M0_DQ14" "M0_DQ14"
U2 63
RP10 6
Net 541 "/DDR Banks/M0_DQ15" "M0_DQ15"
RP10 5
U2 65
Net 542 "/DDR Banks/M0_A0" "M0_A0"
RP14 8
U2 29
Net 543 "/DDR Banks/M0_A1" "M0_A1"
U2 30
RP14 7
Net 544 "/FPGA Port 1, Port 3 DDR, USB/M0_A2" "M0_A2"
RP14 6
U2 31
Net 545 "/FPGA Port 1, Port 3 DDR, USB/M0_A3" "M0_A3"
RP14 5
U2 32
Net 546 "/DDR Banks/M0_A4" "M0_A4"
U2 35
RP17 5
Net 547 "/FPGA Port 1, Port 3 DDR, USB/M0_A5" "M0_A5"
U2 36
RP17 6
Net 548 "/FPGA Port 1, Port 3 DDR, USB/M0_A6" "M0_A6"
U2 37
RP17 7
Net 549 "/DDR Banks/M0_A7" "M0_A7"
U2 38
RP17 8
Net 550 "/DDR Banks/M0_A8" "M0_A8"
U2 39
RP18 5
Net 551 "/DDR Banks/M0_A9" "M0_A9"
U2 40
RP18 6
Net 552 "/DDR Banks/M0_A10" "M0_A10"
RP15 5
U2 28
Net 553 "/DDR Banks/M0_A11" "M0_A11"
U2 41
RP18 7
Net 554 "/FPGA Port 1, Port 3 DDR, USB/M0_A12" "M0_A12"
U2 42
RP18 8
Net 555 "/FPGA Port 1, Port 3 DDR, USB/M1_A0" "M1_A0"
RP1 8
U3 29
Net 556 "/FPGA Port 1, Port 3 DDR, USB/M1_A1" "M1_A1"
RP1 7
U3 30
Net 557 "/FPGA Port 1, Port 3 DDR, USB/M1_A2" "M1_A2"
U3 31
RP1 6
Net 558 "/DDR Banks/M1_A3" "M1_A3"
U3 32
RP1 5
Net 559 "/FPGA GPIOS/FPGA_BANK0_IO_36" "FPGA_BANK0_IO_36"
U1 T14
P1 30
Net 562 "/FPGA GPIOS/FPGA_BANK0_IO_39" "FPGA_BANK0_IO_39"
P1 23
U1 AB13
P1 23
Net 563 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_40" "FPGA_BANK0_IO_40"
P1 32
U1 Y11
Net 566 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_43" "FPGA_BANK0_IO_43"
U1 V11
P1 34
Net 567 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_44" "FPGA_BANK0_IO_44"
U1 W11
P1 31
Net 568 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_45" "FPGA_BANK0_IO_45"
U1 Y9
P1 35
Net 569 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_46" "FPGA_BANK0_IO_46"
P1 36
U1 W10
Net 570 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_47" "FPGA_BANK0_IO_47"
U1 Y10
P1 33
Net 571 "/FPGA GPIOS/FPGA_BANK0_IO_48" "FPGA_BANK0_IO_48"
P1 40
U1 W8
Net 573 "/FPGA GPIOS/FPGA_BANK0_IO_50" "FPGA_BANK0_IO_50"
P1 38
U1 W9
Net 575 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_52" "FPGA_BANK0_IO_52"
U1 V9
P1 37
Net 577 "/FPGA GPIOS/FPGA_BANK0_IO_17" "FPGA_BANK0_IO_17"
P1 13
U1 V15
Net 578 "/FPGA GPIOS/FPGA_BANK0_IO_18" "FPGA_BANK0_IO_18"
U1 AA18
P1 12
Net 580 "/FPGA GPIOS/FPGA_BANK0_IO_20" "FPGA_BANK0_IO_20"
U1 Y17
P1 15
Net 581 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_21" "FPGA_BANK0_IO_21"
U1 AB17
P1 14
Net 582 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_22" "FPGA_BANK0_IO_22"
P1 19
U1 AA14
Net 584 "/FPGA GPIOS/FPGA_BANK0_IO_24" "FPGA_BANK0_IO_24"
U1 Y16
P1 16
Net 585 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_25" "FPGA_BANK0_IO_25"
U1 W15
P1 22
Net 587 "/FPGA GPIOS/FPGA_BANK0_IO_27" "FPGA_BANK0_IO_27"
P1 21
U1 W13
Net 588 "/FPGA GPIOS/FPGA_BANK0_IO_28" "FPGA_BANK0_IO_28"
P1 17
U1 AA16
Net 589 "/FPGA GPIOS/FPGA_BANK0_IO_29" "FPGA_BANK0_IO_29"
P1 18
U1 AB16
Net 590 "/FPGA GPIOS/FPGA_BANK0_IO_30" "FPGA_BANK0_IO_30"
P1 20
U1 W14
Net 592 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_32" "FPGA_BANK0_IO_32"
U1 Y15
P1 26
Net 593 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_33" "FPGA_BANK0_IO_33"
U1 AB15
P1 24
Net 596 "/FPGA Port 1, Port 3 DDR, USB/M0_BA0" "M0_BA0"
RP15 7
U2 26
Net 597 "/FPGA Port 1, Port 3 DDR, USB/M0_BA1" "M0_BA1"
U2 27
RP15 6
Net 598 "/FPGA Port 1, Port 3 DDR, USB/M1_BA0" "M1_BA0"
U3 26
RP2 7
Net 599 "/DDR Banks/M1_BA1" "M1_BA1"
RP2 6
U3 27
Net 602 "/FPGA GPIOS/FPGA_BANK0_IO_56" "FPGA_BANK0_IO_56"
P1 39
U1 U10
Net 611 "/FPGA, Port0, Port2, PROG IF/NF_D6" "NF_D6"
U1 A11
U5 43
Net 612 "/FPGA, Port0, Port2, PROG IF/NF_D7" "NF_D7"
U5 44
U1 D11
Net 613 "/FPGA, Port0, Port2, PROG IF/PROG_MISO0" "PROG_MISO0"
U8 5
U1 AB20
Net 614 "/FPGA, Port0, Port2, PROG IF/PROG_MISO1" "PROG_MISO1"
U1 AA20
U8 2
Net 615 "/FPGA, Port0, Port2, PROG IF/PROG_MISO2" "PROG_MISO2"
U1 U14
U8 3
Net 616 "/Non volatile memories/SPI_DQ3" "SPI_DQ3"
U8 7
U1 U13
Net 617 "/Non volatile memories/SD_DAT0" "SD_DAT0"
U1 A18
J1 7
Net 618 "/FPGA, Port0, Port2, PROG IF/SD_DAT1" "SD_DAT1"
U1 B18
J1 8
Net 619 "/Non volatile memories/SD_DAT2" "SD_DAT2"
U1 A16
J1 1
Net 620 "/FPGA, Port0, Port2, PROG IF/SD_DAT3" "SD_DAT3"
J1 2
U1 B16
Net 621 "/FPGA, Port0, Port2, PROG IF/NF_D0" "NF_D0"
U1 C12
U5 29
Net 622 "/FPGA, Port0, Port2, PROG IF/NF_D1" "NF_D1"
U1 D14
U5 30
Net 623 "/Non volatile memories/NF_D2" "NF_D2"
U1 A13
U5 31
Net 624 "/Non volatile memories/NF_D3" "NF_D3"
U1 B12
U5 32
Net 625 "/FPGA, Port0, Port2, PROG IF/NF_D4" "NF_D4"
U1 A12
U5 41
Net 626 "/FPGA, Port0, Port2, PROG IF/NF_D5" "NF_D5"
U1 C11
U5 42
Net 627 "/FPGA, Port0, Port2, PROG IF/ETH_TXD0" "ETH_TXD0"
U1 D10
U4 17
Net 628 "/FPGA, Port0, Port2, PROG IF/ETH_TXD1" "ETH_TXD1"
U4 18
U1 C9
Net 629 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2"
U4 19
U1 C10
Net 630 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3"
U1 A8
U4 20
Net 631 "/FPGA, Port0, Port2, PROG IF/ETH_RXD0" "ETH_RXD0"
U1 B6
U4 6
Net 632 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1"
U4 5
U1 A5
Net 633 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2"
U1 C6
U4 4
Net 634 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3"
U1 C5
U4 3
Net 635 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_0" "FPGA_BANK0_IO_0"
P1 5
U1 AA22
Net 636 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_1" "FPGA_BANK0_IO_1"
U1 T18
P1 2
Net 637 "/FPGA GPIOS/FPGA_BANK0_IO_2" "FPGA_BANK0_IO_2"
U1 T17
P1 25
Net 638 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_3" "FPGA_BANK0_IO_3"
U1 Y19
P1 10
Net 640 "/FPGA GPIOS/FPGA_BANK0_IO_5" "FPGA_BANK0_IO_5"
U1 Y18
P1 11
Net 641 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_6" "FPGA_BANK0_IO_6"
U1 T16
P1 28
Net 642 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_7" "FPGA_BANK0_IO_7"
U1 T15
P1 27
Net 643 "/FPGA GPIOS/FPGA_BANK0_IO_8" "FPGA_BANK0_IO_8"
P1 1
U1 U17
Net 644 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_9" "FPGA_BANK0_IO_9"
U1 U16
P1 4
Net 645 "/FPGA GPIOS/FPGA_BANK0_IO_10" "FPGA_BANK0_IO_10"
U1 V19
P1 7
Net 646 "/FPGA GPIOS/FPGA_BANK0_IO_11" "FPGA_BANK0_IO_11"
U1 V18
P1 9
Net 647 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_12" "FPGA_BANK0_IO_12"
P1 29
U1 R16
Net 649 "/FPGA GPIOS/FPGA_BANK0_IO_14" "FPGA_BANK0_IO_14"
U1 V17
P1 6
Net 650 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_15" "FPGA_BANK0_IO_15"
P1 8
U1 W17
Net 651 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_16" "FPGA_BANK0_IO_16"
U1 U15
P1 3
Net 652 "/Image Sensor/IS_DOUT0" "IS_DOUT0"
U24 45
U1 AB12
Net 653 "/Image Sensor/IS_DOUT1" "IS_DOUT1"
U1 AA12
U24 46
Net 654 "/FPGA, Port0, Port2, PROG IF/IS_DOUT2" "IS_DOUT2"
U24 47
U1 AB11
Net 655 "/FPGA, Port0, Port2, PROG IF/IS_DOUT3" "IS_DOUT3"
U24 48
U1 AB10
Net 656 "/FPGA, Port0, Port2, PROG IF/IS_DOUT4" "IS_DOUT4"
U1 AA10
U24 1
Net 657 "/Image Sensor/IS_DOUT5" "IS_DOUT5"
U1 AB9
U24 2
Net 658 "/Image Sensor/IS_DOUT6" "IS_DOUT6"
U1 Y8
U24 3
Net 659 "/Image Sensor/IS_DOUT7" "IS_DOUT7"
U24 7
U1 AA8
Net 660 "/FPGA, Port0, Port2, PROG IF/IS_DOUT8" "IS_DOUT8"
U24 8
U1 AB8
Net 661 "/Image Sensor/IS_DOUT9" "IS_DOUT9"
U24 9
U1 Y7
Net 662 "/FPGA, Port0, Port2, PROG IF/IS_DOUT10" "IS_DOUT10"
U1 Y6
U24 10
Net 663 "/Image Sensor/IS_DOUT11" "IS_DOUT11"
U1 AB7
U24 11
}
#End
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