mirror of
git://projects.qi-hardware.com/xue.git
synced 2024-09-16 18:16:27 +03:00
487 lines
11 KiB
Plaintext
487 lines
11 KiB
Plaintext
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:01:41 AM COT
|
|
LIBS:power
|
|
LIBS:r_pack2
|
|
LIBS:v0402mhs03
|
|
LIBS:usb-48204-0001
|
|
LIBS:microsmd075f
|
|
LIBS:mic2550
|
|
LIBS:rj45-48025
|
|
LIBS:xue-nv
|
|
LIBS:xc6slx75fgg484
|
|
LIBS:xc6slx45fgg484
|
|
LIBS:micron_mobile_ddr
|
|
LIBS:micron_ddr_512Mb
|
|
LIBS:k8001
|
|
LIBS:device
|
|
LIBS:transistors
|
|
LIBS:conn
|
|
LIBS:linear
|
|
LIBS:regul
|
|
LIBS:74xx
|
|
LIBS:cmos4000
|
|
LIBS:adc-dac
|
|
LIBS:memory
|
|
LIBS:xilinx
|
|
LIBS:special
|
|
LIBS:microcontrollers
|
|
LIBS:dsp
|
|
LIBS:microchip
|
|
LIBS:analog_switches
|
|
LIBS:motorola
|
|
LIBS:texas
|
|
LIBS:intel
|
|
LIBS:audio
|
|
LIBS:interface
|
|
LIBS:digital-audio
|
|
LIBS:philips
|
|
LIBS:display
|
|
LIBS:cypress
|
|
LIBS:siliconi
|
|
LIBS:opto
|
|
LIBS:atmel
|
|
LIBS:contrib
|
|
LIBS:valves
|
|
LIBS:pasives-connectors
|
|
LIBS:x25x64mb
|
|
LIBS:attiny
|
|
LIBS:PSU
|
|
LIBS:tps793xx
|
|
LIBS:reg102
|
|
LIBS:mt9m033
|
|
LIBS:m12-tu400a
|
|
LIBS:xue-rnc-cache
|
|
EELAYER 24 0
|
|
EELAYER END
|
|
$Descr A3 16535 11700
|
|
Sheet 1 11
|
|
Title ""
|
|
Date "8 oct 2010"
|
|
Rev ""
|
|
Comp ""
|
|
Comment1 ""
|
|
Comment2 ""
|
|
Comment3 ""
|
|
Comment4 ""
|
|
$EndDescr
|
|
Wire Wire Line
|
|
4950 8600 5950 8600
|
|
Wire Wire Line
|
|
4950 8400 5950 8400
|
|
Wire Wire Line
|
|
5950 7400 4950 7400
|
|
Wire Wire Line
|
|
4950 8200 5950 8200
|
|
Wire Wire Line
|
|
4950 8000 5950 8000
|
|
Wire Wire Line
|
|
4950 7800 5950 7800
|
|
Wire Wire Line
|
|
5950 7600 4950 7600
|
|
Wire Wire Line
|
|
3150 9050 3400 9050
|
|
Wire Wire Line
|
|
3150 8750 3400 8750
|
|
Wire Wire Line
|
|
10600 1950 9250 1950
|
|
Wire Wire Line
|
|
10600 1750 9250 1750
|
|
Wire Wire Line
|
|
10600 1550 9250 1550
|
|
Wire Wire Line
|
|
4950 6650 5950 6650
|
|
Wire Wire Line
|
|
5950 6450 4950 6450
|
|
Wire Bus Line
|
|
10650 9150 9300 9150
|
|
Wire Wire Line
|
|
10650 8100 9300 8100
|
|
Wire Wire Line
|
|
10650 8500 9300 8500
|
|
Wire Wire Line
|
|
9300 8200 10650 8200
|
|
Wire Wire Line
|
|
10600 5850 9300 5850
|
|
Wire Bus Line
|
|
9300 7750 10650 7750
|
|
Wire Wire Line
|
|
9300 7550 10650 7550
|
|
Wire Wire Line
|
|
10600 1350 9250 1350
|
|
Wire Wire Line
|
|
10600 1150 9250 1150
|
|
Wire Wire Line
|
|
10600 950 9250 950
|
|
Wire Wire Line
|
|
9300 6850 10600 6850
|
|
Wire Wire Line
|
|
9300 6450 10600 6450
|
|
Wire Wire Line
|
|
10600 5950 9300 5950
|
|
Wire Wire Line
|
|
9300 5550 10600 5550
|
|
Wire Bus Line
|
|
4700 1300 5950 1300
|
|
Wire Wire Line
|
|
4700 950 5950 950
|
|
Wire Wire Line
|
|
4700 1900 5950 1900
|
|
Wire Wire Line
|
|
4700 2050 5950 2050
|
|
Wire Wire Line
|
|
4700 2400 5950 2400
|
|
Wire Wire Line
|
|
4700 4100 5950 4100
|
|
Wire Wire Line
|
|
4700 4700 5950 4700
|
|
Wire Bus Line
|
|
4700 3400 5950 3400
|
|
Wire Wire Line
|
|
4700 4450 5950 4450
|
|
Wire Wire Line
|
|
4700 3850 5950 3850
|
|
Wire Wire Line
|
|
4700 3550 5950 3550
|
|
Wire Bus Line
|
|
4700 1200 5950 1200
|
|
Wire Wire Line
|
|
5950 2250 4700 2250
|
|
Wire Wire Line
|
|
4700 4300 5950 4300
|
|
Wire Bus Line
|
|
5950 3250 5950 3200
|
|
Wire Bus Line
|
|
5950 3200 4700 3200
|
|
Wire Wire Line
|
|
4700 4200 5950 4200
|
|
Wire Wire Line
|
|
4700 2150 5950 2150
|
|
Wire Bus Line
|
|
4700 3300 5950 3300
|
|
Wire Wire Line
|
|
4700 3950 5950 3950
|
|
Wire Wire Line
|
|
4700 3650 5950 3650
|
|
Wire Wire Line
|
|
4700 4550 5950 4550
|
|
Wire Wire Line
|
|
4700 3050 5950 3050
|
|
Wire Wire Line
|
|
4700 2500 5950 2500
|
|
Wire Wire Line
|
|
4700 2650 5950 2650
|
|
Wire Wire Line
|
|
4700 1800 5950 1800
|
|
Wire Wire Line
|
|
4700 1600 5950 1600
|
|
Wire Wire Line
|
|
4700 1500 5950 1500
|
|
Wire Bus Line
|
|
4700 1100 5950 1100
|
|
Wire Wire Line
|
|
9300 5400 10600 5400
|
|
Wire Wire Line
|
|
9300 5650 10600 5650
|
|
Wire Wire Line
|
|
9300 6050 10600 6050
|
|
Wire Wire Line
|
|
9300 6350 10600 6350
|
|
Wire Wire Line
|
|
9300 6550 10600 6550
|
|
Wire Wire Line
|
|
9300 6750 10600 6750
|
|
Wire Wire Line
|
|
9300 6950 10600 6950
|
|
Wire Wire Line
|
|
10600 1050 9250 1050
|
|
Wire Wire Line
|
|
10600 1250 9250 1250
|
|
Wire Bus Line
|
|
9300 6650 10600 6650
|
|
Wire Bus Line
|
|
10600 6250 9300 6250
|
|
Wire Wire Line
|
|
9300 7650 10650 7650
|
|
Wire Wire Line
|
|
10600 5750 9300 5750
|
|
Wire Bus Line
|
|
10650 8700 9300 8700
|
|
Wire Wire Line
|
|
10650 8300 9300 8300
|
|
Wire Wire Line
|
|
10650 8400 9300 8400
|
|
Wire Wire Line
|
|
10650 8600 9300 8600
|
|
Wire Wire Line
|
|
10650 8950 9300 8950
|
|
Wire Wire Line
|
|
10650 9050 9300 9050
|
|
Wire Wire Line
|
|
5950 6550 4950 6550
|
|
Wire Wire Line
|
|
5950 6750 4950 6750
|
|
Wire Wire Line
|
|
10600 1650 9250 1650
|
|
Wire Wire Line
|
|
10600 1850 9250 1850
|
|
Wire Wire Line
|
|
3150 8600 3400 8600
|
|
Wire Wire Line
|
|
3150 8900 3400 8900
|
|
Wire Wire Line
|
|
3150 9200 3400 9200
|
|
Wire Bus Line
|
|
5950 9000 4950 9000
|
|
Wire Wire Line
|
|
4950 7700 5950 7700
|
|
Wire Wire Line
|
|
5950 7900 4950 7900
|
|
Wire Wire Line
|
|
4950 8100 5950 8100
|
|
Wire Wire Line
|
|
4950 8300 5950 8300
|
|
Wire Wire Line
|
|
4950 7500 5950 7500
|
|
Wire Wire Line
|
|
4950 8500 5950 8500
|
|
$Sheet
|
|
S 3400 7300 1550 2050
|
|
U 4C9E2AF4
|
|
F0 "Image Sensor" 60
|
|
F1 "sensor.sch" 60
|
|
F2 "+2.8_VDDIO" B L 3400 8750 60
|
|
F3 "+1.8_VDD" B L 3400 8900 60
|
|
F4 "+2.8_VAA" B L 3400 9200 60
|
|
F5 "+2.8_VAAPIX" B L 3400 9050 60
|
|
F6 "+2.8_VDDPLL" B L 3400 8600 60
|
|
F7 "IS_TRIGGER" I R 4950 7400 60
|
|
F8 "IS_FLASH" O R 4950 7500 60
|
|
F9 "IS_SDA" B R 4950 7600 60
|
|
F10 "IS_SCL" B R 4950 7700 60
|
|
F11 "IS_I2C_ADDR" I R 4950 7800 60
|
|
F12 "IS_EXTCLK" I R 4950 7900 60
|
|
F13 "IS_RESET_N" I R 4950 8000 60
|
|
F14 "IS_OE_N" I R 4950 8100 60
|
|
F15 "IS_STANDBY" I R 4950 8200 60
|
|
F16 "IS_TEST" I R 4950 8300 60
|
|
F17 "IS_PIXEL" O R 4950 8400 60
|
|
F18 "IS_LINE" O R 4950 8500 60
|
|
F19 "IS_FRAME" O R 4950 8600 60
|
|
F20 "IS_DOUT[0..11]" O R 4950 9000 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 2050 8300 1100 1000
|
|
U 4C9E2B0F
|
|
F0 "Snesor PSU" 60
|
|
F1 "sensor_psu.sch" 60
|
|
F2 "+2.8_VDDPLL" B R 3150 8600 60
|
|
F3 "+2.8_VDDIO" B R 3150 8750 60
|
|
F4 "+1.8_VDD" B R 3150 8900 60
|
|
F5 "+2.8_VAAPIX" B R 3150 9050 60
|
|
F6 "+2.8_VAA" B R 3150 9200 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 5950 5150 3350 4350
|
|
U 4C7BC2B2
|
|
F0 "FPGA, Port0, Port2, PROG IF" 60
|
|
F1 "FPGA_0_2_PROG.sch" 60
|
|
F2 "S6_TCK" I L 5950 6450 60
|
|
F3 "S6_TDI" I L 5950 6550 60
|
|
F4 "S6_TDO" O L 5950 6650 60
|
|
F5 "S6_TMS" I L 5950 6750 60
|
|
F6 "PROG_MISO[0..3]" B R 9300 9150 60
|
|
F7 "PROG_CCLK" O R 9300 9050 60
|
|
F8 "PROG_CSO" O R 9300 8950 60
|
|
F9 "NF_D[0..7]" B R 9300 8700 60
|
|
F10 "ETH_COL" B R 9300 5850 60
|
|
F11 "ETH_CRS" B R 9300 5750 60
|
|
F12 "NF_WE_N" O R 9300 8400 60
|
|
F13 "NF_ALE" O R 9300 8200 60
|
|
F14 "NF_CLE" O R 9300 8300 60
|
|
F15 "NF_CS1_N" O R 9300 8100 60
|
|
F16 "NF_RE_N" O R 9300 8500 60
|
|
F17 "NF_RNB" B R 9300 8600 60
|
|
F18 "SD_CLK" B R 9300 7550 60
|
|
F19 "SD_CMD" B R 9300 7650 60
|
|
F20 "SD_DAT[0..3]" B R 9300 7750 60
|
|
F21 "ETH_CLK" B R 9300 6950 60
|
|
F22 "ETH_RXC" B R 9300 5550 60
|
|
F23 "ETH_TXC" B R 9300 6550 60
|
|
F24 "ETH_TXD[0..3]" O R 9300 6650 60
|
|
F25 "ETH_TXEN" B R 9300 6750 60
|
|
F26 "ETH_TXER" B R 9300 6850 60
|
|
F27 "ETH_RXER" B R 9300 6450 60
|
|
F28 "ETH_RXDV" B R 9300 6350 60
|
|
F29 "ETH_RXD[0..3]" I R 9300 6250 60
|
|
F30 "ETH_RESET_N" B R 9300 5650 60
|
|
F31 "ETH_MDIO" B R 9300 5950 60
|
|
F32 "ETH_MDC" B R 9300 6050 60
|
|
F33 "ETH_INT" B R 9300 5400 60
|
|
F34 "IS_DOUT[0..11]" I L 5950 9000 60
|
|
F35 "IS_TEST" O L 5950 8300 60
|
|
F36 "IS_STANDBY" O L 5950 8200 60
|
|
F37 "IS_OE_N" O L 5950 8100 60
|
|
F38 "IS_RESET_N" O L 5950 8000 60
|
|
F39 "IS_EXTCLK" O L 5950 7900 60
|
|
F40 "IS_I2C_ADDR" O L 5950 7800 60
|
|
F41 "IS_SCL" B L 5950 7700 60
|
|
F42 "IS_SDA" B L 5950 7600 60
|
|
F43 "IS_FRAME" I L 5950 8600 60
|
|
F44 "IS_LINE" I L 5950 8500 60
|
|
F45 "IS_PIXEL" I L 5950 8400 60
|
|
F46 "IS_FLASH" I L 5950 7500 60
|
|
F47 "IS_TRIGGER" O L 5950 7400 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 5950 700 3300 4200
|
|
U 4C7BC2A2
|
|
F0 "FPGA Port 1, Port 3 DDR, USB" 60
|
|
F1 "FPGA_1_3.sch" 60
|
|
F2 "USBD_VP" B R 9250 1850 60
|
|
F3 "USBD_SPD" B R 9250 1550 60
|
|
F4 "USBD_OE_N" B R 9250 1650 60
|
|
F5 "USBD_RCV" B R 9250 1750 60
|
|
F6 "USBD_VM" B R 9250 1950 60
|
|
F7 "M0_CKE" O L 5950 4100 60
|
|
F8 "M0_UDM" O L 5950 3850 60
|
|
F9 "M0_UDQS" O L 5950 3550 60
|
|
F10 "M0_BA[0..1]" O L 5950 3400 60
|
|
F11 "M0_CAS#" O L 5950 4450 60
|
|
F12 "M0_RAS#" O L 5950 4550 60
|
|
F13 "M0_WE#" O L 5950 4700 60
|
|
F14 "M0_LDM" O L 5950 3950 60
|
|
F15 "M0_LDQS" O L 5950 3650 60
|
|
F16 "M1_UDQS" O L 5950 1500 60
|
|
F17 "M1_UDM" O L 5950 1800 60
|
|
F18 "M1_LDQS" O L 5950 1600 60
|
|
F19 "M1_LDM" O L 5950 1900 60
|
|
F20 "M1_WE#" O L 5950 2650 60
|
|
F21 "M1_CKE" O L 5950 2050 60
|
|
F22 "M1_RAS#" O L 5950 2500 60
|
|
F23 "M1_CAS#" O L 5950 2400 60
|
|
F24 "M1_BA[0..1]" O L 5950 1300 60
|
|
F25 "M1_CS#" O L 5950 950 60
|
|
F26 "USBA_VM" B R 9250 1350 60
|
|
F27 "USBA_VP" B R 9250 1250 60
|
|
F28 "USBA_RCV" B R 9250 1150 60
|
|
F29 "USBA_OE_N" B R 9250 1050 60
|
|
F30 "USBA_SPD" B R 9250 950 60
|
|
F31 "M1_DQ[0..15]" B L 5950 1100 60
|
|
F32 "M0_CS#" O L 5950 3050 60
|
|
F33 "M0_DQ[0..15]" B L 5950 3200 60
|
|
F34 "M0_A[0..12]" O L 5950 3300 60
|
|
F35 "M1_A[0..12]" O L 5950 1200 60
|
|
F36 "M1_CLK" O L 5950 2150 60
|
|
F37 "M1_CLK#" O L 5950 2250 60
|
|
F38 "M0_CLK" O L 5950 4200 60
|
|
F39 "M0_CLK#" O L 5950 4300 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 3750 6400 1200 700
|
|
U 4C716A4D
|
|
F0 "DBG_PRG" 60
|
|
F1 "DBG_PRG.sch" 60
|
|
F2 "FPGA_TDO" B R 4950 6650 60
|
|
F3 "FPGA_TDI" B R 4950 6550 60
|
|
F4 "FPGA_TMS" B R 4950 6750 60
|
|
F5 "FPGA_TCK" B R 4950 6450 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 3750 5400 1200 750
|
|
U 4C69ED5F
|
|
F0 "PSU" 60
|
|
F1 "PSU.sch" 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 10650 7350 1050 1950
|
|
U 4C4227FE
|
|
F0 "Non volatile memories" 60
|
|
F1 "NV_MEMORIES.sch" 60
|
|
F2 "SD_CMD" I L 10650 7650 60
|
|
F3 "SD_CLK" I L 10650 7550 60
|
|
F4 "SD_DAT[0..3]" B L 10650 7750 60
|
|
F5 "NF_D[0..7]" B L 10650 8700 60
|
|
F6 "NF_ALE" B L 10650 8200 60
|
|
F7 "NF_CLE" B L 10650 8300 60
|
|
F8 "NF_WE_N" B L 10650 8400 60
|
|
F9 "NF_CS1_N" B L 10650 8100 60
|
|
F10 "NF_RE_N" B L 10650 8500 60
|
|
F11 "NF_RNB" B L 10650 8600 60
|
|
F12 "SPI_CLK" I L 10650 9050 60
|
|
F13 "SPI_FLASH_CS#" I L 10650 8950 60
|
|
F14 "SPI_DQ[0..3]" B L 10650 9150 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 10600 900 1100 1150
|
|
U 4C5F1EDC
|
|
F0 "USB" 60
|
|
F1 "USB.sch" 60
|
|
F2 "USBA_SPD" B L 10600 950 60
|
|
F3 "USBA_OE_N" B L 10600 1050 60
|
|
F4 "USBA_RCV" B L 10600 1150 60
|
|
F5 "USBA_VP" B L 10600 1250 60
|
|
F6 "USBA_VM" B L 10600 1350 60
|
|
F7 "USBD_SPD" B L 10600 1550 60
|
|
F8 "USBD_OE_N" B L 10600 1650 60
|
|
F9 "USBD_RCV" B L 10600 1750 60
|
|
F10 "USBD_VP" B L 10600 1850 60
|
|
F11 "USBD_VM" B L 10600 1950 60
|
|
$EndSheet
|
|
Text Notes 12850 10750 0 60 ~ 0
|
|
Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
|
|
$Sheet
|
|
S 10600 5300 1300 1800
|
|
U 4C4320F3
|
|
F0 "Ethernet Phy" 60
|
|
F1 "eth_phy.sch" 60
|
|
F2 "ETH_RXC" O L 10600 5550 60
|
|
F3 "ETH_RST_N" I L 10600 5650 60
|
|
F4 "ETH_CRS" O L 10600 5750 60
|
|
F5 "ETH_COL" O L 10600 5850 60
|
|
F6 "ETH_MDIO" B L 10600 5950 60
|
|
F7 "ETH_MDC" I L 10600 6050 60
|
|
F8 "ETH_RXD[0..3]" O L 10600 6250 60
|
|
F9 "ETH_RXDV" O L 10600 6350 60
|
|
F10 "ETH_RXER" O L 10600 6450 60
|
|
F11 "ETH_TXC" B L 10600 6550 60
|
|
F12 "ETH_TXD[0..3]" I L 10600 6650 60
|
|
F13 "ETH_TXEN" I L 10600 6750 60
|
|
F14 "ETH_TXER" I L 10600 6850 60
|
|
F15 "ETH_CLK" I L 10600 6950 60
|
|
F16 "ETH_INT" O L 10600 5400 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 3600 850 1100 4000
|
|
U 4C421DD3
|
|
F0 "DDR Banks" 60
|
|
F1 "DRAM.sch" 60
|
|
F2 "M0_BA[0..1]" I R 4700 3400 60
|
|
F3 "M1_BA[0..1]" I R 4700 1300 60
|
|
F4 "M0_WE#" I R 4700 4700 60
|
|
F5 "M0_RAS#" I R 4700 4550 60
|
|
F6 "M1_RAS#" I R 4700 2500 60
|
|
F7 "M1_WE#" I R 4700 2650 60
|
|
F8 "M0_CAS#" I R 4700 4450 60
|
|
F9 "M0_CKE" I R 4700 4100 60
|
|
F10 "M0_CLK" I R 4700 4200 60
|
|
F11 "M0_CLK#" I R 4700 4300 60
|
|
F12 "M0_CS#" I R 4700 3050 60
|
|
F13 "M1_CLK#" I R 4700 2250 60
|
|
F14 "M1_CLK" I R 4700 2150 60
|
|
F15 "M1_CKE" I R 4700 2050 60
|
|
F16 "M1_CAS#" I R 4700 2400 60
|
|
F17 "M0_DQ[0..15]" B R 4700 3200 60
|
|
F18 "M0_UDM" I R 4700 3850 60
|
|
F19 "M0_LDQS" I R 4700 3650 60
|
|
F20 "M0_A[0..12]" I R 4700 3300 60
|
|
F21 "M0_LDM" I R 4700 3950 60
|
|
F22 "M0_UDQS" I R 4700 3550 60
|
|
F23 "M1_UDQS" I R 4700 1500 60
|
|
F24 "M1_LDM" I R 4700 1900 60
|
|
F25 "M1_LDQS" I R 4700 1600 60
|
|
F26 "M1_UDM" I R 4700 1800 60
|
|
F27 "M1_CS#" I R 4700 950 60
|
|
F28 "M1_A[0..12]" I R 4700 1200 60
|
|
F29 "M1_DQ[0..15]" B R 4700 1100 60
|
|
$EndSheet
|
|
$EndSCHEMATC
|