Andres Calderon 5197a47953 ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00

..

clean

chie renamed to xue

2010-07-24 14:02:57 -05:00

DRAM.sch

ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00

eth_phy.sch

ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00

FPGA.sch

ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00

NV_MEMORIES.sch

ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00

xue-rnc-cache.lib

ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00

xue-rnc.brd

ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00

xue-rnc.cache.dcm

some ethernet phy conections

2010-07-27 20:09:20 -05:00

xue-rnc.cache.lib

some ethernet phy conections

2010-07-27 20:09:20 -05:00

xue-rnc.cmp

ddr mobile replaced by ddr

2010-08-03 21:23:17 -05:00

xue-rnc.net

ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00

xue-rnc.pro

ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00

xue-rnc.sch

ddr address and data has been conected to the FPGA

2010-08-04 20:50:31 -05:00