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Code
5c25d1c015
xue/kicad/xue-rnc/xue-rnc.net
Andres Calderon 5c25d1c015 DDR0 termaintor placement
2010-08-16 23:30:34 -05:00

3044 lines
52 KiB
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# EESchema Netlist Version 1.1 created Mon 16 Aug 2010 11:28:07 PM COT
(
( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF}
( PAD GND )
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 ? )
( 7 ? )
( 8 GND )
( 9 ? )
( 10 ? )
( 11 ? )
( 12 ? )
( 13 ? )
( 14 ? )
( 15 ? )
( 16 ? )
( 17 ? )
( 18 ? )
( 19 ? )
( 20 ? )
)
( /4C4227FE/4C6969AB $noname C75 100nF {Lib=C}
( 1 GND )
( 2 +3.3V )
)
( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D67C 0402 C73 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D661 0402 C72 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB}
( 1 /FPGA_Spartan6/PROG_CSO )
( 2 /FPGA_Spartan6/PROG_MISO1 )
( 3 /FPGA_Spartan6/PROG_MISO2 )
( 4 GND )
( 5 /FPGA_Spartan6/PROG_MISO0 )
( 6 /FPGA_Spartan6/PROG_CCLK )
( 7 /FPGA_Spartan6/PROG_MISO3 )
( 8 VCCO2 )
)
( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD}
( CASE GND )
( COM GND )
( CD ? )
( 1 /Non_volatile_memories/SD_DAT2 )
( 2 /FPGA_Spartan6/SD_DAT3 )
( 3 /Non_volatile_memories/SD_CMD )
( 4 +3.3V )
( 5 /Non_volatile_memories/SD_CLK )
( 6 GND )
( 7 /FPGA_Spartan6/SD_DAT0 )
( 8 /Non_volatile_memories/SD_DAT1 )
)
( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M}
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 /FPGA_Spartan6/NF_RNB )
( 7 /FPGA_Spartan6/NF_RNB )
( 8 /FPGA_Spartan6/NF_RE_N )
( 9 /Non_volatile_memories/NF_CS1_N )
( 10 ? )
( 11 ? )
( 12 +3.3V )
( 13 GND )
( 14 ? )
( 15 ? )
( 16 /Non_volatile_memories/NF_CLE )
( 17 /FPGA_Spartan6/NF_ALE )
( 18 /FPGA_Spartan6/NF_WE_N )
( 19 +3.3V )
( 20 ? )
( 21 ? )
( 22 ? )
( 23 ? )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 ? )
( 29 /FPGA_Spartan6/NF_D0 )
( 30 /Non_volatile_memories/NF_D1 )
( 31 /Non_volatile_memories/NF_D2 )
( 32 /Non_volatile_memories/NF_D3 )
( 33 ? )
( 34 ? )
( 35 ? )
( 36 GND )
( 37 +3.3V )
( 38 ? )
( 39 ? )
( 40 ? )
( 41 /FPGA_Spartan6/NF_D4 )
( 42 /Non_volatile_memories/NF_D5 )
( 43 /FPGA_Spartan6/NF_D6 )
( 44 /Non_volatile_memories/NF_D7 )
( 45 ? )
( 46 ? )
( 47 ? )
( 48 ? )
)
( /4C5F1EDC/4C6552BF $noname U7 MIC2550AYTS {Lib=MIC2550AYTS}
( 1 +2.5V )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 7 GND )
( 8 GND )
( 9 ? )
( 10 N-000428 )
( 11 N-000429 )
( 12 +3.3V )
( 14 +3.3V )
)
( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BD $noname C36 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BC $noname C37 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F}
( 1 N-000422 )
( 2 +5V )
)
( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000428 )
( 2 GND )
)
( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000429 )
( 2 GND )
)
( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C}
( 1 N-000430 )
( 2 GND )
)
( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R}
( 1 N-000430 )
( 2 GND )
)
( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR}
( 1 ? )
( 2 GND )
)
( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR}
( 1 N-000422 )
( 2 ? )
)
( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR}
( 1 N-000425 )
( 2 N-000426 )
)
( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR}
( 1 N-000420 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R}
( 1 N-000421 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C}
( 1 N-000421 )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000427 )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000419 )
( 2 GND )
)
( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F}
( 1 N-000425 )
( 2 +5V )
)
( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001}
( S1 N-000421 )
( S2 N-000421 )
( S3 N-000421 )
( S4 N-000421 )
( 1 N-000426 )
( 2 N-000419 )
( 3 N-000427 )
( 4 N-000420 )
)
( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS}
( 1 +2.5V )
( 2 /FPGA_Spartan6/USBA_SPD )
( 3 /USB/USBA_RCV )
( 4 /FPGA_Spartan6/USBA_VP )
( 5 /USB/USBA_VM )
( 7 GND )
( 8 GND )
( 9 /FPGA_Spartan6/USBA_OE_N )
( 10 N-000419 )
( 11 N-000427 )
( 12 +3.3V )
( 14 +3.3V )
)
( /4C431A63/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M0_A0 )
( 2 /FPGA_Spartan6/R_M0_A1 )
( 3 /FPGA_Spartan6/R_M0_A2 )
( 4 /FPGA_Spartan6/R_M0_A3 )
( 5 /DDR_Banks/M0_A3 )
( 6 /FPGA_Spartan6/M0_A2 )
( 7 /FPGA_Spartan6/M0_A1 )
( 8 /FPGA_Spartan6/M0_A0 )
)
( /4C431A63/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4}
( 1 ? )
( 2 /FPGA_Spartan6/R_M0_BA0 )
( 3 /FPGA_Spartan6/R_M0_BA1 )
( 4 /FPGA_Spartan6/R_M0_A10 )
( 5 /FPGA_Spartan6/M0_A10 )
( 6 /FPGA_Spartan6/M0_BA1 )
( 7 /DDR_Banks/M0_BA0 )
( 8 /FPGA_Spartan6/M0_RAS# )
)
( /4C431A63/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4}
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 /DDR_Banks/M0_CAS# )
( 6 /FPGA_Spartan6/M0_WE# )
( 7 /FPGA_Spartan6/M0_LDM )
( 8 /FPGA_Spartan6/M0_LDQS )
)
( /4C431A63/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M0_A7 )
( 2 /FPGA_Spartan6/R_M0_A6 )
( 3 /FPGA_Spartan6/R_M0_A5 )
( 4 /FPGA_Spartan6/R_M0_A4 )
( 5 /DDR_Banks/M0_A4 )
( 6 /FPGA_Spartan6/M0_A5 )
( 7 /FPGA_Spartan6/M0_A6 )
( 8 /DDR_Banks/M0_A7 )
)
( /4C431A63/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M0_A12 )
( 2 /FPGA_Spartan6/R_M0_A11 )
( 3 /FPGA_Spartan6/R_M0_A9 )
( 4 /FPGA_Spartan6/R_M0_A8 )
( 5 /FPGA_Spartan6/M0_A8 )
( 6 /FPGA_Spartan6/M0_A9 )
( 7 /DDR_Banks/M0_A11 )
( 8 /DDR_Banks/M0_A12 )
)
( /4C431A63/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M0_DQ4 )
( 2 /FPGA_Spartan6/R_M0_DQ5 )
( 3 /FPGA_Spartan6/R_M0_DQ6 )
( 4 /FPGA_Spartan6/R_M0_DQ7 )
( 5 /DDR_Banks/M0_DQ7 )
( 6 /FPGA_Spartan6/M0_DQ6 )
( 7 /FPGA_Spartan6/M0_DQ5 )
( 8 /FPGA_Spartan6/M0_DQ4 )
)
( /4C431A63/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M0_DQ0 )
( 2 /FPGA_Spartan6/R_M0_DQ1 )
( 3 /FPGA_Spartan6/R_M0_DQ2 )
( 4 /FPGA_Spartan6/R_M0_DQ3 )
( 5 /FPGA_Spartan6/M0_DQ3 )
( 6 /FPGA_Spartan6/M0_DQ2 )
( 7 /FPGA_Spartan6/M0_DQ1 )
( 8 /DDR_Banks/M0_DQ0 )
)
( /4C431A63/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M0_DQ8 )
( 2 /FPGA_Spartan6/R_M0_DQ9 )
( 3 /FPGA_Spartan6/R_M0_DQ10 )
( 4 /FPGA_Spartan6/R_M0_DQ11 )
( 5 /FPGA_Spartan6/M0_DQ11 )
( 6 /FPGA_Spartan6/M0_DQ10 )
( 7 /FPGA_Spartan6/M0_DQ9 )
( 8 /FPGA_Spartan6/M0_DQ8 )
)
( /4C431A63/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M0_DQ12 )
( 2 /FPGA_Spartan6/R_M0_DQ13 )
( 3 /FPGA_Spartan6/R_M0_DQ14 )
( 4 /FPGA_Spartan6/R_M0_DQ15 )
( 5 /FPGA_Spartan6/M0_DQ15 )
( 6 /FPGA_Spartan6/M0_DQ14 )
( 7 /DDR_Banks/M0_DQ13 )
( 8 /DDR_Banks/M0_DQ12 )
)
( /4C431A63/4C69E7DD 0402 R19 33 {Lib=R}
( 1 /FPGA_Spartan6/R_M1_UDQS )
( 2 /DDR_Banks/M1_UDQS )
)
( /4C431A63/4C69E92D 0402 R20 33 {Lib=R}
( 1 /FPGA_Spartan6/R_M1_CS# )
( 2 /FPGA_Spartan6/M1_CS# )
)
( /4C431A63/4C69E7F8 0402 R17 33 {Lib=R}
( 1 /FPGA_Spartan6/R_M1_CKE )
( 2 /FPGA_Spartan6/M1_CKE )
)
( /4C431A63/4C69E7C2 0402 R18 33 {Lib=R}
( 1 /FPGA_Spartan6/R_M1_UDM )
( 2 /DDR_Banks/M1_UDM )
)
( /4C431A63/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_DQ11 )
( 2 /FPGA_Spartan6/R_M1_DQ10 )
( 3 /FPGA_Spartan6/R_M1_DQ9 )
( 4 /FPGA_Spartan6/R_M1_DQ8 )
( 5 /FPGA_Spartan6/M1_DQ8 )
( 6 /FPGA_Spartan6/M1_DQ9 )
( 7 /FPGA_Spartan6/M1_DQ10 )
( 8 /FPGA_Spartan6/M1_DQ11 )
)
( /4C431A63/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_DQ15 )
( 2 /FPGA_Spartan6/R_M1_DQ14 )
( 3 /FPGA_Spartan6/R_M1_DQ13 )
( 4 /FPGA_Spartan6/R_M1_DQ12 )
( 5 /FPGA_Spartan6/M1_DQ12 )
( 6 /FPGA_Spartan6/M1_DQ13 )
( 7 /DDR_Banks/M1_DQ14 )
( 8 /DDR_Banks/M1_DQ15 )
)
( /4C431A63/4C69DF7A 0402 R16 120 {Lib=R}
( 1 /DDR_Banks/M1_CLK# )
( 2 /DDR_Banks/M1_CLK )
)
( /4C431A63/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_A12 )
( 2 /FPGA_Spartan6/R_M1_A11 )
( 3 /FPGA_Spartan6/R_M1_A9 )
( 4 /FPGA_Spartan6/R_M1_A8 )
( 5 /FPGA_Spartan6/M1_A8 )
( 6 /FPGA_Spartan6/M1_A9 )
( 7 /FPGA_Spartan6/M1_A11 )
( 8 /DDR_Banks/M1_A12 )
)
( /4C431A63/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_A7 )
( 2 /FPGA_Spartan6/R_M1_A6 )
( 3 /FPGA_Spartan6/R_M1_A5 )
( 4 ? )
( 5 /DDR_Banks/M1_A4 )
( 6 /FPGA_Spartan6/M1_A5 )
( 7 /FPGA_Spartan6/M1_A6 )
( 8 /FPGA_Spartan6/M1_A7 )
)
( /4C431A63/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_DQ0 )
( 2 /FPGA_Spartan6/R_M1_DQ1 )
( 3 /FPGA_Spartan6/R_M1_DQ2 )
( 4 /FPGA_Spartan6/R_M1_DQ3 )
( 5 /FPGA_Spartan6/M1_DQ3 )
( 6 /DDR_Banks/M1_DQ2 )
( 7 /DDR_Banks/M1_DQ1 )
( 8 /DDR_Banks/M1_DQ0 )
)
( /4C431A63/4C69D3A4 $noname RP3 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_LDQS )
( 2 /FPGA_Spartan6/R_M1_LDM )
( 3 /FPGA_Spartan6/R_M1_WE# )
( 4 /FPGA_Spartan6/R_M1_CAS# )
( 5 /DDR_Banks/M1_CAS# )
( 6 /FPGA_Spartan6/M1_WE# )
( 7 /DDR_Banks/M1_LDM )
( 8 /DDR_Banks/M1_LDQS )
)
( /4C431A63/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_DQ4 )
( 2 /FPGA_Spartan6/R_M1_DQ5 )
( 3 /FPGA_Spartan6/R_M1_DQ6 )
( 4 /FPGA_Spartan6/R_M1_DQ7 )
( 5 /FPGA_Spartan6/M1_DQ7 )
( 6 /FPGA_Spartan6/M1_DQ6 )
( 7 /DDR_Banks/M1_DQ5 )
( 8 /FPGA_Spartan6/M1_DQ4 )
)
( /4C431A63/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_RAS# )
( 2 /FPGA_Spartan6/R_M1_BA0 )
( 3 /FPGA_Spartan6/R_M1_BA1 )
( 4 /FPGA_Spartan6/R_M1_A10 )
( 5 /FPGA_Spartan6/M1_A10 )
( 6 /FPGA_Spartan6/M1_BA1 )
( 7 /DDR_Banks/M1_BA0 )
( 8 /DDR_Banks/M1_RAS# )
)
( /4C431A63/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_A0 )
( 2 /FPGA_Spartan6/R_M1_A1 )
( 3 /FPGA_Spartan6/R_M1_A2 )
( 4 /FPGA_Spartan6/R_M1_A3 )
( 5 /FPGA_Spartan6/M1_A3 )
( 6 /FPGA_Spartan6/M1_A2 )
( 7 /FPGA_Spartan6/M1_A1 )
( 8 /DDR_Banks/M1_A0 )
)
( /4C431A63/4C656D9D $noname C66 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D9A $noname C63 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D99 $noname C60 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D98 $noname C57 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D97 $noname C54 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D53 $noname C69 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D49 $noname C67 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D46 $noname C64 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D45 $noname C61 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D44 $noname C58 4.7uF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D43 $noname C55 100uF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D08 $noname C68 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CFC $noname C65 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CFB $noname C62 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CFA $noname C59 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CF9 $noname C56 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CBB $noname C50 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656CBA $noname C47 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656CB9 $noname C44 4.7uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656CB7 $noname C41 100uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656C49 $noname C53 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656C27 $noname C51 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656C24 $noname C49 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656C16 $noname C46 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656BFA $noname C52 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656BF9 $noname C43 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656BF8 $noname C40 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656AC2 $noname C48 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656AC0 $noname C45 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656ABD $noname C42 4.7uF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656A80 $noname C39 100uF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
( H8 ? )
( P7 ? )
( N7 ? )
( M7 ? )
( L7 +2.5V )
( K7 ? )
( J7 ? )
( G7 ? )
( F7 ? )
( P6 ? )
( N6 ? )
( M6 ? )
( L6 ? )
( K6 /FPGA_Spartan6/R_M0_A3 )
( J6 ? )
( H6 /FPGA_Spartan6/R_M0_A7 )
( G6 ? )
( F6 +2.5V )
( E6 ? )
( U5 +2.5V )
( P5 ? )
( N5 +2.5V )
( M5 ? )
( K5 /FPGA_Spartan6/M0_RAS# )
( J5 +2.5V )
( H5 /FPGA_Spartan6/R_M0_A2 )
( F5 ? )
( E5 ? )
( D5 ? )
( U4 ? )
( K21 /FPGA_Spartan6/R_M1_DQ6 )
( H21 /FPGA_Spartan6/R_M1_RAS# )
( G21 +2.5V )
( F21 /FPGA_Spartan6/R_M1_A0 )
( D21 /FPGA_Spartan6/R_M1_CKE )
( C21 +2.5V )
( B21 ? )
( A21 ? )
( W20 ? )
( V20 ? )
( U20 /FPGA_Spartan6/R_M1_DQ12 )
( T20 ? )
( R20 /FPGA_Spartan6/R_M1_DQ10 )
( P20 ? )
( N20 /FPGA_Spartan6/R_M1_DQ0 )
( M20 /FPGA_Spartan6/R_M1_UDM )
( L20 /FPGA_Spartan6/R_M1_LDQS )
( K20 /FPGA_Spartan6/R_M1_A5 )
( J20 /FPGA_Spartan6/R_M1_DQ4 )
( H20 /DDR_Banks/M1_CLK )
( G20 /FPGA_Spartan6/R_M1_A3 )
( F20 ? )
( E20 /FPGA_Spartan6/R_M1_A7 )
( D20 ? )
( C20 /FPGA_Spartan6/R_M1_A8 )
( B20 ? )
( A20 ? )
( P8 ? )
( M8 ? )
( K8 ? )
( Y2 ? )
( W2 +2.5V )
( V2 /FPGA_Spartan6/R_M0_DQ14 )
( T2 /FPGA_Spartan6/M0_UDQS )
( R2 +2.5V )
( P2 /FPGA_Spartan6/R_M0_DQ8 )
( M2 /FPGA_Spartan6/R_M0_DQ2 )
( L2 +2.5V )
( K2 /FPGA_Spartan6/R_M0_DQ6 )
( H2 /FPGA_Spartan6/R_M0_A0 )
( G2 +2.5V )
( F2 /FPGA_Spartan6/M0_WE# )
( D2 /FPGA_Spartan6/M0_CKE )
( C2 +2.5V )
( B2 ? )
( A2 ? )
( Y1 ? )
( W1 ? )
( V1 /FPGA_Spartan6/R_M0_DQ15 )
( U1 /FPGA_Spartan6/R_M0_DQ13 )
( T1 ? )
( R1 /FPGA_Spartan6/R_M0_DQ11 )
( P1 /FPGA_Spartan6/R_M0_DQ9 )
( N1 /FPGA_Spartan6/R_M0_DQ1 )
( M1 /FPGA_Spartan6/R_M0_DQ3 )
( L1 ? )
( K1 /FPGA_Spartan6/R_M0_DQ7 )
( J1 /FPGA_Spartan6/R_M0_DQ5 )
( H1 /FPGA_Spartan6/R_M0_A1 )
( G1 /FPGA_Spartan6/R_M0_BA1 )
( T4 ? )
( R4 ? )
( P4 ? )
( N4 ? )
( M4 ? )
( L4 /FPGA_Spartan6/M0_LDM )
( K4 /DDR_Banks/M0_CAS# )
( J4 /FPGA_Spartan6/R_M0_A6 )
( H4 /FPGA_Spartan6/M0_CLK )
( G4 /FPGA_Spartan6/R_M0_A10 )
( F4 +2.5V )
( E4 ? )
( C4 ? )
( W3 ? )
( V3 ? )
( U3 /FPGA_Spartan6/R_M0_DQ12 )
( T3 ? )
( R3 /FPGA_Spartan6/R_M0_DQ10 )
( P3 ? )
( N3 /FPGA_Spartan6/R_M0_DQ0 )
( M3 /FPGA_Spartan6/M0_UDM )
( L3 /FPGA_Spartan6/M0_LDQS )
( K3 /FPGA_Spartan6/R_M0_A5 )
( J3 /FPGA_Spartan6/R_M0_DQ4 )
( H3 /FPGA_Spartan6/M0_CLK# )
( G3 /FPGA_Spartan6/R_M0_BA0 )
( F3 /FPGA_Spartan6/R_M0_A4 )
( E3 /FPGA_Spartan6/R_M0_A8 )
( D3 ? )
( C3 ? )
( B3 ? )
( G10 +3.3V )
( D10 /FPGA_Spartan6/ETH_MDC )
( C10 /FPGA_Spartan6/ETH_CRS )
( B10 /FPGA_Spartan6/ETH_COL )
( A10 /FPGA_Spartan6/ETH_INT )
( E9 +3.3V )
( D9 /FPGA_Spartan6/ETH_TXD0 )
( C9 /FPGA_Spartan6/ETH_TXD2 )
( A9 /Ethernet_Phy/ETH_TXD3 )
( D8 /FPGA_Spartan6/ETH_RXC )
( C8 /FPGA_Spartan6/ETH_TXD1 )
( B8 /FPGA_Spartan6/ETH_TXER )
( A8 /Ethernet_Phy/ETH_TXEN )
( D7 /Ethernet_Phy/ETH_TXC )
( C7 /FPGA_Spartan6/ETH_RXDV )
( B7 +3.3V )
( A7 /FPGA_Spartan6/ETH_RXER )
( D6 /FPGA_Spartan6/ETH_RXD3 )
( C6 /FPGA_Spartan6/ETH_RXD2 )
( B6 /Ethernet_Phy/ETH_RXD1 )
( A6 /Ethernet_Phy/ETH_RXD0 )
( C5 /FPGA_Spartan6/ETH_MDIO )
( A5 /FPGA_Spartan6/ETH_RESET_N )
( B4 +3.3V )
( A4 /Ethernet_Phy/ETH_CLK )
( A3 ? )
( U19 ? )
( T19 ? )
( R19 /FPGA_Spartan6/USBA_SPD )
( P19 ? )
( B19 +3.3V )
( B18 /Non_volatile_memories/SD_DAT1 )
( A18 /FPGA_Spartan6/SD_DAT0 )
( E17 +3.3V )
( D17 /Non_volatile_memories/SD_CMD )
( C17 /FPGA_Spartan6/SD_DAT3 )
( A17 /Non_volatile_memories/SD_DAT2 )
( E16 /Non_volatile_memories/SD_CLK )
( C16 /Non_volatile_memories/NF_CS1_N )
( B16 /FPGA_Spartan6/NF_RE_N )
( A16 /FPGA_Spartan6/NF_RNB )
( D15 /Non_volatile_memories/NF_CLE )
( C15 /FPGA_Spartan6/NF_WE_N )
( B15 +3.3V )
( A15 /FPGA_Spartan6/NF_ALE )
( G14 +3.3V )
( D14 /FPGA_Spartan6/NF_D0 )
( C14 ? )
( B14 ? )
( A14 ? )
( E13 +3.3V )
( C13 /Non_volatile_memories/NF_D2 )
( A13 /Non_volatile_memories/NF_D1 )
( C12 /Non_volatile_memories/NF_D5 )
( B12 /FPGA_Spartan6/NF_D4 )
( A12 /Non_volatile_memories/NF_D3 )
( D11 /FPGA_Spartan6/NF_D6 )
( C11 ? )
( B11 +3.3V )
( A11 /Non_volatile_memories/NF_D7 )
( J16 ? )
( H16 /FPGA_Spartan6/R_M1_CS# )
( G16 ? )
( F16 ? )
( L15 ? )
( W22 ? )
( V22 /FPGA_Spartan6/R_M1_DQ15 )
( U22 /FPGA_Spartan6/R_M1_DQ13 )
( T22 ? )
( R22 /FPGA_Spartan6/R_M1_DQ11 )
( P22 /FPGA_Spartan6/R_M1_DQ9 )
( N22 /FPGA_Spartan6/R_M1_DQ1 )
( M22 /FPGA_Spartan6/R_M1_DQ3 )
( L22 ? )
( K22 /FPGA_Spartan6/R_M1_DQ7 )
( J22 /FPGA_Spartan6/R_M1_DQ5 )
( H22 /FPGA_Spartan6/R_M1_CAS# )
( G22 ? )
( F22 /FPGA_Spartan6/R_M1_A1 )
( E22 /FPGA_Spartan6/R_M1_A2 )
( D22 /FPGA_Spartan6/R_M1_A12 )
( C22 /FPGA_Spartan6/R_M1_A9 )
( B22 ? )
( W21 +2.5V )
( V21 /FPGA_Spartan6/R_M1_DQ14 )
( T21 /FPGA_Spartan6/R_M1_UDQS )
( R21 +2.5V )
( P21 /FPGA_Spartan6/R_M1_DQ8 )
( M21 /FPGA_Spartan6/R_M1_DQ2 )
( L21 +2.5V )
( N19 ? )
( M19 ? )
( L19 /FPGA_Spartan6/R_M1_LDM )
( K19 /FPGA_Spartan6/R_M1_A6 )
( J19 /DDR_Banks/M1_CLK# )
( H19 /FPGA_Spartan6/R_M1_WE# )
( G19 /FPGA_Spartan6/R_M1_A10 )
( F19 /FPGA_Spartan6/R_M1_A11 )
( E19 +2.5V )
( D19 ? )
( C19 ? )
( U18 +2.5V )
( P18 /FPGA_Spartan6/USBA_OE_N )
( N18 +2.5V )
( M18 /USB/USBA_VM )
( K18 ? )
( J18 +2.5V )
( H18 ? )
( F18 ? )
( P17 /FPGA_Spartan6/USBA_VP )
( M17 ? )
( L17 ? )
( K17 /FPGA_Spartan6/R_M1_BA1 )
( J17 /FPGA_Spartan6/R_M1_BA0 )
( H17 ? )
( G17 ? )
( F17 ? )
( N16 /USB/USBA_RCV )
( M16 ? )
( L16 +2.5V )
( K16 ? )
( J14 +1.2V )
( H14 ? )
( F14 ? )
( E14 ? )
( P13 +1.2V )
( N13 GND )
( M13 +1.2V )
( L13 GND )
( K13 +1.2V )
( J13 GND )
( H13 ? )
( G13 ? )
( F13 ? )
( D13 ? )
( B13 GND )
( Y22 ? )
( A22 GND )
( R12 +2.5V )
( P12 GND )
( N12 +1.2V )
( M12 GND )
( L12 +1.2V )
( K12 GND )
( J12 +1.2V )
( H12 ? )
( G12 +2.5V )
( F12 ? )
( E12 ? )
( D12 ? )
( AB1 GND )
( A19 ? )
( R18 GND )
( L18 GND )
( G18 GND )
( E18 ? )
( D18 GND )
( C18 ? )
( R17 ? )
( N17 GND )
( B17 GND )
( W16 GND )
( P16 ? )
( D16 +2.5V )
( AA5 GND )
( P15 ? )
( N15 ? )
( M15 +2.5V )
( K15 +2.5V )
( J15 GND )
( H15 +2.5V )
( G15 ? )
( F15 ? )
( E15 GND )
( V14 GND )
( R14 +1.2V )
( P14 GND )
( N14 +1.2V )
( M14 GND )
( L14 +1.2V )
( K14 GND )
( L9 GND )
( K9 +1.2V )
( J9 GND )
( H9 +2.5V )
( G9 ? )
( F9 ? )
( B9 GND )
( N8 +2.5V )
( L8 +2.5V )
( J8 +1.2V )
( G8 ? )
( F8 ? )
( E8 ? )
( W7 GND )
( U7 GND )
( H7 GND )
( E7 GND )
( V6 +2.5V )
( R6 +2.5V )
( R5 GND )
( L5 GND )
( G5 GND )
( B5 GND )
( V4 GND )
( D4 GND )
( U2 GND )
( N2 GND )
( J2 GND )
( E2 GND )
( A1 GND )
( AA1 ? )
( U21 GND )
( N21 GND )
( J21 GND )
( E21 GND )
( U11 +2.5V )
( P11 +1.2V )
( N11 GND )
( M11 +1.2V )
( L11 GND )
( K11 +1.2V )
( J11 GND )
( H11 ? )
( G11 ? )
( F11 +2.5V )
( E11 GND )
( Y20 ? )
( V10 GND )
( R10 +2.5V )
( P10 GND )
( N10 +1.2V )
( M10 GND )
( L10 +1.2V )
( K10 GND )
( J10 +1.2V )
( H10 ? )
( F10 ? )
( E10 ? )
( P9 +1.2V )
( N9 GND )
( M9 +1.2V )
( V19 ? )
( AB8 ? )
( AA8 ? )
( Y18 ? )
( W18 ? )
( V18 ? )
( T18 ? )
( AB7 ? )
( AA7 VCCO2 )
( Y17 ? )
( W17 ? )
( V17 ? )
( U17 ? )
( T17 ? )
( AB6 ? )
( AA6 ? )
( Y16 ? )
( V16 VCCO2 )
( U16 ? )
( T16 ? )
( R16 ? )
( AB5 ? )
( Y15 ? )
( W15 ? )
( V15 ? )
( U15 ? )
( T15 ? )
( R15 ? )
( AB4 ? )
( AA4 ? )
( F1 ? )
( E1 /FPGA_Spartan6/R_M0_A9 )
( D1 /FPGA_Spartan6/R_M0_A12 )
( C1 /FPGA_Spartan6/R_M0_A11 )
( B1 ? )
( AB19 ? )
( AA19 VCCO2 )
( AB18 ? )
( AA18 ? )
( AB17 ? )
( AB16 ? )
( AA16 ? )
( AB15 ? )
( AA15 VCCO2 )
( AB14 ? )
( AA14 ? )
( AB13 ? )
( AA22 ? )
( AB12 ? )
( AA12 ? )
( AB21 ? )
( AA21 /FPGA_Spartan6/PROG_CCLK )
( AB11 ? )
( AA11 VCCO2 )
( AB20 /FPGA_Spartan6/PROG_MISO0 )
( AA20 /FPGA_Spartan6/PROG_MISO1 )
( AB10 ? )
( AA10 ? )
( AB9 ? )
( Y19 ? )
( V9 ? )
( U9 ? )
( T9 VCCO2 )
( R9 ? )
( Y8 ? )
( W8 ? )
( V8 VCCO2 )
( U8 ? )
( T8 ? )
( R8 ? )
( Y7 ? )
( V7 ? )
( T7 ? )
( R7 ? )
( Y6 ? )
( W6 ? )
( U6 ? )
( T6 ? )
( Y5 ? )
( W5 VCCO2 )
( V5 ? )
( T5 /FPGA_Spartan6/PROG_CSO )
( Y4 ? )
( W4 ? )
( Y3 ? )
( AA17 GND )
( AA13 GND )
( AB22 GND )
( AA9 GND )
( W19 GND )
( Y14 ? )
( W14 ? )
( U14 /FPGA_Spartan6/PROG_MISO2 )
( T14 ? )
( AB3 ? )
( AA3 VCCO2 )
( Y13 ? )
( W13 ? )
( V13 ? )
( U13 /FPGA_Spartan6/PROG_MISO3 )
( T13 VCCO2 )
( R13 ? )
( AB2 ? )
( AA2 ? )
( Y12 ? )
( W12 ? )
( V12 VCCO2 )
( U12 ? )
( T12 ? )
( Y21 ? )
( Y11 ? )
( W11 ? )
( V11 ? )
( T11 ? )
( R11 ? )
( Y10 ? )
( W10 ? )
( U10 ? )
( T10 ? )
( Y9 ? )
( W9 ? )
)
( /4C4320F3/4C5D8114 $noname C9 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_PLL1.8V )
( 2 GND )
)
( /4C4320F3/4C5D810A 0402 L3 FB {Lib=INDUCTOR}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 /Ethernet_Phy/ETH_PLL1.8V )
)
( /4C4320F3/4C5D8104 $noname C6 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 GND )
)
( /4C4320F3/4C5D80F3 0402 L1 FB {Lib=INDUCTOR}
( 1 +1.8V )
( 2 /Ethernet_Phy/ETH_A1.8V )
)
( /4C4320F3/4C5D80F0 $noname C4 100nF {Lib=C}
( 1 +1.8V )
( 2 GND )
)
( /4C4320F3/4C5D80ED $noname C2 1uF {Lib=C}
( 1 +1.8V )
( 2 GND )
)
( /4C4320F3/4C5D7FB7 0402 L2 FB {Lib=INDUCTOR}
( 1 +3.3V )
( 2 /Ethernet_Phy/ETH_A3.3V )
)
( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R}
( 1 /FPGA_Spartan6/ETH_MDIO )
( 2 +3.3V )
)
( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R}
( 1 N-000394 )
( 2 GND )
)
( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C}
( 1 N-000412 )
( 2 GND )
)
( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R}
( 1 N-000412 )
( 2 GND )
)
( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001}
( 1 /FPGA_Spartan6/ETH_MDIO )
( 2 /FPGA_Spartan6/ETH_MDC )
( 3 /FPGA_Spartan6/ETH_RXD3 )
( 4 /FPGA_Spartan6/ETH_RXD2 )
( 5 /Ethernet_Phy/ETH_RXD1 )
( 6 /Ethernet_Phy/ETH_RXD0 )
( 7 +3.3V )
( 8 GND )
( 9 /FPGA_Spartan6/ETH_RXDV )
( 10 /FPGA_Spartan6/ETH_RXC )
( 11 /FPGA_Spartan6/ETH_RXER )
( 12 GND )
( 13 +1.8V )
( 14 /FPGA_Spartan6/ETH_TXER )
( 15 /Ethernet_Phy/ETH_TXC )
( 16 /Ethernet_Phy/ETH_TXEN )
( 17 /FPGA_Spartan6/ETH_TXD0 )
( 18 /FPGA_Spartan6/ETH_TXD1 )
( 19 /FPGA_Spartan6/ETH_TXD2 )
( 20 /Ethernet_Phy/ETH_TXD3 )
( 21 /FPGA_Spartan6/ETH_COL )
( 22 /FPGA_Spartan6/ETH_CRS )
( 23 GND )
( 24 +3.3V )
( 25 /FPGA_Spartan6/ETH_INT )
( 26 /Ethernet_Phy/ETH_LED0 )
( 27 /Ethernet_Phy/ETH_LED1 )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 /Ethernet_Phy/ETH_A1.8V )
( 32 N-000409 )
( 33 N-000407 )
( 34 ? )
( 35 GND )
( 36 GND )
( 37 N-000394 )
( 38 /Ethernet_Phy/ETH_A3.3V )
( 39 GND )
( 40 N-000408 )
( 41 N-000406 )
( 42 ? )
( 43 ? )
( 44 GND )
( 45 ? )
( 46 /Ethernet_Phy/ETH_CLK )
( 47 /Ethernet_Phy/ETH_PLL1.8V )
( 48 /FPGA_Spartan6/ETH_RESET_N )
)
( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R}
( 1 +3.3V )
( 2 N-000406 )
)
( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R}
( 1 +3.3V )
( 2 N-000408 )
)
( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R}
( 1 +3.3V )
( 2 N-000409 )
)
( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R}
( 1 +3.3V )
( 2 N-000407 )
)
( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R}
( 1 N-000397 )
( 2 /Ethernet_Phy/ETH_LED1 )
)
( /4C4320F3/4C5D719D $noname R7 220 {Lib=R}
( 1 N-000410 )
( 2 /Ethernet_Phy/ETH_LED0 )
)
( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025}
( 1 N-000406 )
( 2 N-000408 )
( 3 +3.3V )
( 4 GND )
( 5 GND )
( 6 +3.3V )
( 7 N-000407 )
( 8 N-000409 )
( 9 +3.3V )
( 10 N-000410 )
( 11 +3.3V )
( 12 N-000397 )
( 13 N-000412 )
( 14 N-000412 )
)
( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /DDR_Banks/M1_DQ0 )
( 3 +2.5V )
( 4 /DDR_Banks/M1_DQ1 )
( 5 /DDR_Banks/M1_DQ2 )
( 6 GND )
( 7 /FPGA_Spartan6/M1_DQ3 )
( 8 /FPGA_Spartan6/M1_DQ4 )
( 9 +2.5V )
( 10 /DDR_Banks/M1_DQ5 )
( 11 /FPGA_Spartan6/M1_DQ6 )
( 12 GND )
( 13 /FPGA_Spartan6/M1_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /DDR_Banks/M1_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /DDR_Banks/M1_LDM )
( 21 /FPGA_Spartan6/M1_WE# )
( 22 /DDR_Banks/M1_CAS# )
( 23 /DDR_Banks/M1_RAS# )
( 24 /FPGA_Spartan6/M1_CS# )
( 25 ? )
( 26 /DDR_Banks/M1_BA0 )
( 27 /FPGA_Spartan6/M1_BA1 )
( 28 /FPGA_Spartan6/M1_A10 )
( 29 /DDR_Banks/M1_A0 )
( 30 /FPGA_Spartan6/M1_A1 )
( 31 /FPGA_Spartan6/M1_A2 )
( 32 /FPGA_Spartan6/M1_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /DDR_Banks/M1_A4 )
( 36 /FPGA_Spartan6/M1_A5 )
( 37 /FPGA_Spartan6/M1_A6 )
( 38 /FPGA_Spartan6/M1_A7 )
( 39 /FPGA_Spartan6/M1_A8 )
( 40 /FPGA_Spartan6/M1_A9 )
( 41 /FPGA_Spartan6/M1_A11 )
( 42 /DDR_Banks/M1_A12 )
( 43 ? )
( 44 /DDR_Banks/M1_CLK# )
( 45 /FPGA_Spartan6/M1_CKE )
( 46 /DDR_Banks/M1_CLK )
( 47 /DDR_Banks/M1_UDM )
( 48 GND )
( 49 N-000058 )
( 50 ? )
( 51 /DDR_Banks/M1_UDQS )
( 52 GND )
( 53 ? )
( 54 /FPGA_Spartan6/M1_DQ8 )
( 55 +2.5V )
( 56 /FPGA_Spartan6/M1_DQ9 )
( 57 /FPGA_Spartan6/M1_DQ10 )
( 58 GND )
( 59 /FPGA_Spartan6/M1_DQ11 )
( 60 /FPGA_Spartan6/M1_DQ12 )
( 61 +2.5V )
( 62 /FPGA_Spartan6/M1_DQ13 )
( 63 /DDR_Banks/M1_DQ14 )
( 64 GND )
( 65 /DDR_Banks/M1_DQ15 )
( 66 GND )
)
( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D151 1206 C33 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R}
( 1 +2.5V )
( 2 N-000058 )
)
( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R}
( 1 N-000058 )
( 2 GND )
)
( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R}
( 1 N-000059 )
( 2 GND )
)
( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R}
( 1 +2.5V )
( 2 N-000059 )
)
( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP}
( 1 +2.5V )
( 2 N-000058 )
)
( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP}
( 1 N-000058 )
( 2 GND )
)
( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP}
( 1 N-000059 )
( 2 GND )
)
( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP}
( 1 +2.5V )
( 2 N-000059 )
)
( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /DDR_Banks/M0_DQ0 )
( 3 +2.5V )
( 4 /FPGA_Spartan6/M0_DQ1 )
( 5 /FPGA_Spartan6/M0_DQ2 )
( 6 GND )
( 7 /FPGA_Spartan6/M0_DQ3 )
( 8 /FPGA_Spartan6/M0_DQ4 )
( 9 +2.5V )
( 10 /FPGA_Spartan6/M0_DQ5 )
( 11 /FPGA_Spartan6/M0_DQ6 )
( 12 GND )
( 13 /DDR_Banks/M0_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /FPGA_Spartan6/M0_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /FPGA_Spartan6/M0_LDM )
( 21 /FPGA_Spartan6/M0_WE# )
( 22 /DDR_Banks/M0_CAS# )
( 23 /FPGA_Spartan6/M0_RAS# )
( 24 GND )
( 25 ? )
( 26 /DDR_Banks/M0_BA0 )
( 27 /FPGA_Spartan6/M0_BA1 )
( 28 /FPGA_Spartan6/M0_A10 )
( 29 /FPGA_Spartan6/M0_A0 )
( 30 /FPGA_Spartan6/M0_A1 )
( 31 /FPGA_Spartan6/M0_A2 )
( 32 /DDR_Banks/M0_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /DDR_Banks/M0_A4 )
( 36 /FPGA_Spartan6/M0_A5 )
( 37 /FPGA_Spartan6/M0_A6 )
( 38 /DDR_Banks/M0_A7 )
( 39 /FPGA_Spartan6/M0_A8 )
( 40 /FPGA_Spartan6/M0_A9 )
( 41 /DDR_Banks/M0_A11 )
( 42 /DDR_Banks/M0_A12 )
( 43 ? )
( 44 /FPGA_Spartan6/M0_CLK# )
( 45 /FPGA_Spartan6/M0_CKE )
( 46 /FPGA_Spartan6/M0_CLK )
( 47 /FPGA_Spartan6/M0_UDM )
( 48 GND )
( 49 N-000059 )
( 50 ? )
( 51 /FPGA_Spartan6/M0_UDQS )
( 52 GND )
( 53 ? )
( 54 /FPGA_Spartan6/M0_DQ8 )
( 55 +2.5V )
( 56 /FPGA_Spartan6/M0_DQ9 )
( 57 /FPGA_Spartan6/M0_DQ10 )
( 58 GND )
( 59 /FPGA_Spartan6/M0_DQ11 )
( 60 /DDR_Banks/M0_DQ12 )
( 61 +2.5V )
( 62 /DDR_Banks/M0_DQ13 )
( 63 /FPGA_Spartan6/M0_DQ14 )
( 64 GND )
( 65 /FPGA_Spartan6/M0_DQ15 )
( 66 GND )
)
)
*
{ Allowed footprints by component:
$component C75
SM*
C?
C1-1
$endlist
$component C74
SM*
C?
C1-1
$endlist
$component C73
SM*
C?
C1-1
$endlist
$component C72
SM*
C?
C1-1
$endlist
$component C35
SM*
C?
C1-1
$endlist
$component C36
SM*
C?
C1-1
$endlist
$component C37
SM*
C?
C1-1
$endlist
$component C38
SM*
C?
C1-1
$endlist
$component R15
R?
SM0603
SM0805
R?-*
$endlist
$component R10
R?
SM0603
SM0805
R?-*
$endlist
$component C16
SM*
C?
C1-1
$endlist
$component C15
SM*
C?
C1-1
$endlist
$component C14
SM*
C?
C1-1
$endlist
$component C13
SM*
C?
C1-1
$endlist
$component R19
R?
SM0603
SM0805
R?-*
$endlist
$component R20
R?
SM0603
SM0805
R?-*
$endlist
$component R17
R?
SM0603
SM0805
R?-*
$endlist
$component R18
R?
SM0603
SM0805
R?-*
$endlist
$component R16
R?
SM0603
SM0805
R?-*
$endlist
$component C66
SM*
C?
C1-1
$endlist
$component C63
SM*
C?
C1-1
$endlist
$component C60
SM*
C?
C1-1
$endlist
$component C57
SM*
C?
C1-1
$endlist
$component C54
SM*
C?
C1-1
$endlist
$component C69
SM*
C?
C1-1
$endlist
$component C67
SM*
C?
C1-1
$endlist
$component C64
SM*
C?
C1-1
$endlist
$component C61
SM*
C?
C1-1
$endlist
$component C58
SM*
C?
C1-1
$endlist
$component C55
SM*
C?
C1-1
$endlist
$component C68
SM*
C?
C1-1
$endlist
$component C65
SM*
C?
C1-1
$endlist
$component C62
SM*
C?
C1-1
$endlist
$component C59
SM*
C?
C1-1
$endlist
$component C56
SM*
C?
C1-1
$endlist
$component C50
SM*
C?
C1-1
$endlist
$component C47
SM*
C?
C1-1
$endlist
$component C44
SM*
C?
C1-1
$endlist
$component C41
SM*
C?
C1-1
$endlist
$component C53
SM*
C?
C1-1
$endlist
$component C51
SM*
C?
C1-1
$endlist
$component C49
SM*
C?
C1-1
$endlist
$component C46
SM*
C?
C1-1
$endlist
$component C52
SM*
C?
C1-1
$endlist
$component C43
SM*
C?
C1-1
$endlist
$component C40
SM*
C?
C1-1
$endlist
$component C48
SM*
C?
C1-1
$endlist
$component C45
SM*
C?
C1-1
$endlist
$component C42
SM*
C?
C1-1
$endlist
$component C39
SM*
C?
C1-1
$endlist
$component C9
SM*
C?
C1-1
$endlist
$component C6
SM*
C?
C1-1
$endlist
$component C4
SM*
C?
C1-1
$endlist
$component C2
SM*
C?
C1-1
$endlist
$component C8
SM*
C?
C1-1
$endlist
$component C7
SM*
C?
C1-1
$endlist
$component C5
SM*
C?
C1-1
$endlist
$component C3
SM*
C?
C1-1
$endlist
$component C1
SM*
C?
C1-1
$endlist
$component R1
R?
SM0603
SM0805
R?-*
$endlist
$component R2
R?
SM0603
SM0805
R?-*
$endlist
$component C11
SM*
C?
C1-1
$endlist
$component C10
SM*
C?
C1-1
$endlist
$component C12
SM*
C?
C1-1
$endlist
$component R9
R?
SM0603
SM0805
R?-*
$endlist
$component R3
R?
SM0603
SM0805
R?-*
$endlist
$component R4
R?
SM0603
SM0805
R?-*
$endlist
$component R6
R?
SM0603
SM0805
R?-*
$endlist
$component R5
R?
SM0603
SM0805
R?-*
$endlist
$component R8
R?
SM0603
SM0805
R?-*
$endlist
$component R7
R?
SM0603
SM0805
R?-*
$endlist
$component C70
SM*
C?
C1-1
$endlist
$component C71
SM*
C?
C1-1
$endlist
$component C34
SM*
C?
C1-1
$endlist
$component C33
SM*
C?
C1-1
$endlist
$component C28
SM*
C?
C1-1
$endlist
$component C29
SM*
C?
C1-1
$endlist
$component C31
SM*
C?
C1-1
$endlist
$component C30
SM*
C?
C1-1
$endlist
$component C32
SM*
C?
C1-1
$endlist
$component C27
SM*
C?
C1-1
$endlist
$component C21
SM*
C?
C1-1
$endlist
$component C26
SM*
C?
C1-1
$endlist
$component C24
SM*
C?
C1-1
$endlist
$component C25
SM*
C?
C1-1
$endlist
$component C23
SM*
C?
C1-1
$endlist
$component C22
SM*
C?
C1-1
$endlist
$component R13
R?
SM0603
SM0805
R?-*
$endlist
$component R14
R?
SM0603
SM0805
R?-*
$endlist
$component R12
R?
SM0603
SM0805
R?-*
$endlist
$component R11
R?
SM0603
SM0805
R?-*
$endlist
$component C19
SM*
C?
C1-1
$endlist
$component C20
SM*
C?
C1-1
$endlist
$component C18
SM*
C?
C1-1
$endlist
$component C17
SM*
C?
C1-1
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO"
U8 1
U1 T5
Net 2 "/FPGA Spartan6/NF_RE_N" "NF_RE_N"
U5 8
U1 B16
Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N"
U5 9
U1 C16
Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE"
U1 A15
U5 17
Net 5 "/Ethernet Phy/ETH_TXC" "ETH_TXC"
U1 D7
U4 15
Net 6 "/FPGA Spartan6/ETH_RXC" "ETH_RXC"
U1 D8
U4 10
Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK"
U1 A4
U4 46
Net 8 "/FPGA Spartan6/USBA_SPD" "USBA_SPD"
U1 R19
U6 2
Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N"
U6 9
U1 P18
Net 10 "/USB/USBA_RCV" "USBA_RCV"
U6 3
U1 N16
Net 11 "/FPGA Spartan6/USBA_VP" "USBA_VP"
U1 P17
U6 4
Net 12 "/USB/USBA_VM" "USBA_VM"
U1 M18
U6 5
Net 13 "/FPGA Spartan6/ETH_COL" "ETH_COL"
U4 21
U1 B10
Net 14 "/FPGA Spartan6/ETH_CRS" "ETH_CRS"
U1 C10
U4 22
Net 15 "/Non volatile memories/SD_CLK" "SD_CLK"
U1 E16
J1 5
Net 16 "/FPGA Spartan6/ETH_INT" "ETH_INT"
U4 25
U1 A10
Net 17 "/FPGA Spartan6/ETH_MDC" "ETH_MDC"
U1 D10
U4 2
Net 18 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO"
U4 1
R1 1
U1 C5
Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N"
U4 48
U1 A5
Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV"
U4 9
U1 C7
Net 21 "/FPGA Spartan6/ETH_RXER" "ETH_RXER"
U1 A7
U4 11
Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER"
U1 B8
U4 14
Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN"
U1 A8
U4 16
Net 24 "/FPGA Spartan6/M1_CS#" "M1_CS#"
U3 24
R20 2
Net 25 "/DDR Banks/M1_UDM" "M1_UDM"
U3 47
R18 2
Net 26 "/DDR Banks/M1_LDQS" "M1_LDQS"
RP3 8
U3 16
Net 27 "/DDR Banks/M1_LDM" "M1_LDM"
RP3 7
U3 20
Net 28 "/DDR Banks/M1_UDQS" "M1_UDQS"
R19 2
U3 51
Net 29 "/FPGA Spartan6/M0_UDQS" "M0_UDQS"
U1 T2
U2 51
Net 30 "/FPGA Spartan6/M0_LDM" "M0_LDM"
U1 L4
RP16 7
U2 20
Net 31 "/DDR Banks/M1_CAS#" "M1_CAS#"
U3 22
RP3 5
Net 32 "/FPGA Spartan6/M1_CKE" "M1_CKE"
U3 45
R17 2
Net 33 "/DDR Banks/M1_CLK" "M1_CLK"
U1 H20
U3 46
R16 2
Net 34 "/DDR Banks/M1_CLK#" "M1_CLK#"
U3 44
U1 J19
R16 1
Net 35 "GND" "GND"
C32 2
U2 48
C27 2
U2 58
C23 2
C22 2
C33 2
C28 2
C29 2
C31 2
C30 2
U1 L13
U5 13
U1 N13
U1 K14
U1 M14
U1 P14
U1 V14
U1 E15
U1 J15
U1 AA5
U1 N2
U1 U2
U1 D4
U1 V4
U1 B5
U1 G5
U1 L5
U1 R5
U1 E7
U1 H7
U5 36
U1 U7
U1 P10
U1 V10
U1 E11
U1 J11
U1 L11
U1 N11
U1 W16
U1 B17
U1 N17
U1 D18
U1 G18
U1 L18
U1 R18
U1 W19
U1 AA9
U1 AB22
U1 AA13
U1 AA17
U1 W7
U1 B9
U1 J9
U1 J2
U1 E2
U1 A1
C75 1
C74 2
U8 4
C73 2
C72 2
C34 2
C71 2
C70 2
C25 2
C24 2
C26 2
C21 2
J1 CASE
J1 CASE
J1 CASE
J1 COM
J1 6
U1 E21
U1 J21
U1 N21
U1 U21
U1 AB1
U1 K12
U1 M12
U1 P12
U1 A22
U1 B13
U1 J13
U1 L9
U1 N9
U1 K10
U1 M10
U2 34
U2 24
U2 52
U2 12
U2 66
U2 64
C18 2
C20 2
R12 2
R14 2
U2 6
C48 2
C45 2
C42 2
C39 2
J4 4
U4 39
R2 2
C11 2
C10 2
C12 2
R9 2
C4 2
C2 2
C8 2
C7 2
C5 2
C3 2
C1 2
J4 5
C9 2
C6 2
U3 64
U4 23
U4 36
U4 35
U4 44
U4 8
U4 12
V1 2
C16 2
R10 2
U9 PAD
U9 8
L7 2
R15 2
C38 2
V3 2
V4 2
C37 2
C36 2
C35 2
L5 2
U6 8
U6 7
C13 2
C14 2
C15 2
V2 2
U7 8
U7 7
C58 2
C61 2
C64 2
C56 2
C59 2
C62 2
U3 6
C40 2
C43 2
C52 2
C46 2
C49 2
C51 2
C53 2
C67 2
C69 2
C54 2
C57 2
U3 34
U3 52
U3 58
U3 48
U3 66
U3 12
C41 2
C44 2
C47 2
C50 2
C55 2
C60 2
C68 2
C63 2
C66 2
C65 2
Net 36 "/FPGA Spartan6/M0_CLK#" "M0_CLK#"
U2 44
U1 H3
Net 37 "/FPGA Spartan6/M0_CLK" "M0_CLK"
U2 46
U1 H4
Net 38 "/FPGA Spartan6/M0_CKE" "M0_CKE"
U2 45
U1 D2
Net 39 "/DDR Banks/M0_CAS#" "M0_CAS#"
RP16 5
U2 22
U1 K4
Net 40 "/FPGA Spartan6/M1_WE#" "M1_WE#"
U3 21
RP3 6
Net 41 "/DDR Banks/M1_RAS#" "M1_RAS#"
RP2 8
U3 23
Net 42 "/FPGA Spartan6/M0_RAS#" "M0_RAS#"
U1 K5
U2 23
RP15 8
Net 43 "/FPGA Spartan6/M0_WE#" "M0_WE#"
U1 F2
RP16 6
U2 21
Net 44 "/FPGA Spartan6/M0_LDQS" "M0_LDQS"
RP16 8
U2 16
U1 L3
Net 45 "/FPGA Spartan6/M0_UDM" "M0_UDM"
U1 M3
U2 47
Net 46 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK"
U8 6
U1 AA21
Net 47 "/FPGA Spartan6/NF_RNB" "NF_RNB"
U1 A16
U5 6
U5 7
Net 48 "/FPGA Spartan6/NF_WE_N" "NF_WE_N"
U5 18
U1 C15
Net 49 "/Non volatile memories/NF_CLE" "NF_CLE"
U1 D15
U5 16
Net 50 "/Non volatile memories/SD_CMD" "SD_CMD"
U1 D17
J1 3
Net 56 "+2.5V" "+2.5V"
C21 1
C33 1
C22 1
C23 1
C25 1
C24 1
C26 1
C28 1
C29 1
C31 1
C30 1
C32 1
C27 1
U2 9
R13 1
U1 E19
U1 U18
U1 N18
U1 J18
R11 1
C19 1
C17 1
U1 W21
U1 R21
U1 L21
U1 G21
U7 1
U2 1
U2 3
C37 1
C70 1
C71 1
C34 1
U1 C21
U1 L16
U2 15
U2 55
U2 18
U2 61
U2 33
U1 F6
U1 U5
U1 N5
U1 J5
U1 F4
U1 L7
U1 L2
U1 G2
U1 C2
U1 W2
U1 R2
U3 55
U3 18
C59 1
C57 1
U3 9
C54 1
C51 1
C49 1
C46 1
C52 1
U3 3
C43 1
C40 1
U3 1
C53 1
U3 61
C68 1
C65 1
C62 1
C66 1
C63 1
C56 1
C60 1
U3 15
U3 33
U1 L8
U1 G12
U1 F11
C15 1
U1 N8
U1 D16
U1 H9
U6 1
U1 R10
U1 H15
U1 U11
U1 V6
U1 M15
U1 R6
U1 R12
U1 K15
Net 58 "" ""
U3 49
R14 1
R13 2
C19 2
C20 1
Net 59 "" ""
U2 49
C17 2
R12 1
R11 2
C18 1
Net 98 "+3.3V" "+3.3V"
R3 1
U1 E13
R4 1
U1 G14
U1 B15
R6 1
R5 1
C5 1
C3 1
C1 1
C10 1
U1 B19
U1 E17
C11 1
L2 1
U1 E9
R1 2
U1 B7
U1 G10
U1 B11
U1 B4
U4 24
U4 7
U5 12
C36 1
C35 1
J1 4
C74 1
C75 2
C50 1
C47 1
C44 1
C41 1
U7 14
U7 12
C72 1
C73 1
C14 1
C13 1
U6 12
U6 14
J4 11
J4 9
J4 6
J4 3
U5 19
U5 37
Net 99 "VCCO2" "VCCO2"
U1 AA15
U1 AA11
U8 8
U1 T9
U1 V8
U1 AA3
U1 T13
C64 1
C61 1
C58 1
U1 V12
U1 AA19
U1 V16
U1 AA7
C67 1
C55 1
C69 1
U1 W5
Net 105 "/FPGA Spartan6/R_M0_A4" "R_M0_A4"
RP17 4
U1 F3
Net 106 "/FPGA Spartan6/R_M0_A3" "R_M0_A3"
U1 K6
RP14 4
Net 142 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0"
RP2 2
U1 J17
Net 143 "+1.2V" "+1.2V"
U1 P9
U1 N12
U1 N10
U1 J12
U1 K9
U1 L12
U1 P11
U1 J8
U1 R14
U1 M13
C39 1
U1 J10
U1 P13
U1 K11
U1 N14
U1 J14
U1 L14
U1 L10
U1 M11
C48 1
U1 M9
U1 K13
C45 1
C42 1
Net 144 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6"
RP12 3
U1 K2
Net 145 "/FPGA Spartan6/R_M0_A9" "R_M0_A9"
RP18 3
U1 E1
Net 146 "/FPGA Spartan6/R_M0_A11" "R_M0_A11"
U1 C1
RP18 2
Net 147 "/FPGA Spartan6/R_M0_A1" "R_M0_A1"
U1 H1
RP14 2
Net 148 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1"
RP15 3
U1 G1
Net 149 "/FPGA Spartan6/R_M0_A2" "R_M0_A2"
U1 H5
RP14 3
Net 150 "/FPGA Spartan6/R_M0_A5" "R_M0_A5"
RP17 3
U1 K3
Net 151 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14"
RP10 3
U1 V2
Net 152 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12"
U1 U3
RP10 1
Net 153 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9"
U1 P1
RP11 2
Net 154 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10"
U1 R3
RP11 3
Net 155 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0"
U1 N3
RP13 1
Net 156 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2"
U1 M2
RP13 3
Net 157 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4"
U1 J3
RP12 1
Net 158 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5"
RP12 2
U1 J1
Net 159 "/FPGA Spartan6/R_M1_A6" "R_M1_A6"
U1 K19
RP6 2
Net 160 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#"
U1 H19
RP3 3
Net 161 "/FPGA Spartan6/R_M1_A10" "R_M1_A10"
U1 G19
RP2 4
Net 162 "/FPGA Spartan6/R_M1_A11" "R_M1_A11"
RP7 2
U1 F19
Net 179 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14"
U1 V21
RP8 2
Net 180 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8"
U1 P21
RP9 4
Net 181 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2"
RP5 3
U1 M21
Net 182 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6"
RP4 3
U1 K21
Net 183 "/FPGA Spartan6/R_M1_A0" "R_M1_A0"
U1 F21
RP1 1
Net 184 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE"
U1 D21
R17 1
Net 189 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12"
RP8 4
U1 U20
Net 191 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10"
RP9 2
U1 R20
Net 193 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0"
U1 N20
RP5 1
Net 194 "/FPGA Spartan6/R_M1_A5" "R_M1_A5"
RP6 3
U1 K20
Net 195 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4"
RP4 1
U1 J20
Net 203 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15"
RP8 1
U1 V22
Net 204 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13"
RP8 3
U1 U22
Net 206 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11"
U1 R22
RP9 1
Net 207 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9"
RP9 3
U1 P22
Net 208 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1"
U1 N22
RP5 2
Net 209 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3"
RP5 4
U1 M22
Net 211 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7"
RP4 4
U1 K22
Net 212 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5"
U1 J22
RP4 2
Net 214 "/FPGA Spartan6/R_M1_A1" "R_M1_A1"
RP1 2
U1 F22
Net 215 "/FPGA Spartan6/R_M1_A2" "R_M1_A2"
U1 E22
RP1 3
Net 216 "/FPGA Spartan6/R_M1_A12" "R_M1_A12"
RP7 1
U1 D22
Net 217 "/FPGA Spartan6/R_M1_A9" "R_M1_A9"
RP7 3
U1 C22
Net 317 "/FPGA Spartan6/R_M0_A7" "R_M0_A7"
U1 H6
RP17 1
Net 331 "/FPGA Spartan6/R_M0_A6" "R_M0_A6"
U1 J4
RP17 2
Net 332 "/FPGA Spartan6/R_M0_A10" "R_M0_A10"
RP15 4
U1 G4
Net 333 "/FPGA Spartan6/R_M1_A3" "R_M1_A3"
U1 G20
RP1 4
Net 335 "/FPGA Spartan6/R_M1_A7" "R_M1_A7"
RP6 1
U1 E20
Net 337 "/FPGA Spartan6/R_M1_A8" "R_M1_A8"
RP7 4
U1 C20
Net 356 "/FPGA Spartan6/R_M0_A0" "R_M0_A0"
U1 H2
RP14 1
Net 361 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15"
RP10 4
U1 V1
Net 362 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13"
RP10 2
U1 U1
Net 364 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11"
U1 R1
RP11 4
Net 365 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1"
U1 N1
RP13 2
Net 366 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3"
RP13 4
U1 M1
Net 368 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7"
RP12 4
U1 K1
Net 370 "/FPGA Spartan6/R_M0_A12" "R_M0_A12"
RP18 1
U1 D1
Net 377 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0"
U1 G3
RP15 2
Net 378 "/FPGA Spartan6/R_M0_A8" "R_M0_A8"
RP18 4
U1 E3
Net 383 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8"
RP11 1
U1 P2
Net 384 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS"
U1 L20
RP3 1
Net 385 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM"
RP3 2
U1 L19
Net 386 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#"
R20 1
U1 H16
Net 387 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS"
U1 T21
R19 1
Net 388 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM"
R18 1
U1 M20
Net 389 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#"
RP2 1
U1 H21
Net 390 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1"
U1 K17
RP2 3
Net 391 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#"
U1 H22
RP3 4
Net 392 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
C9 1
U4 47
L3 2
Net 393 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
U4 38
L2 2
C7 1
C8 1
Net 394 "" ""
R2 1
U4 37
Net 397 "" ""
J4 12
R8 1
Net 398 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
U4 27
R8 2
Net 401 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
R7 2
U4 26
Net 403 "+1.8V" "+1.8V"
C4 1
U4 13
L1 1
C2 1
Net 406 "" ""
U4 41
J4 1
R3 2
Net 407 "" ""
R5 2
J4 7
U4 33
Net 408 "" ""
R4 2
J4 2
U4 40
Net 409 "" ""
R6 2
U4 32
J4 8
Net 410 "" ""
J4 10
R7 1
Net 411 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
C6 1
L3 1
L1 2
U4 31
Net 412 "" ""
C12 1
R9 1
J4 14
J4 13
Net 419 "" ""
V2 1
V2 1
J5 2
U6 10
Net 420 "" ""
J5 4
L5 1
Net 421 "" ""
C16 1
J5 S4
J5 S3
R10 1
J5 S1
J5 S2
Net 422 "" ""
F2 1
L6 1
Net 424 "+5V" "+5V"
F1 2
F2 2
Net 425 "" ""
F1 1
L4 1
Net 426 "" ""
L4 2
J5 1
Net 427 "" ""
U6 11
V1 1
J5 3
V1 1
Net 428 "" ""
V4 1
V4 1
U7 10
Net 429 "" ""
V3 1
U7 11
V3 1
Net 430 "" ""
C38 1
R15 1
Net 450 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3"
U1 U13
U8 7
Net 451 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2"
U1 U14
U8 3
Net 452 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1"
U1 AA20
U8 2
Net 453 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0"
U1 AB20
U8 5
Net 454 "/Non volatile memories/NF_D7" "NF_D7"
U1 A11
U5 44
Net 455 "/FPGA Spartan6/NF_D6" "NF_D6"
U5 43
U1 D11
Net 456 "/Non volatile memories/NF_D5" "NF_D5"
U5 42
U1 C12
Net 457 "/FPGA Spartan6/NF_D4" "NF_D4"
U1 B12
U5 41
Net 458 "/Non volatile memories/NF_D3" "NF_D3"
U5 32
U1 A12
Net 459 "/Non volatile memories/NF_D2" "NF_D2"
U1 C13
U5 31
Net 460 "/Non volatile memories/NF_D1" "NF_D1"
U1 A13
U5 30
Net 461 "/FPGA Spartan6/NF_D0" "NF_D0"
U1 D14
U5 29
Net 462 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3"
U1 A9
U4 20
Net 463 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2"
U4 19
U1 C9
Net 464 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1"
U1 C8
U4 18
Net 465 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0"
U4 17
U1 D9
Net 466 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3"
U4 3
U1 D6
Net 467 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2"
U1 C6
U4 4
Net 468 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1"
U1 B6
U4 5
Net 469 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0"
U4 6
U1 A6
Net 470 "/FPGA Spartan6/M0_BA1" "M0_BA1"
RP15 6
U2 27
Net 471 "/DDR Banks/M0_BA0" "M0_BA0"
U2 26
RP15 7
Net 472 "/FPGA Spartan6/M1_BA1" "M1_BA1"
RP2 6
U3 27
Net 473 "/DDR Banks/M1_BA0" "M1_BA0"
RP2 7
U3 26
Net 474 "/DDR Banks/M1_DQ15" "M1_DQ15"
RP8 8
U3 65
Net 475 "/DDR Banks/M1_DQ14" "M1_DQ14"
U3 63
RP8 7
Net 476 "/FPGA Spartan6/M1_DQ13" "M1_DQ13"
U3 62
RP8 6
Net 477 "/FPGA Spartan6/M1_DQ12" "M1_DQ12"
U3 60
RP8 5
Net 478 "/FPGA Spartan6/M1_DQ11" "M1_DQ11"
RP9 8
U3 59
Net 479 "/FPGA Spartan6/M1_DQ10" "M1_DQ10"
U3 57
RP9 7
Net 480 "/FPGA Spartan6/SD_DAT3" "SD_DAT3"
U1 C17
J1 2
Net 481 "/Non volatile memories/SD_DAT2" "SD_DAT2"
U1 A17
J1 1
Net 482 "/Non volatile memories/SD_DAT1" "SD_DAT1"
J1 8
U1 B18
Net 483 "/FPGA Spartan6/SD_DAT0" "SD_DAT0"
U1 A18
J1 7
Net 484 "/FPGA Spartan6/M1_A7" "M1_A7"
RP6 8
U3 38
Net 485 "/FPGA Spartan6/M1_A6" "M1_A6"
RP6 7
U3 37
Net 486 "/FPGA Spartan6/M1_A5" "M1_A5"
U3 36
RP6 6
Net 487 "/DDR Banks/M1_A4" "M1_A4"
U3 35
RP6 5
Net 488 "/FPGA Spartan6/M1_A3" "M1_A3"
RP1 5
U3 32
Net 489 "/FPGA Spartan6/M1_A2" "M1_A2"
RP1 6
U3 31
Net 490 "/FPGA Spartan6/M1_A1" "M1_A1"
RP1 7
U3 30
Net 491 "/DDR Banks/M1_A0" "M1_A0"
U3 29
RP1 8
Net 492 "/DDR Banks/M0_A12" "M0_A12"
U2 42
RP18 8
Net 493 "/DDR Banks/M0_A11" "M0_A11"
RP18 7
U2 41
Net 494 "/FPGA Spartan6/M0_A10" "M0_A10"
U2 28
RP15 5
Net 495 "/FPGA Spartan6/M0_A9" "M0_A9"
RP18 6
U2 40
Net 496 "/FPGA Spartan6/M0_A8" "M0_A8"
U2 39
RP18 5
Net 497 "/DDR Banks/M0_A7" "M0_A7"
RP17 8
U2 38
Net 498 "/FPGA Spartan6/M1_DQ9" "M1_DQ9"
U3 56
RP9 6
Net 499 "/FPGA Spartan6/M1_DQ8" "M1_DQ8"
RP9 5
U3 54
Net 500 "/FPGA Spartan6/M1_DQ7" "M1_DQ7"
RP4 5
U3 13
Net 501 "/FPGA Spartan6/M1_DQ6" "M1_DQ6"
RP4 6
U3 11
Net 502 "/DDR Banks/M1_DQ5" "M1_DQ5"
U3 10
RP4 7
Net 503 "/FPGA Spartan6/M1_DQ4" "M1_DQ4"
RP4 8
U3 8
Net 504 "/FPGA Spartan6/M1_DQ3" "M1_DQ3"
U3 7
RP5 5
Net 505 "/DDR Banks/M1_DQ2" "M1_DQ2"
U3 5
RP5 6
Net 506 "/DDR Banks/M1_DQ1" "M1_DQ1"
U3 4
RP5 7
Net 507 "/DDR Banks/M1_DQ0" "M1_DQ0"
U3 2
RP5 8
Net 508 "/DDR Banks/M1_A12" "M1_A12"
U3 42
RP7 8
Net 509 "/FPGA Spartan6/M1_A11" "M1_A11"
U3 41
RP7 7
Net 510 "/FPGA Spartan6/M1_A10" "M1_A10"
RP2 5
U3 28
Net 511 "/FPGA Spartan6/M1_A9" "M1_A9"
RP7 6
U3 40
Net 512 "/FPGA Spartan6/M1_A8" "M1_A8"
RP7 5
U3 39
Net 513 "/FPGA Spartan6/M0_DQ3" "M0_DQ3"
RP13 5
U2 7
Net 514 "/FPGA Spartan6/M0_DQ2" "M0_DQ2"
RP13 6
U2 5
Net 515 "/FPGA Spartan6/M0_DQ1" "M0_DQ1"
RP13 7
U2 4
Net 516 "/DDR Banks/M0_DQ0" "M0_DQ0"
RP13 8
U2 2
Net 517 "/FPGA Spartan6/M0_A6" "M0_A6"
U2 37
RP17 7
Net 518 "/FPGA Spartan6/M0_A5" "M0_A5"
U2 36
RP17 6
Net 519 "/DDR Banks/M0_A4" "M0_A4"
RP17 5
U2 35
Net 520 "/DDR Banks/M0_A3" "M0_A3"
RP14 5
U2 32
Net 521 "/FPGA Spartan6/M0_A2" "M0_A2"
U2 31
RP14 6
Net 522 "/FPGA Spartan6/M0_A1" "M0_A1"
RP14 7
U2 30
Net 523 "/FPGA Spartan6/M0_A0" "M0_A0"
U2 29
RP14 8
Net 524 "/FPGA Spartan6/M0_DQ15" "M0_DQ15"
U2 65
RP10 5
Net 525 "/FPGA Spartan6/M0_DQ14" "M0_DQ14"
RP10 6
U2 63
Net 526 "/DDR Banks/M0_DQ13" "M0_DQ13"
U2 62
RP10 7
Net 527 "/DDR Banks/M0_DQ12" "M0_DQ12"
RP10 8
U2 60
Net 528 "/FPGA Spartan6/M0_DQ11" "M0_DQ11"
RP11 5
U2 59
Net 529 "/FPGA Spartan6/M0_DQ10" "M0_DQ10"
U2 57
RP11 6
Net 530 "/FPGA Spartan6/M0_DQ9" "M0_DQ9"
RP11 7
U2 56
Net 531 "/FPGA Spartan6/M0_DQ8" "M0_DQ8"
U2 54
RP11 8
Net 532 "/DDR Banks/M0_DQ7" "M0_DQ7"
U2 13
RP12 5
Net 533 "/FPGA Spartan6/M0_DQ6" "M0_DQ6"
RP12 6
U2 11
Net 534 "/FPGA Spartan6/M0_DQ5" "M0_DQ5"
U2 10
RP12 7
Net 535 "/FPGA Spartan6/M0_DQ4" "M0_DQ4"
RP12 8
U2 8
}
#End
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