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95 lines
3.1 KiB
Verilog
95 lines
3.1 KiB
Verilog
/****************************************************************************************
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*
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* File Name: ddr2_mcp.v
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*
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* Dependencies: ddr2.v, ddr2_parameters.vh
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*
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* Description: Micron SDRAM DDR2 (Double Data Rate 2) multi-chip package model
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
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`timescale 1ps / 1ps
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module ddr2_mcp (
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ck,
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ck_n,
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cke,
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cs_n,
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ras_n,
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cas_n,
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we_n,
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dm_rdqs,
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ba,
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addr,
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dq,
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dqs,
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dqs_n,
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rdqs_n,
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odt
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);
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`include "ddr2_parameters.vh"
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// Declare Ports
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input ck;
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input ck_n;
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input [CS_BITS-1:0] cke;
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input [CS_BITS-1:0] cs_n;
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input ras_n;
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input cas_n;
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input we_n;
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inout [DM_BITS-1:0] dm_rdqs;
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input [BA_BITS-1:0] ba;
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input [ADDR_BITS-1:0] addr;
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inout [DQ_BITS-1:0] dq;
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inout [DQS_BITS-1:0] dqs;
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inout [DQS_BITS-1:0] dqs_n;
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output [DQS_BITS-1:0] rdqs_n;
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input [CS_BITS-1:0] odt;
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wire [RANKS-1:0] cke_mcp = cke;
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wire [RANKS-1:0] cs_n_mcp = cs_n;
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wire [RANKS-1:0] odt_mcp = odt;
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ddr2 rank [RANKS-1:0] (
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ck,
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ck_n,
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cke_mcp,
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cs_n_mcp,
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ras_n,
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cas_n,
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we_n,
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dm_rdqs,
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ba,
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addr,
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dq,
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dqs,
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dqs_n,
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rdqs_n,
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odt_mcp
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);
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endmodule
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