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Code
ba734f70bf
xue/kicad/xue-rnc/xue-rnc.net
Andres Calderon ba734f70bf terminal resistors placement
2010-08-16 19:06:33 -05:00

2614 lines
41 KiB
Plaintext
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# EESchema Netlist Version 1.1 created Mon 16 Aug 2010 07:01:48 PM COT
(
( /4C4227FE/4C6969AB $noname C75 100nF {Lib=C}
( 1 GND )
( 2 +3.3V )
)
( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D67C 0402 C73 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D661 0402 C72 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB}
( 1 /FPGA_Spartan6/PROG_CSO )
( 2 /FPGA_Spartan6/PROG_MISO1 )
( 3 /FPGA_Spartan6/PROG_MISO2 )
( 4 GND )
( 5 /FPGA_Spartan6/PROG_MISO0 )
( 6 /FPGA_Spartan6/PROG_CCLK )
( 7 /FPGA_Spartan6/PROG_MISO3 )
( 8 VCCO2 )
)
( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD}
( CASE GND )
( COM GND )
( CD ? )
( 1 /Non_volatile_memories/SD_DAT2 )
( 2 /FPGA_Spartan6/SD_DAT3 )
( 3 /FPGA_Spartan6/SD_CMD )
( 4 +3.3V )
( 5 /Non_volatile_memories/SD_CLK )
( 6 GND )
( 7 /Non_volatile_memories/SD_DAT0 )
( 8 /FPGA_Spartan6/SD_DAT1 )
)
( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M}
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 /FPGA_Spartan6/NF_RNB )
( 7 /FPGA_Spartan6/NF_RNB )
( 8 /Non_volatile_memories/NF_RE_N )
( 9 /Non_volatile_memories/NF_CS1_N )
( 10 ? )
( 11 ? )
( 12 +3.3V )
( 13 GND )
( 14 ? )
( 15 ? )
( 16 /FPGA_Spartan6/NF_CLE )
( 17 /FPGA_Spartan6/NF_ALE )
( 18 /FPGA_Spartan6/NF_WE_N )
( 19 +3.3V )
( 20 ? )
( 21 ? )
( 22 ? )
( 23 ? )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 ? )
( 29 /Non_volatile_memories/NF_D0 )
( 30 /FPGA_Spartan6/NF_D1 )
( 31 /Non_volatile_memories/NF_D2 )
( 32 /Non_volatile_memories/NF_D3 )
( 33 ? )
( 34 ? )
( 35 ? )
( 36 GND )
( 37 +3.3V )
( 38 ? )
( 39 ? )
( 40 ? )
( 41 /Non_volatile_memories/NF_D4 )
( 42 /FPGA_Spartan6/NF_D5 )
( 43 /Non_volatile_memories/NF_D6 )
( 44 /FPGA_Spartan6/NF_D7 )
( 45 ? )
( 46 ? )
( 47 ? )
( 48 ? )
)
( /4C5F1EDC/4C6552BF $noname U7 MIC2550AYTS {Lib=MIC2550AYTS}
( 1 +2.5V )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 7 GND )
( 8 GND )
( 9 ? )
( 10 N-000356 )
( 11 N-000351 )
( 12 +3.3V )
( 14 +3.3V )
)
( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BD $noname C36 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BC $noname C37 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F}
( 1 N-000357 )
( 2 +5V )
)
( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000356 )
( 2 GND )
)
( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000351 )
( 2 GND )
)
( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C}
( 1 N-000359 )
( 2 GND )
)
( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R}
( 1 N-000359 )
( 2 GND )
)
( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR}
( 1 ? )
( 2 GND )
)
( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR}
( 1 N-000357 )
( 2 ? )
)
( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR}
( 1 N-000361 )
( 2 N-000346 )
)
( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR}
( 1 N-000349 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R}
( 1 N-000347 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C}
( 1 N-000347 )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000344 )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000348 )
( 2 GND )
)
( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F}
( 1 N-000361 )
( 2 +5V )
)
( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001}
( S1 N-000347 )
( S2 N-000347 )
( S3 N-000347 )
( S4 N-000347 )
( 1 N-000346 )
( 2 N-000348 )
( 3 N-000344 )
( 4 N-000349 )
)
( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS}
( 1 +2.5V )
( 2 /USB/USBA_SPD )
( 3 /USB/USBA_RCV )
( 4 /FPGA_Spartan6/USBA_VP )
( 5 /USB/USBA_VM )
( 7 GND )
( 8 GND )
( 9 /FPGA_Spartan6/USBA_OE_N )
( 10 N-000348 )
( 11 N-000344 )
( 12 +3.3V )
( 14 +3.3V )
)
( /4C431A63/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_CAS# )
( 2 /FPGA_Spartan6/R_M1_RAS# )
( 3 /FPGA_Spartan6/R_M1_BA0 )
( 4 /FPGA_Spartan6/R_M1_BA1 )
( 5 /DDR_Banks/M1_BA1 )
( 6 /DDR_Banks/M1_BA0 )
( 7 /FPGA_Spartan6/M1_RAS# )
( 8 /DDR_Banks/M1_CAS# )
)
( /4C431A63/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Spartan6/R_M1_A0 )
( 2 /FPGA_Spartan6/R_M1_A1 )
( 3 /FPGA_Spartan6/R_M1_A2 )
( 4 /FPGA_Spartan6/R_M1_A3 )
( 5 /FPGA_Spartan6/M1_A3 )
( 6 /DDR_Banks/M1_A2 )
( 7 /DDR_Banks/M1_A1 )
( 8 /FPGA_Spartan6/M1_A0 )
)
( /4C431A63/4C656D9D $noname C66 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D9A $noname C63 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D99 $noname C60 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D98 $noname C57 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D97 $noname C54 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656D53 $noname C69 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D49 $noname C67 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D46 $noname C64 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D45 $noname C61 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D44 $noname C58 4.7uF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D43 $noname C55 100uF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C431A63/4C656D08 $noname C68 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CFC $noname C65 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CFB $noname C62 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CFA $noname C59 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CF9 $noname C56 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656CBB $noname C50 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656CBA $noname C47 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656CB9 $noname C44 4.7uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656CB7 $noname C41 100uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C431A63/4C656C49 $noname C53 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656C27 $noname C51 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656C24 $noname C49 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656C16 $noname C46 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656BFA $noname C52 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656BF9 $noname C43 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656BF8 $noname C40 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C431A63/4C656AC2 $noname C48 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656AC0 $noname C45 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656ABD $noname C42 4.7uF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C656A80 $noname C39 100uF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
( H8 ? )
( P7 ? )
( N7 ? )
( M7 ? )
( L7 +2.5V )
( K7 ? )
( J7 ? )
( G7 ? )
( F7 ? )
( P6 ? )
( N6 ? )
( M6 ? )
( L6 ? )
( K6 /FPGA_Spartan6/M0_A3 )
( J6 ? )
( H6 /FPGA_Spartan6/M0_A7 )
( G6 ? )
( F6 +2.5V )
( E6 ? )
( U5 +2.5V )
( P5 ? )
( N5 +2.5V )
( M5 ? )
( K5 /FPGA_Spartan6/M0_RAS# )
( J5 +2.5V )
( H5 /FPGA_Spartan6/M0_A2 )
( F5 ? )
( E5 ? )
( D5 ? )
( U4 ? )
( K21 /FPGA_Spartan6/M1_DQ6 )
( H21 /FPGA_Spartan6/R_M1_RAS# )
( G21 +2.5V )
( F21 /FPGA_Spartan6/R_M1_A0 )
( D21 /DDR_Banks/M1_CKE )
( C21 +2.5V )
( B21 ? )
( A21 ? )
( W20 ? )
( V20 ? )
( U20 /FPGA_Spartan6/M1_DQ12 )
( T20 ? )
( R20 /DDR_Banks/M1_DQ10 )
( P20 ? )
( N20 /DDR_Banks/M1_DQ0 )
( M20 /DDR_Banks/M1_UDM )
( L20 /DDR_Banks/M1_LDQS )
( K20 /DDR_Banks/M1_A5 )
( J20 /FPGA_Spartan6/M1_DQ4 )
( H20 /FPGA_Spartan6/M1_CLK )
( G20 /FPGA_Spartan6/R_M1_A3 )
( F20 /FPGA_Spartan6/M1_A4 )
( E20 /FPGA_Spartan6/M1_A7 )
( D20 ? )
( C20 /FPGA_Spartan6/M1_A8 )
( B20 ? )
( A20 ? )
( P8 ? )
( M8 ? )
( K8 ? )
( Y2 ? )
( W2 +2.5V )
( V2 /FPGA_Spartan6/M0_DQ14 )
( T2 /FPGA_Spartan6/M0_UDQS )
( R2 +2.5V )
( P2 /FPGA_Spartan6/M0_DQ8 )
( M2 /FPGA_Spartan6/M0_DQ2 )
( L2 +2.5V )
( K2 /DDR_Banks/M0_DQ6 )
( H2 /DDR_Banks/M0_A0 )
( G2 +2.5V )
( F2 /DDR_Banks/M0_WE# )
( D2 /FPGA_Spartan6/M0_CKE )
( C2 +2.5V )
( B2 ? )
( A2 ? )
( Y1 ? )
( W1 ? )
( V1 /FPGA_Spartan6/M0_DQ15 )
( U1 /FPGA_Spartan6/M0_DQ13 )
( T1 ? )
( R1 /FPGA_Spartan6/M0_DQ11 )
( P1 /DDR_Banks/M0_DQ9 )
( N1 /FPGA_Spartan6/M0_DQ1 )
( M1 /FPGA_Spartan6/M0_DQ3 )
( L1 ? )
( K1 /FPGA_Spartan6/M0_DQ7 )
( J1 /FPGA_Spartan6/M0_DQ5 )
( H1 /FPGA_Spartan6/M0_A1 )
( G1 /FPGA_Spartan6/M0_BA1 )
( T4 ? )
( R4 ? )
( P4 ? )
( N4 ? )
( M4 ? )
( L4 /FPGA_Spartan6/M0_LDM )
( K4 /FPGA_Spartan6/M0_CAS# )
( J4 /FPGA_Spartan6/M0_A6 )
( H4 /FPGA_Spartan6/M0_CLK )
( G4 /DDR_Banks/M0_A10 )
( F4 +2.5V )
( E4 ? )
( C4 ? )
( W3 ? )
( V3 ? )
( U3 /FPGA_Spartan6/M0_DQ12 )
( T3 ? )
( R3 /DDR_Banks/M0_DQ10 )
( P3 ? )
( N3 /FPGA_Spartan6/M0_DQ0 )
( M3 /DDR_Banks/M0_UDM )
( L3 /DDR_Banks/M0_LDQS )
( K3 /DDR_Banks/M0_A5 )
( J3 /FPGA_Spartan6/M0_DQ4 )
( H3 /FPGA_Spartan6/M0_CLK# )
( G3 /DDR_Banks/M0_BA0 )
( F3 /FPGA_Spartan6/M0_A4 )
( E3 /DDR_Banks/M0_A8 )
( D3 ? )
( C3 ? )
( B3 ? )
( G10 +3.3V )
( D10 /Ethernet_Phy/ETH_MDC )
( C10 /Ethernet_Phy/ETH_CRS )
( B10 /Ethernet_Phy/ETH_COL )
( A10 /Ethernet_Phy/ETH_INT )
( E9 +3.3V )
( D9 /Ethernet_Phy/ETH_TXD0 )
( C9 /Ethernet_Phy/ETH_TXD2 )
( A9 /FPGA_Spartan6/ETH_TXD3 )
( D8 /FPGA_Spartan6/ETH_RXC )
( C8 /Ethernet_Phy/ETH_TXD1 )
( B8 /Ethernet_Phy/ETH_TXER )
( A8 /Ethernet_Phy/ETH_TXEN )
( D7 /FPGA_Spartan6/ETH_TXC )
( C7 /Ethernet_Phy/ETH_RXDV )
( B7 +3.3V )
( A7 /Ethernet_Phy/ETH_RXER )
( D6 /FPGA_Spartan6/ETH_RXD3 )
( C6 /FPGA_Spartan6/ETH_RXD2 )
( B6 /Ethernet_Phy/ETH_RXD1 )
( A6 /Ethernet_Phy/ETH_RXD0 )
( C5 /FPGA_Spartan6/ETH_MDIO )
( A5 /FPGA_Spartan6/ETH_RESET_N )
( B4 +3.3V )
( A4 /Ethernet_Phy/ETH_CLK )
( A3 ? )
( U19 ? )
( T19 ? )
( R19 /USB/USBA_SPD )
( P19 ? )
( B19 +3.3V )
( B18 /FPGA_Spartan6/SD_DAT1 )
( A18 /Non_volatile_memories/SD_DAT0 )
( E17 +3.3V )
( D17 /FPGA_Spartan6/SD_CMD )
( C17 /FPGA_Spartan6/SD_DAT3 )
( A17 /Non_volatile_memories/SD_DAT2 )
( E16 /Non_volatile_memories/SD_CLK )
( C16 /Non_volatile_memories/NF_CS1_N )
( B16 /Non_volatile_memories/NF_RE_N )
( A16 /FPGA_Spartan6/NF_RNB )
( D15 /FPGA_Spartan6/NF_CLE )
( C15 /FPGA_Spartan6/NF_WE_N )
( B15 +3.3V )
( A15 /FPGA_Spartan6/NF_ALE )
( G14 +3.3V )
( D14 /Non_volatile_memories/NF_D0 )
( C14 ? )
( B14 ? )
( A14 ? )
( E13 +3.3V )
( C13 /Non_volatile_memories/NF_D2 )
( A13 /FPGA_Spartan6/NF_D1 )
( C12 /FPGA_Spartan6/NF_D5 )
( B12 /Non_volatile_memories/NF_D4 )
( A12 /Non_volatile_memories/NF_D3 )
( D11 /Non_volatile_memories/NF_D6 )
( C11 ? )
( B11 +3.3V )
( A11 /FPGA_Spartan6/NF_D7 )
( J16 ? )
( H16 ? )
( G16 ? )
( F16 ? )
( L15 ? )
( W22 ? )
( V22 /DDR_Banks/M1_DQ15 )
( U22 /DDR_Banks/M1_DQ13 )
( T22 ? )
( R22 /DDR_Banks/M1_DQ11 )
( P22 /FPGA_Spartan6/M1_DQ9 )
( N22 /FPGA_Spartan6/M1_DQ1 )
( M22 /DDR_Banks/M1_DQ3 )
( L22 ? )
( K22 /FPGA_Spartan6/M1_DQ7 )
( J22 /FPGA_Spartan6/M1_DQ5 )
( H22 /FPGA_Spartan6/R_M1_CAS# )
( G22 ? )
( F22 /FPGA_Spartan6/R_M1_A1 )
( E22 /FPGA_Spartan6/R_M1_A2 )
( D22 /FPGA_Spartan6/M1_A12 )
( C22 /FPGA_Spartan6/M1_A9 )
( B22 ? )
( W21 +2.5V )
( V21 /FPGA_Spartan6/M1_DQ14 )
( T21 /FPGA_Spartan6/M1_UDQS )
( R21 +2.5V )
( P21 /FPGA_Spartan6/M1_DQ8 )
( M21 /FPGA_Spartan6/M1_DQ2 )
( L21 +2.5V )
( N19 ? )
( M19 ? )
( L19 /FPGA_Spartan6/M1_LDM )
( K19 /DDR_Banks/M1_A6 )
( J19 /DDR_Banks/M1_CLK# )
( H19 /DDR_Banks/M1_WE# )
( G19 /FPGA_Spartan6/M1_A10 )
( F19 /DDR_Banks/M1_A11 )
( E19 +2.5V )
( D19 ? )
( C19 ? )
( U18 +2.5V )
( P18 /FPGA_Spartan6/USBA_OE_N )
( N18 +2.5V )
( M18 /USB/USBA_VM )
( K18 ? )
( J18 +2.5V )
( H18 ? )
( F18 ? )
( P17 /FPGA_Spartan6/USBA_VP )
( M17 ? )
( L17 ? )
( K17 /FPGA_Spartan6/R_M1_BA1 )
( J17 /FPGA_Spartan6/R_M1_BA0 )
( H17 ? )
( G17 ? )
( F17 ? )
( N16 /USB/USBA_RCV )
( M16 ? )
( L16 +2.5V )
( K16 ? )
( J14 +1.2V )
( H14 ? )
( F14 ? )
( E14 ? )
( P13 +1.2V )
( N13 GND )
( M13 +1.2V )
( L13 GND )
( K13 +1.2V )
( J13 GND )
( H13 ? )
( G13 ? )
( F13 ? )
( D13 ? )
( B13 GND )
( Y22 ? )
( A22 GND )
( R12 +2.5V )
( P12 GND )
( N12 +1.2V )
( M12 GND )
( L12 +1.2V )
( K12 GND )
( J12 +1.2V )
( H12 ? )
( G12 +2.5V )
( F12 ? )
( E12 ? )
( D12 ? )
( AB1 GND )
( A19 ? )
( R18 GND )
( L18 GND )
( G18 GND )
( E18 ? )
( D18 GND )
( C18 ? )
( R17 ? )
( N17 GND )
( B17 GND )
( W16 GND )
( P16 ? )
( D16 +2.5V )
( AA5 GND )
( P15 ? )
( N15 ? )
( M15 +2.5V )
( K15 +2.5V )
( J15 GND )
( H15 +2.5V )
( G15 ? )
( F15 ? )
( E15 GND )
( V14 GND )
( R14 +1.2V )
( P14 GND )
( N14 +1.2V )
( M14 GND )
( L14 +1.2V )
( K14 GND )
( L9 GND )
( K9 +1.2V )
( J9 GND )
( H9 +2.5V )
( G9 ? )
( F9 ? )
( B9 GND )
( N8 +2.5V )
( L8 +2.5V )
( J8 +1.2V )
( G8 ? )
( F8 ? )
( E8 ? )
( W7 GND )
( U7 GND )
( H7 GND )
( E7 GND )
( V6 +2.5V )
( R6 +2.5V )
( R5 GND )
( L5 GND )
( G5 GND )
( B5 GND )
( V4 GND )
( D4 GND )
( U2 GND )
( N2 GND )
( J2 GND )
( E2 GND )
( A1 GND )
( AA1 ? )
( U21 GND )
( N21 GND )
( J21 GND )
( E21 GND )
( U11 +2.5V )
( P11 +1.2V )
( N11 GND )
( M11 +1.2V )
( L11 GND )
( K11 +1.2V )
( J11 GND )
( H11 ? )
( G11 ? )
( F11 +2.5V )
( E11 GND )
( Y20 ? )
( V10 GND )
( R10 +2.5V )
( P10 GND )
( N10 +1.2V )
( M10 GND )
( L10 +1.2V )
( K10 GND )
( J10 +1.2V )
( H10 ? )
( F10 ? )
( E10 ? )
( P9 +1.2V )
( N9 GND )
( M9 +1.2V )
( V19 ? )
( AB8 ? )
( AA8 ? )
( Y18 ? )
( W18 ? )
( V18 ? )
( T18 ? )
( AB7 ? )
( AA7 VCCO2 )
( Y17 ? )
( W17 ? )
( V17 ? )
( U17 ? )
( T17 ? )
( AB6 ? )
( AA6 ? )
( Y16 ? )
( V16 VCCO2 )
( U16 ? )
( T16 ? )
( R16 ? )
( AB5 ? )
( Y15 ? )
( W15 ? )
( V15 ? )
( U15 ? )
( T15 ? )
( R15 ? )
( AB4 ? )
( AA4 ? )
( F1 ? )
( E1 /FPGA_Spartan6/M0_A9 )
( D1 /FPGA_Spartan6/M0_A12 )
( C1 /FPGA_Spartan6/M0_A11 )
( B1 ? )
( AB19 ? )
( AA19 VCCO2 )
( AB18 ? )
( AA18 ? )
( AB17 ? )
( AB16 ? )
( AA16 ? )
( AB15 ? )
( AA15 VCCO2 )
( AB14 ? )
( AA14 ? )
( AB13 ? )
( AA22 ? )
( AB12 ? )
( AA12 ? )
( AB21 ? )
( AA21 /FPGA_Spartan6/PROG_CCLK )
( AB11 ? )
( AA11 VCCO2 )
( AB20 /FPGA_Spartan6/PROG_MISO0 )
( AA20 /FPGA_Spartan6/PROG_MISO1 )
( AB10 ? )
( AA10 ? )
( AB9 ? )
( Y19 ? )
( V9 ? )
( U9 ? )
( T9 VCCO2 )
( R9 ? )
( Y8 ? )
( W8 ? )
( V8 VCCO2 )
( U8 ? )
( T8 ? )
( R8 ? )
( Y7 ? )
( V7 ? )
( T7 ? )
( R7 ? )
( Y6 ? )
( W6 ? )
( U6 ? )
( T6 ? )
( Y5 ? )
( W5 VCCO2 )
( V5 ? )
( T5 /FPGA_Spartan6/PROG_CSO )
( Y4 ? )
( W4 ? )
( Y3 ? )
( AA17 GND )
( AA13 GND )
( AB22 GND )
( AA9 GND )
( W19 GND )
( Y14 ? )
( W14 ? )
( U14 /FPGA_Spartan6/PROG_MISO2 )
( T14 ? )
( AB3 ? )
( AA3 VCCO2 )
( Y13 ? )
( W13 ? )
( V13 ? )
( U13 /FPGA_Spartan6/PROG_MISO3 )
( T13 VCCO2 )
( R13 ? )
( AB2 ? )
( AA2 ? )
( Y12 ? )
( W12 ? )
( V12 VCCO2 )
( U12 ? )
( T12 ? )
( Y21 ? )
( Y11 ? )
( W11 ? )
( V11 ? )
( T11 ? )
( R11 ? )
( Y10 ? )
( W10 ? )
( U10 ? )
( T10 ? )
( Y9 ? )
( W9 ? )
)
( /4C4320F3/4C5D8114 $noname C9 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_PLL1.8V )
( 2 GND )
)
( /4C4320F3/4C5D810A 0402 L3 FB {Lib=INDUCTOR}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 /Ethernet_Phy/ETH_PLL1.8V )
)
( /4C4320F3/4C5D8104 $noname C6 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 GND )
)
( /4C4320F3/4C5D80F3 0402 L1 FB {Lib=INDUCTOR}
( 1 +1.8V )
( 2 /Ethernet_Phy/ETH_A1.8V )
)
( /4C4320F3/4C5D80F0 $noname C4 100nF {Lib=C}
( 1 +1.8V )
( 2 GND )
)
( /4C4320F3/4C5D80ED $noname C2 1uF {Lib=C}
( 1 +1.8V )
( 2 GND )
)
( /4C4320F3/4C5D7FB7 0402 L2 FB {Lib=INDUCTOR}
( 1 +3.3V )
( 2 /Ethernet_Phy/ETH_A3.3V )
)
( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R}
( 1 /FPGA_Spartan6/ETH_MDIO )
( 2 +3.3V )
)
( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R}
( 1 N-000331 )
( 2 GND )
)
( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C}
( 1 N-000332 )
( 2 GND )
)
( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R}
( 1 N-000332 )
( 2 GND )
)
( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001}
( 1 /FPGA_Spartan6/ETH_MDIO )
( 2 /Ethernet_Phy/ETH_MDC )
( 3 /FPGA_Spartan6/ETH_RXD3 )
( 4 /FPGA_Spartan6/ETH_RXD2 )
( 5 /Ethernet_Phy/ETH_RXD1 )
( 6 /Ethernet_Phy/ETH_RXD0 )
( 7 +3.3V )
( 8 GND )
( 9 /Ethernet_Phy/ETH_RXDV )
( 10 /FPGA_Spartan6/ETH_RXC )
( 11 /Ethernet_Phy/ETH_RXER )
( 12 GND )
( 13 +1.8V )
( 14 /Ethernet_Phy/ETH_TXER )
( 15 /FPGA_Spartan6/ETH_TXC )
( 16 /Ethernet_Phy/ETH_TXEN )
( 17 /Ethernet_Phy/ETH_TXD0 )
( 18 /Ethernet_Phy/ETH_TXD1 )
( 19 /Ethernet_Phy/ETH_TXD2 )
( 20 /FPGA_Spartan6/ETH_TXD3 )
( 21 /Ethernet_Phy/ETH_COL )
( 22 /Ethernet_Phy/ETH_CRS )
( 23 GND )
( 24 +3.3V )
( 25 /Ethernet_Phy/ETH_INT )
( 26 /Ethernet_Phy/ETH_LED0 )
( 27 /Ethernet_Phy/ETH_LED1 )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 /Ethernet_Phy/ETH_A1.8V )
( 32 N-000338 )
( 33 N-000334 )
( 34 ? )
( 35 GND )
( 36 GND )
( 37 N-000331 )
( 38 /Ethernet_Phy/ETH_A3.3V )
( 39 GND )
( 40 N-000323 )
( 41 N-000335 )
( 42 ? )
( 43 ? )
( 44 GND )
( 45 ? )
( 46 /Ethernet_Phy/ETH_CLK )
( 47 /Ethernet_Phy/ETH_PLL1.8V )
( 48 /FPGA_Spartan6/ETH_RESET_N )
)
( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R}
( 1 +3.3V )
( 2 N-000335 )
)
( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R}
( 1 +3.3V )
( 2 N-000323 )
)
( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R}
( 1 +3.3V )
( 2 N-000338 )
)
( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R}
( 1 +3.3V )
( 2 N-000334 )
)
( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R}
( 1 N-000325 )
( 2 /Ethernet_Phy/ETH_LED1 )
)
( /4C4320F3/4C5D719D $noname R7 220 {Lib=R}
( 1 N-000337 )
( 2 /Ethernet_Phy/ETH_LED0 )
)
( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025}
( 1 N-000335 )
( 2 N-000323 )
( 3 +3.3V )
( 4 GND )
( 5 GND )
( 6 +3.3V )
( 7 N-000334 )
( 8 N-000338 )
( 9 +3.3V )
( 10 N-000337 )
( 11 +3.3V )
( 12 N-000325 )
( 13 N-000332 )
( 14 N-000332 )
)
( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /DDR_Banks/M1_DQ0 )
( 3 +2.5V )
( 4 /FPGA_Spartan6/M1_DQ1 )
( 5 /FPGA_Spartan6/M1_DQ2 )
( 6 GND )
( 7 /DDR_Banks/M1_DQ3 )
( 8 /FPGA_Spartan6/M1_DQ4 )
( 9 +2.5V )
( 10 /FPGA_Spartan6/M1_DQ5 )
( 11 /FPGA_Spartan6/M1_DQ6 )
( 12 GND )
( 13 /FPGA_Spartan6/M1_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /DDR_Banks/M1_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /FPGA_Spartan6/M1_LDM )
( 21 /DDR_Banks/M1_WE# )
( 22 /DDR_Banks/M1_CAS# )
( 23 /FPGA_Spartan6/M1_RAS# )
( 24 GND )
( 25 ? )
( 26 /DDR_Banks/M1_BA0 )
( 27 /DDR_Banks/M1_BA1 )
( 28 /FPGA_Spartan6/M1_A10 )
( 29 /FPGA_Spartan6/M1_A0 )
( 30 /DDR_Banks/M1_A1 )
( 31 /DDR_Banks/M1_A2 )
( 32 /FPGA_Spartan6/M1_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /FPGA_Spartan6/M1_A4 )
( 36 /DDR_Banks/M1_A5 )
( 37 /DDR_Banks/M1_A6 )
( 38 /FPGA_Spartan6/M1_A7 )
( 39 /FPGA_Spartan6/M1_A8 )
( 40 /FPGA_Spartan6/M1_A9 )
( 41 /DDR_Banks/M1_A11 )
( 42 /FPGA_Spartan6/M1_A12 )
( 43 ? )
( 44 /DDR_Banks/M1_CLK# )
( 45 /DDR_Banks/M1_CKE )
( 46 /FPGA_Spartan6/M1_CLK )
( 47 /DDR_Banks/M1_UDM )
( 48 GND )
( 49 N-000057 )
( 50 ? )
( 51 /FPGA_Spartan6/M1_UDQS )
( 52 GND )
( 53 ? )
( 54 /FPGA_Spartan6/M1_DQ8 )
( 55 +2.5V )
( 56 /FPGA_Spartan6/M1_DQ9 )
( 57 /DDR_Banks/M1_DQ10 )
( 58 GND )
( 59 /DDR_Banks/M1_DQ11 )
( 60 /FPGA_Spartan6/M1_DQ12 )
( 61 +2.5V )
( 62 /DDR_Banks/M1_DQ13 )
( 63 /FPGA_Spartan6/M1_DQ14 )
( 64 GND )
( 65 /DDR_Banks/M1_DQ15 )
( 66 GND )
)
( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D151 1206 C33 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R}
( 1 +2.5V )
( 2 N-000057 )
)
( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R}
( 1 N-000057 )
( 2 GND )
)
( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R}
( 1 N-000058 )
( 2 GND )
)
( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R}
( 1 +2.5V )
( 2 N-000058 )
)
( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP}
( 1 +2.5V )
( 2 N-000057 )
)
( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP}
( 1 N-000057 )
( 2 GND )
)
( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP}
( 1 N-000058 )
( 2 GND )
)
( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP}
( 1 +2.5V )
( 2 N-000058 )
)
( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /FPGA_Spartan6/M0_DQ0 )
( 3 +2.5V )
( 4 /FPGA_Spartan6/M0_DQ1 )
( 5 /FPGA_Spartan6/M0_DQ2 )
( 6 GND )
( 7 /FPGA_Spartan6/M0_DQ3 )
( 8 /FPGA_Spartan6/M0_DQ4 )
( 9 +2.5V )
( 10 /FPGA_Spartan6/M0_DQ5 )
( 11 /DDR_Banks/M0_DQ6 )
( 12 GND )
( 13 /FPGA_Spartan6/M0_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /DDR_Banks/M0_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /FPGA_Spartan6/M0_LDM )
( 21 /DDR_Banks/M0_WE# )
( 22 /FPGA_Spartan6/M0_CAS# )
( 23 /FPGA_Spartan6/M0_RAS# )
( 24 GND )
( 25 ? )
( 26 /DDR_Banks/M0_BA0 )
( 27 /FPGA_Spartan6/M0_BA1 )
( 28 /DDR_Banks/M0_A10 )
( 29 /DDR_Banks/M0_A0 )
( 30 /FPGA_Spartan6/M0_A1 )
( 31 /FPGA_Spartan6/M0_A2 )
( 32 /FPGA_Spartan6/M0_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /FPGA_Spartan6/M0_A4 )
( 36 /DDR_Banks/M0_A5 )
( 37 /FPGA_Spartan6/M0_A6 )
( 38 /FPGA_Spartan6/M0_A7 )
( 39 /DDR_Banks/M0_A8 )
( 40 /FPGA_Spartan6/M0_A9 )
( 41 /FPGA_Spartan6/M0_A11 )
( 42 /FPGA_Spartan6/M0_A12 )
( 43 ? )
( 44 /FPGA_Spartan6/M0_CLK# )
( 45 /FPGA_Spartan6/M0_CKE )
( 46 /FPGA_Spartan6/M0_CLK )
( 47 /DDR_Banks/M0_UDM )
( 48 GND )
( 49 N-000058 )
( 50 ? )
( 51 /FPGA_Spartan6/M0_UDQS )
( 52 GND )
( 53 ? )
( 54 /FPGA_Spartan6/M0_DQ8 )
( 55 +2.5V )
( 56 /DDR_Banks/M0_DQ9 )
( 57 /DDR_Banks/M0_DQ10 )
( 58 GND )
( 59 /FPGA_Spartan6/M0_DQ11 )
( 60 /FPGA_Spartan6/M0_DQ12 )
( 61 +2.5V )
( 62 /FPGA_Spartan6/M0_DQ13 )
( 63 /FPGA_Spartan6/M0_DQ14 )
( 64 GND )
( 65 /FPGA_Spartan6/M0_DQ15 )
( 66 GND )
)
)
*
{ Allowed footprints by component:
$component C75
SM*
C?
C1-1
$endlist
$component C74
SM*
C?
C1-1
$endlist
$component C73
SM*
C?
C1-1
$endlist
$component C72
SM*
C?
C1-1
$endlist
$component C35
SM*
C?
C1-1
$endlist
$component C36
SM*
C?
C1-1
$endlist
$component C37
SM*
C?
C1-1
$endlist
$component C38
SM*
C?
C1-1
$endlist
$component R15
R?
SM0603
SM0805
R?-*
$endlist
$component R10
R?
SM0603
SM0805
R?-*
$endlist
$component C16
SM*
C?
C1-1
$endlist
$component C15
SM*
C?
C1-1
$endlist
$component C14
SM*
C?
C1-1
$endlist
$component C13
SM*
C?
C1-1
$endlist
$component C66
SM*
C?
C1-1
$endlist
$component C63
SM*
C?
C1-1
$endlist
$component C60
SM*
C?
C1-1
$endlist
$component C57
SM*
C?
C1-1
$endlist
$component C54
SM*
C?
C1-1
$endlist
$component C69
SM*
C?
C1-1
$endlist
$component C67
SM*
C?
C1-1
$endlist
$component C64
SM*
C?
C1-1
$endlist
$component C61
SM*
C?
C1-1
$endlist
$component C58
SM*
C?
C1-1
$endlist
$component C55
SM*
C?
C1-1
$endlist
$component C68
SM*
C?
C1-1
$endlist
$component C65
SM*
C?
C1-1
$endlist
$component C62
SM*
C?
C1-1
$endlist
$component C59
SM*
C?
C1-1
$endlist
$component C56
SM*
C?
C1-1
$endlist
$component C50
SM*
C?
C1-1
$endlist
$component C47
SM*
C?
C1-1
$endlist
$component C44
SM*
C?
C1-1
$endlist
$component C41
SM*
C?
C1-1
$endlist
$component C53
SM*
C?
C1-1
$endlist
$component C51
SM*
C?
C1-1
$endlist
$component C49
SM*
C?
C1-1
$endlist
$component C46
SM*
C?
C1-1
$endlist
$component C52
SM*
C?
C1-1
$endlist
$component C43
SM*
C?
C1-1
$endlist
$component C40
SM*
C?
C1-1
$endlist
$component C48
SM*
C?
C1-1
$endlist
$component C45
SM*
C?
C1-1
$endlist
$component C42
SM*
C?
C1-1
$endlist
$component C39
SM*
C?
C1-1
$endlist
$component C9
SM*
C?
C1-1
$endlist
$component C6
SM*
C?
C1-1
$endlist
$component C4
SM*
C?
C1-1
$endlist
$component C2
SM*
C?
C1-1
$endlist
$component C8
SM*
C?
C1-1
$endlist
$component C7
SM*
C?
C1-1
$endlist
$component C5
SM*
C?
C1-1
$endlist
$component C3
SM*
C?
C1-1
$endlist
$component C1
SM*
C?
C1-1
$endlist
$component R1
R?
SM0603
SM0805
R?-*
$endlist
$component R2
R?
SM0603
SM0805
R?-*
$endlist
$component C11
SM*
C?
C1-1
$endlist
$component C10
SM*
C?
C1-1
$endlist
$component C12
SM*
C?
C1-1
$endlist
$component R9
R?
SM0603
SM0805
R?-*
$endlist
$component R3
R?
SM0603
SM0805
R?-*
$endlist
$component R4
R?
SM0603
SM0805
R?-*
$endlist
$component R6
R?
SM0603
SM0805
R?-*
$endlist
$component R5
R?
SM0603
SM0805
R?-*
$endlist
$component R8
R?
SM0603
SM0805
R?-*
$endlist
$component R7
R?
SM0603
SM0805
R?-*
$endlist
$component C70
SM*
C?
C1-1
$endlist
$component C71
SM*
C?
C1-1
$endlist
$component C34
SM*
C?
C1-1
$endlist
$component C33
SM*
C?
C1-1
$endlist
$component C28
SM*
C?
C1-1
$endlist
$component C29
SM*
C?
C1-1
$endlist
$component C31
SM*
C?
C1-1
$endlist
$component C30
SM*
C?
C1-1
$endlist
$component C32
SM*
C?
C1-1
$endlist
$component C27
SM*
C?
C1-1
$endlist
$component C21
SM*
C?
C1-1
$endlist
$component C26
SM*
C?
C1-1
$endlist
$component C24
SM*
C?
C1-1
$endlist
$component C25
SM*
C?
C1-1
$endlist
$component C23
SM*
C?
C1-1
$endlist
$component C22
SM*
C?
C1-1
$endlist
$component R13
R?
SM0603
SM0805
R?-*
$endlist
$component R14
R?
SM0603
SM0805
R?-*
$endlist
$component R12
R?
SM0603
SM0805
R?-*
$endlist
$component R11
R?
SM0603
SM0805
R?-*
$endlist
$component C19
SM*
C?
C1-1
$endlist
$component C20
SM*
C?
C1-1
$endlist
$component C18
SM*
C?
C1-1
$endlist
$component C17
SM*
C?
C1-1
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO"
U8 1
U1 T5
Net 2 "/Non volatile memories/NF_RE_N" "NF_RE_N"
U1 B16
U5 8
Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N"
U1 C16
U5 9
Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE"
U5 17
U1 A15
Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC"
U4 15
U1 D7
Net 6 "/FPGA Spartan6/ETH_RXC" "ETH_RXC"
U4 10
U1 D8
Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK"
U4 46
U1 A4
Net 8 "/USB/USBA_SPD" "USBA_SPD"
U1 R19
U6 2
Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N"
U1 P18
U6 9
Net 10 "/USB/USBA_RCV" "USBA_RCV"
U6 3
U1 N16
Net 11 "/FPGA Spartan6/USBA_VP" "USBA_VP"
U1 P17
U6 4
Net 12 "/USB/USBA_VM" "USBA_VM"
U6 5
U1 M18
Net 13 "/Ethernet Phy/ETH_COL" "ETH_COL"
U4 21
U1 B10
Net 14 "/Ethernet Phy/ETH_CRS" "ETH_CRS"
U1 C10
U4 22
Net 15 "/Non volatile memories/SD_CLK" "SD_CLK"
J1 5
U1 E16
Net 16 "/Ethernet Phy/ETH_INT" "ETH_INT"
U4 25
U1 A10
Net 17 "/Ethernet Phy/ETH_MDC" "ETH_MDC"
U1 D10
U4 2
Net 18 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO"
U1 C5
U4 1
R1 1
Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N"
U1 A5
U4 48
Net 20 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV"
U1 C7
U4 9
Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER"
U1 A7
U4 11
Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER"
U4 14
U1 B8
Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN"
U4 16
U1 A8
Net 24 "/DDR Banks/M1_UDM" "M1_UDM"
U1 M20
U3 47
Net 25 "/DDR Banks/M1_LDQS" "M1_LDQS"
U3 16
U1 L20
Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM"
U3 20
U1 L19
Net 27 "/FPGA Spartan6/M1_UDQS" "M1_UDQS"
U1 T21
U3 51
Net 28 "/FPGA Spartan6/M0_UDQS" "M0_UDQS"
U1 T2
U2 51
Net 29 "/FPGA Spartan6/M0_LDM" "M0_LDM"
U1 L4
U2 20
Net 30 "/DDR Banks/M1_CAS#" "M1_CAS#"
U3 22
RP2 8
Net 31 "/DDR Banks/M1_CKE" "M1_CKE"
U3 45
U1 D21
Net 32 "/FPGA Spartan6/M1_CLK" "M1_CLK"
U3 46
U1 H20
Net 33 "/DDR Banks/M1_CLK#" "M1_CLK#"
U3 44
U1 J19
Net 34 "GND" "GND"
C34 2
U2 34
C70 2
C71 2
U4 23
U4 44
U4 35
U4 36
C10 2
C11 2
R9 2
C12 2
C8 2
C7 2
C5 2
C3 2
C1 2
C29 2
C28 2
C33 2
C22 2
U2 58
C23 2
C25 2
C24 2
C26 2
C21 2
R2 2
U4 8
U4 12
U2 48
C27 2
C32 2
C30 2
C31 2
U1 J21
U1 N21
U1 U21
U1 AB1
U1 K12
U1 M12
C2 2
U1 K10
C4 2
C74 2
U1 M10
U1 P10
U1 V10
C75 1
U1 E11
U1 J11
U1 L11
U1 K14
C72 2
C73 2
U1 N11
U1 E21
U8 4
U1 AA17
U1 AA13
U1 AB22
U1 AA9
U1 W19
U1 R18
U1 L18
U1 G18
U1 D18
U1 N17
U1 B17
U1 A1
U1 E2
U1 J2
U1 N2
U1 U2
U1 D4
U1 V4
U1 B5
U1 G5
U1 L5
U1 R5
C6 2
C9 2
U1 M14
U1 P14
U1 V14
U1 E15
U1 J15
U1 AA5
U1 W16
U1 P12
U1 A22
U1 B13
U1 J13
U1 L13
U1 N13
U1 E7
U1 H7
U1 U7
U1 W7
U1 B9
U1 J9
U1 L9
U1 N9
J1 CASE
J1 CASE
J1 CASE
J1 COM
J1 6
U2 24
U2 52
U2 12
U2 66
U2 64
C18 2
C20 2
R12 2
R14 2
U2 6
U5 13
U5 36
C64 2
C61 2
L7 2
C48 2
C45 2
C42 2
C39 2
C40 2
U3 66
C58 2
C55 2
C44 2
C41 2
C68 2
U3 12
U3 64
U3 34
U3 24
U3 52
C50 2
U3 58
U3 48
C47 2
V4 2
V3 2
C38 2
R15 2
U7 8
L5 2
C37 2
C36 2
C35 2
C54 2
C16 2
C69 2
C66 2
V2 2
C43 2
C63 2
C60 2
C57 2
V1 2
U4 39
J4 5
J4 4
C67 2
R10 2
U6 8
U6 7
C49 2
C51 2
C13 2
C53 2
C56 2
C59 2
C14 2
U3 6
C15 2
U7 7
C62 2
C65 2
C52 2
C46 2
Net 35 "/FPGA Spartan6/M0_CLK#" "M0_CLK#"
U2 44
U1 H3
Net 36 "/FPGA Spartan6/M0_CLK" "M0_CLK"
U2 46
U1 H4
Net 37 "/FPGA Spartan6/M0_CKE" "M0_CKE"
U1 D2
U2 45
Net 38 "/FPGA Spartan6/M0_CAS#" "M0_CAS#"
U2 22
U1 K4
Net 39 "/DDR Banks/M1_WE#" "M1_WE#"
U1 H19
U3 21
Net 40 "/FPGA Spartan6/M1_RAS#" "M1_RAS#"
RP2 7
U3 23
Net 41 "/FPGA Spartan6/M0_RAS#" "M0_RAS#"
U2 23
U1 K5
Net 42 "/DDR Banks/M0_WE#" "M0_WE#"
U2 21
U1 F2
Net 43 "/DDR Banks/M0_LDQS" "M0_LDQS"
U1 L3
U2 16
Net 44 "/DDR Banks/M0_UDM" "M0_UDM"
U1 M3
U2 47
Net 45 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK"
U1 AA21
U8 6
Net 46 "/FPGA Spartan6/NF_RNB" "NF_RNB"
U1 A16
U5 7
U5 6
Net 47 "/FPGA Spartan6/NF_WE_N" "NF_WE_N"
U1 C15
U5 18
Net 48 "/FPGA Spartan6/NF_CLE" "NF_CLE"
U1 D15
U5 16
Net 49 "/FPGA Spartan6/SD_CMD" "SD_CMD"
U1 D17
J1 3
Net 55 "+2.5V" "+2.5V"
C51 1
U1 L8
U1 R10
U1 V6
C40 1
C49 1
C46 1
U1 N8
U1 G12
U1 R6
C43 1
U1 R2
U1 L2
U1 G2
U1 M15
U1 K15
U1 D16
C53 1
U1 U11
U1 F11
U1 H9
U1 C2
C52 1
U1 H15
U1 R12
U1 W21
C56 1
C59 1
C62 1
C65 1
U1 C21
U1 G21
U1 L21
U1 R21
U1 J18
U1 N18
C68 1
U1 U18
U1 W2
U1 F4
U1 L16
U1 E19
C63 1
C60 1
C57 1
C54 1
C66 1
U1 J5
U1 L7
U1 F6
U1 U5
U1 N5
U3 55
U3 1
R11 1
C34 1
C71 1
C70 1
U3 61
C15 1
U3 9
U2 1
U2 3
U3 15
C17 1
U3 33
U3 18
R13 1
C19 1
U3 3
U6 1
C21 1
C26 1
C24 1
C25 1
C23 1
C22 1
C33 1
C37 1
C28 1
C29 1
U2 33
U2 61
U2 18
U2 9
U7 1
C30 1
C32 1
C27 1
U2 55
U2 15
C31 1
Net 57 "" ""
R14 1
R13 2
C20 1
C19 2
U3 49
Net 58 "" ""
R12 1
U2 49
R11 2
C18 1
C17 2
Net 97 "+3.3V" "+3.3V"
J1 4
C14 1
C13 1
C41 1
C44 1
C47 1
C50 1
U7 12
U7 14
C35 1
C36 1
L2 1
C5 1
C3 1
C1 1
U4 24
U4 7
U6 12
U6 14
R5 1
R3 1
R4 1
R6 1
J4 9
J4 6
J4 3
J4 11
R1 2
C11 1
C10 1
U1 B7
C74 1
C75 2
U1 B4
U1 E13
U1 B11
U1 G10
U1 E9
U1 G14
U1 B15
C72 1
C73 1
U1 E17
U1 B19
U5 12
U5 19
U5 37
Net 98 "VCCO2" "VCCO2"
U1 T13
U1 AA19
U1 AA3
U8 8
U1 AA7
C58 1
C61 1
C64 1
U1 W5
C67 1
U1 V12
U1 V8
U1 AA11
U1 T9
U1 V16
C55 1
C69 1
U1 AA15
Net 241 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#"
U1 H21
RP2 2
Net 242 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#"
RP2 1
U1 H22
Net 243 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1"
RP2 4
U1 K17
Net 256 "/FPGA Spartan6/R_M1_A3" "R_M1_A3"
U1 G20
RP1 4
Net 308 "/FPGA Spartan6/R_M1_A0" "R_M1_A0"
U1 F21
RP1 1
Net 318 "/FPGA Spartan6/R_M1_A1" "R_M1_A1"
RP1 2
U1 F22
Net 319 "/FPGA Spartan6/R_M1_A2" "R_M1_A2"
U1 E22
RP1 3
Net 321 "+1.2V" "+1.2V"
U1 K9
C45 1
C39 1
C42 1
U1 M9
C48 1
U1 K13
U1 M13
U1 P13
U1 J14
U1 P11
U1 M11
U1 J12
U1 L12
U1 N12
U1 P9
U1 J10
U1 J8
U1 L10
U1 N10
U1 N14
U1 R14
U1 L14
U1 K11
Net 322 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0"
RP2 3
U1 J17
Net 323 "" ""
J4 2
U4 40
R4 2
Net 324 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
U4 27
R8 2
Net 325 "" ""
J4 12
R8 1
Net 328 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
C9 1
L3 2
U4 47
Net 329 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
C6 1
U4 31
L3 1
L1 2
Net 330 "+1.8V" "+1.8V"
C2 1
U4 13
L1 1
C4 1
Net 331 "" ""
R2 1
U4 37
Net 332 "" ""
J4 14
J4 13
R9 1
C12 1
Net 333 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
U4 38
C7 1
C8 1
L2 2
Net 334 "" ""
R5 2
U4 33
J4 7
Net 335 "" ""
U4 41
R3 2
J4 1
Net 336 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
U4 26
R7 2
Net 337 "" ""
J4 10
R7 1
Net 338 "" ""
U4 32
R6 2
J4 8
Net 344 "" ""
J5 3
U6 11
V1 1
V1 1
Net 345 "+5V" "+5V"
F2 2
F1 2
Net 346 "" ""
L4 2
J5 1
Net 347 "" ""
R10 1
C16 1
J5 S1
J5 S2
J5 S3
J5 S4
Net 348 "" ""
U6 10
J5 2
V2 1
V2 1
Net 349 "" ""
L5 1
J5 4
Net 351 "" ""
V3 1
U7 11
V3 1
Net 356 "" ""
V4 1
V4 1
U7 10
Net 357 "" ""
L6 1
F2 1
Net 359 "" ""
C38 1
R15 1
Net 361 "" ""
L4 1
F1 1
Net 362 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3"
U8 7
U1 U13
Net 363 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2"
U1 U14
U8 3
Net 364 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1"
U8 2
U1 AA20
Net 365 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0"
U1 AB20
U8 5
Net 366 "/FPGA Spartan6/NF_D7" "NF_D7"
U1 A11
U5 44
Net 367 "/Non volatile memories/NF_D6" "NF_D6"
U5 43
U1 D11
Net 368 "/FPGA Spartan6/NF_D5" "NF_D5"
U1 C12
U5 42
Net 369 "/Non volatile memories/NF_D4" "NF_D4"
U1 B12
U5 41
Net 370 "/Non volatile memories/NF_D3" "NF_D3"
U1 A12
U5 32
Net 371 "/Non volatile memories/NF_D2" "NF_D2"
U5 31
U1 C13
Net 372 "/FPGA Spartan6/NF_D1" "NF_D1"
U5 30
U1 A13
Net 373 "/Non volatile memories/NF_D0" "NF_D0"
U5 29
U1 D14
Net 374 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3"
U1 A9
U4 20
Net 375 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2"
U4 19
U1 C9
Net 376 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1"
U1 C8
U4 18
Net 377 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0"
U4 17
U1 D9
Net 378 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3"
U4 3
U1 D6
Net 379 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2"
U1 C6
U4 4
Net 380 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1"
U1 B6
U4 5
Net 381 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0"
U4 6
U1 A6
Net 382 "/FPGA Spartan6/M0_BA1" "M0_BA1"
U1 G1
U2 27
Net 383 "/DDR Banks/M0_BA0" "M0_BA0"
U2 26
U1 G3
Net 384 "/DDR Banks/M1_BA1" "M1_BA1"
U3 27
RP2 5
Net 385 "/DDR Banks/M1_BA0" "M1_BA0"
U3 26
RP2 6
Net 386 "/DDR Banks/M1_DQ15" "M1_DQ15"
U1 V22
U3 65
Net 387 "/FPGA Spartan6/M1_DQ14" "M1_DQ14"
U3 63
U1 V21
Net 388 "/DDR Banks/M1_DQ13" "M1_DQ13"
U3 62
U1 U22
Net 389 "/FPGA Spartan6/M1_DQ12" "M1_DQ12"
U3 60
U1 U20
Net 390 "/DDR Banks/M1_DQ11" "M1_DQ11"
U3 59
U1 R22
Net 391 "/DDR Banks/M1_DQ10" "M1_DQ10"
U1 R20
U3 57
Net 392 "/FPGA Spartan6/SD_DAT3" "SD_DAT3"
U1 C17
J1 2
Net 393 "/Non volatile memories/SD_DAT2" "SD_DAT2"
U1 A17
J1 1
Net 394 "/FPGA Spartan6/SD_DAT1" "SD_DAT1"
J1 8
U1 B18
Net 395 "/Non volatile memories/SD_DAT0" "SD_DAT0"
J1 7
U1 A18
Net 396 "/FPGA Spartan6/M1_A7" "M1_A7"
U1 E20
U3 38
Net 397 "/DDR Banks/M1_A6" "M1_A6"
U3 37
U1 K19
Net 398 "/DDR Banks/M1_A5" "M1_A5"
U1 K20
U3 36
Net 399 "/FPGA Spartan6/M1_A4" "M1_A4"
U3 35
U1 F20
Net 400 "/FPGA Spartan6/M1_A3" "M1_A3"
RP1 5
U3 32
Net 401 "/DDR Banks/M1_A2" "M1_A2"
U3 31
RP1 6
Net 402 "/DDR Banks/M1_A1" "M1_A1"
RP1 7
U3 30
Net 403 "/FPGA Spartan6/M1_A0" "M1_A0"
U3 29
RP1 8
Net 404 "/FPGA Spartan6/M0_A12" "M0_A12"
U2 42
U1 D1
Net 405 "/FPGA Spartan6/M0_A11" "M0_A11"
U2 41
U1 C1
Net 406 "/DDR Banks/M0_A10" "M0_A10"
U1 G4
U2 28
Net 407 "/FPGA Spartan6/M0_A9" "M0_A9"
U1 E1
U2 40
Net 408 "/DDR Banks/M0_A8" "M0_A8"
U1 E3
U2 39
Net 409 "/FPGA Spartan6/M0_A7" "M0_A7"
U2 38
U1 H6
Net 410 "/FPGA Spartan6/M1_DQ9" "M1_DQ9"
U3 56
U1 P22
Net 411 "/FPGA Spartan6/M1_DQ8" "M1_DQ8"
U3 54
U1 P21
Net 412 "/FPGA Spartan6/M1_DQ7" "M1_DQ7"
U1 K22
U3 13
Net 413 "/FPGA Spartan6/M1_DQ6" "M1_DQ6"
U3 11
U1 K21
Net 414 "/FPGA Spartan6/M1_DQ5" "M1_DQ5"
U3 10
U1 J22
Net 415 "/FPGA Spartan6/M1_DQ4" "M1_DQ4"
U1 J20
U3 8
Net 416 "/DDR Banks/M1_DQ3" "M1_DQ3"
U1 M22
U3 7
Net 417 "/FPGA Spartan6/M1_DQ2" "M1_DQ2"
U1 M21
U3 5
Net 418 "/FPGA Spartan6/M1_DQ1" "M1_DQ1"
U3 4
U1 N22
Net 419 "/DDR Banks/M1_DQ0" "M1_DQ0"
U3 2
U1 N20
Net 420 "/FPGA Spartan6/M1_A12" "M1_A12"
U3 42
U1 D22
Net 421 "/DDR Banks/M1_A11" "M1_A11"
U3 41
U1 F19
Net 422 "/FPGA Spartan6/M1_A10" "M1_A10"
U3 28
U1 G19
Net 423 "/FPGA Spartan6/M1_A9" "M1_A9"
U1 C22
U3 40
Net 424 "/FPGA Spartan6/M1_A8" "M1_A8"
U3 39
U1 C20
Net 425 "/FPGA Spartan6/M0_DQ3" "M0_DQ3"
U2 7
U1 M1
Net 426 "/FPGA Spartan6/M0_DQ2" "M0_DQ2"
U2 5
U1 M2
Net 427 "/FPGA Spartan6/M0_DQ1" "M0_DQ1"
U2 4
U1 N1
Net 428 "/FPGA Spartan6/M0_DQ0" "M0_DQ0"
U2 2
U1 N3
Net 429 "/FPGA Spartan6/M0_A6" "M0_A6"
U2 37
U1 J4
Net 430 "/DDR Banks/M0_A5" "M0_A5"
U2 36
U1 K3
Net 431 "/FPGA Spartan6/M0_A4" "M0_A4"
U2 35
U1 F3
Net 432 "/FPGA Spartan6/M0_A3" "M0_A3"
U2 32
U1 K6
Net 433 "/FPGA Spartan6/M0_A2" "M0_A2"
U2 31
U1 H5
Net 434 "/FPGA Spartan6/M0_A1" "M0_A1"
U2 30
U1 H1
Net 435 "/DDR Banks/M0_A0" "M0_A0"
U1 H2
U2 29
Net 436 "/FPGA Spartan6/M0_DQ15" "M0_DQ15"
U1 V1
U2 65
Net 437 "/FPGA Spartan6/M0_DQ14" "M0_DQ14"
U2 63
U1 V2
Net 438 "/FPGA Spartan6/M0_DQ13" "M0_DQ13"
U2 62
U1 U1
Net 439 "/FPGA Spartan6/M0_DQ12" "M0_DQ12"
U2 60
U1 U3
Net 440 "/FPGA Spartan6/M0_DQ11" "M0_DQ11"
U1 R1
U2 59
Net 441 "/DDR Banks/M0_DQ10" "M0_DQ10"
U2 57
U1 R3
Net 442 "/DDR Banks/M0_DQ9" "M0_DQ9"
U2 56
U1 P1
Net 443 "/FPGA Spartan6/M0_DQ8" "M0_DQ8"
U2 54
U1 P2
Net 444 "/FPGA Spartan6/M0_DQ7" "M0_DQ7"
U2 13
U1 K1
Net 445 "/DDR Banks/M0_DQ6" "M0_DQ6"
U1 K2
U2 11
Net 446 "/FPGA Spartan6/M0_DQ5" "M0_DQ5"
U2 10
U1 J1
Net 447 "/FPGA Spartan6/M0_DQ4" "M0_DQ4"
U2 8
U1 J3
}
#End
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