mirror of
git://projects.qi-hardware.com/xue.git
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469 lines
15 KiB
Verilog
469 lines
15 KiB
Verilog
/****************************************************************************************
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*
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* File Name: tb.v
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*
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* Dependencies: ddr2.v, ddr2_parameters.vh
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*
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* Description: Micron SDRAM DDR2 (Double Data Rate 2) test bench
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*
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* Note: -Set simulator resolution to "ps" accuracy
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* -Set Debug = 0 to disable $display messages
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
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// DO NOT CHANGE THE TIMESCALE
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`timescale 1ps / 1ps
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module tb;
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`include "ddr2_parameters.vh"
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// ports
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reg ck;
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wire ck_n = ~ck;
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reg cke;
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reg cs_n;
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reg ras_n;
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reg cas_n;
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reg we_n;
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reg [BA_BITS-1:0] ba;
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reg [ADDR_BITS-1:0] a;
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wire [DM_BITS-1:0] dm;
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wire [DQ_BITS-1:0] dq;
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wire [DQS_BITS-1:0] dqs;
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wire [DQS_BITS-1:0] dqs_n;
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wire [DQS_BITS-1:0] rdqs_n;
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reg odt;
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// mode registers
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reg [ADDR_BITS-1:0] mode_reg0; //Mode Register
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reg [ADDR_BITS-1:0] mode_reg1; //Extended Mode Register
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wire [2:0] cl = mode_reg0[6:4]; //CAS Latency
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wire bo = mode_reg0[3]; //Burst Order
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wire [7:0] bl = (1<<mode_reg0[2:0]); //Burst Length
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wire rdqs_en = mode_reg1[11]; //RDQS Enable
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wire dqs_n_en = ~mode_reg1[10]; //dqs# Enable
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wire [2:0] al = mode_reg1[5:3]; //Additive Latency
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wire [3:0] rl = al + cl; //Read Latency
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wire [3:0] wl = al + cl-1'b1; //Write Latency
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// dq transmit
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reg dq_en;
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reg [DM_BITS-1:0] dm_out;
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reg [DQ_BITS-1:0] dq_out;
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reg dqs_en;
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reg [DQS_BITS-1:0] dqs_out;
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assign dm = dq_en ? dm_out : {DM_BITS{1'bz}};
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assign dq = dq_en ? dq_out : {DQ_BITS{1'bz}};
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assign dqs = dqs_en ? dqs_out : {DQS_BITS{1'bz}};
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assign dqs_n = (dqs_en & dqs_n_en) ? ~dqs_out : {DQS_BITS{1'bz}};
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// dq receive
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reg [DM_BITS-1:0] dm_fifo [2*(AL_MAX+CL_MAX)+BL_MAX:0];
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reg [DQ_BITS-1:0] dq_fifo [2*(AL_MAX+CL_MAX)+BL_MAX:0];
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wire [DQ_BITS-1:0] q0, q1, q2, q3;
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reg [1:0] burst_cntr;
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assign rdqs_n = {DQS_BITS{1'bz}};
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// timing definition in tCK units
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real tck;
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wire [11:0] taa = ceil(CL_TIME/tck);
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wire [11:0] tanpd = TANPD;
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wire [11:0] taond = TAOND;
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wire [11:0] taofd = ceil(TAOFD);
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wire [11:0] taxpd = TAXPD;
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wire [11:0] tccd = TCCD;
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wire [11:0] tcke = TCKE;
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wire [11:0] tdllk = TDLLK;
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wire [11:0] tfaw = ceil(TFAW/tck);
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wire [11:0] tmod = ceil(TMOD/tck);
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wire [11:0] tmrd = TMRD;
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wire [11:0] tras = ceil(TRAS_MIN/tck);
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wire [11:0] trc = TRC;
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wire [11:0] trcd = ceil(TRCD/tck);
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wire [11:0] trfc = ceil(TRFC_MIN/tck);
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wire [11:0] trp = ceil(TRP/tck);
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wire [11:0] trrd = ceil(TRRD/tck);
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wire [11:0] trtp = ceil(TRTP/tck);
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wire [11:0] twr = ceil(TWR/tck);
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wire [11:0] twtr = ceil(TWTR/tck);
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wire [11:0] txard = TXARD;
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wire [11:0] txards = TXARDS;
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wire [11:0] txp = TXP;
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wire [11:0] txsnr = ceil(TXSNR/tck);
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wire [11:0] txsrd = TXSRD;
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initial begin
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$timeformat (-9, 1, " ns", 1);
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`ifdef period
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tck <= `period;
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`else
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tck <= TCK_MIN;
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`endif
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ck <= 1'b1;
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end
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// component instantiation
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ddr2 sdramddr2 (
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ck,
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ck_n,
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cke,
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cs_n,
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ras_n,
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cas_n,
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we_n,
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dm,
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ba,
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a,
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dq,
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dqs,
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dqs_n,
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rdqs_n,
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odt
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);
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// clock generator
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always @(posedge ck) begin
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ck <= #(tck/2) 1'b0;
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ck <= #(tck) 1'b1;
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end
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function integer ceil;
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input number;
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real number;
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if (number > $rtoi(number))
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ceil = $rtoi(number) + 1;
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else
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ceil = number;
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endfunction
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function integer max;
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input arg1;
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input arg2;
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integer arg1;
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integer arg2;
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if (arg1 > arg2)
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max = arg1;
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else
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max = arg2;
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endfunction
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task power_up;
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begin
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cke <= 1'b0;
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odt <= 1'b0;
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repeat(10) @(negedge ck);
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cke <= 1'b1;
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nop (400000/tck+1);
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end
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endtask
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task load_mode;
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input [BA_BITS-1:0] bank;
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input [ADDR_BITS-1:0] addr;
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begin
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case (bank)
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0: mode_reg0 = addr;
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1: mode_reg1 = addr;
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endcase
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b0;
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we_n <= 1'b0;
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ba <= bank;
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a <= addr;
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@(negedge ck);
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end
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endtask
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task refresh;
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b0;
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we_n <= 1'b1;
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@(negedge ck);
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end
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endtask
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task precharge;
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input [BA_BITS-1:0] bank;
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input ap; //precharge all
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b1;
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we_n <= 1'b0;
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ba <= bank;
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a <= (ap<<10);
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@(negedge ck);
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end
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endtask
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task activate;
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input [BA_BITS-1:0] bank;
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input [ROW_BITS-1:0] row;
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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ba <= bank;
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a <= row;
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@(negedge ck);
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end
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endtask
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//write task supports burst lengths <= 8
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task write;
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input [BA_BITS-1:0] bank;
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input [COL_BITS-1:0] col;
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input ap; //Auto Precharge
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input [8*DM_BITS-1:0] dm;
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input [8*DQ_BITS-1:0] dq;
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reg [ADDR_BITS-1:0] atemp [1:0];
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integer i;
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b1;
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cas_n <= 1'b0;
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we_n <= 1'b0;
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ba <= bank;
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atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0]
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atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10]
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a <= atemp[0] | atemp[1] | (ap<<10);
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for (i=0; i<=bl; i=i+1) begin
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dqs_en <= #(wl*tck + i*tck/2) 1'b1;
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if (i%2 == 0) begin
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dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b0}};
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end else begin
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dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b1}};
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end
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dq_en <= #(wl*tck + i*tck/2 + tck/4) 1'b1;
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dm_out <= #(wl*tck + i*tck/2 + tck/4) dm>>i*DM_BITS;
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dq_out <= #(wl*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
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end
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dqs_en <= #(wl*tck + bl*tck/2 + tck/2) 1'b0;
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dq_en <= #(wl*tck + bl*tck/2 + tck/4) 1'b0;
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@(negedge ck);
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end
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endtask
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// read without data verification
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task read;
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input [BA_BITS-1:0] bank;
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input [COL_BITS-1:0] col;
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input ap; //Auto Precharge
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reg [ADDR_BITS-1:0] atemp [1:0];
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b1;
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cas_n <= 1'b0;
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we_n <= 1'b1;
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ba <= bank;
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atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0]
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atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10]
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a <= atemp[0] | atemp[1] | (ap<<10);
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@(negedge ck);
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end
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endtask
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task nop;
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input [31:0] count;
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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repeat(count) @(negedge ck);
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end
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endtask
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task deselect;
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input [31:0] count;
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begin
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cke <= 1'b1;
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cs_n <= 1'b1;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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repeat(count) @(negedge ck);
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end
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endtask
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task power_down;
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input [31:0] count;
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begin
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cke <= 1'b0;
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cs_n <= 1'b1;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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repeat(count) @(negedge ck);
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end
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endtask
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task self_refresh;
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input [31:0] count;
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begin
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cke <= 1'b0;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b0;
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we_n <= 1'b1;
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cs_n <= #(tck) 1'b1;
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ras_n <= #(tck) 1'b1;
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cas_n <= #(tck) 1'b1;
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we_n <= #(tck) 1'b1;
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repeat(count) @(negedge ck);
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end
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endtask
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// read with data verification
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task read_verify;
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input [BA_BITS-1:0] bank;
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input [COL_BITS-1:0] col;
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input ap; //Auto Precharge
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input [8*DM_BITS-1:0] dm; //Expected Data Mask
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input [8*DQ_BITS-1:0] dq; //Expected Data
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integer i;
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begin
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read (bank, col, ap);
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for (i=0; i<bl; i=i+1) begin
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dm_fifo[2*rl + i] = dm >> (i*DM_BITS);
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dq_fifo[2*rl + i] = dq >> (i*DQ_BITS);
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end
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end
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endtask
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// receiver(s) for data_verify process
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dqrx dqrx[DQS_BITS-1:0] (dqs, dq, q0, q1, q2, q3);
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// perform data verification as a result of read_verify task call
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always @(ck) begin:data_verify
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integer i;
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integer j;
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reg [DQ_BITS-1:0] bit_mask;
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reg [DM_BITS-1:0] dm_temp;
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reg [DQ_BITS-1:0] dq_temp;
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for (i = !ck; (i < 2/(2.0 - !ck)); i=i+1) begin
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if (dm_fifo[i] === {DM_BITS{1'bx}}) begin
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burst_cntr = 0;
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end else begin
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dm_temp = dm_fifo[i];
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for (j=0; j<DQ_BITS; j=j+1) begin
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bit_mask[j] = !dm_temp[j/8];
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end
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case (burst_cntr)
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0: dq_temp = q0;
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1: dq_temp = q1;
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2: dq_temp = q2;
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3: dq_temp = q3;
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endcase
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//if ( ((dq_temp & bit_mask) === (dq_fifo[i] & bit_mask)))
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// $display ("%m at time %t: INFO: Successful read data compare. Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
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if ((dq_temp & bit_mask) !== (dq_fifo[i] & bit_mask))
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$display ("%m at time %t: ERROR: Read data miscompare. Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
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burst_cntr = burst_cntr + 1;
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end
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end
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if (ck) begin
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if (dm_fifo[2] === {DM_BITS{1'bx}}) begin
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dqrx[0%DQS_BITS].ptr <= 0; // v2k syntax
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dqrx[1%DQS_BITS].ptr <= 0; // v2k syntax
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dqrx[2%DQS_BITS].ptr <= 0; // v2k syntax
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dqrx[3%DQS_BITS].ptr <= 0; // v2k syntax
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end
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end else begin
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for (i=0; i<=(2*(AL_MAX+CL_MAX)+BL_MAX); i=i+1) begin
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dm_fifo[i] = dm_fifo[i+2];
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dq_fifo[i] = dq_fifo[i+2];
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end
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end
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end
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// End-of-test triggered in 'subtest.vh'
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task test_done;
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begin
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$display ("%m at time %t: INFO: Simulation is Complete", $time);
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$stop(0);
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end
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endtask
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// Test included from external file
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`include "subtest.vh"
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endmodule
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module dqrx (
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dqs, dq, q0, q1, q2, q3
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);
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`include "ddr2_parameters.vh"
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input dqs;
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input [DQ_BITS/DQS_BITS-1:0] dq;
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output [DQ_BITS/DQS_BITS-1:0] q0;
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output [DQ_BITS/DQS_BITS-1:0] q1;
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output [DQ_BITS/DQS_BITS-1:0] q2;
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output [DQ_BITS/DQS_BITS-1:0] q3;
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reg [DQ_BITS/DQS_BITS-1:0] q [3:0];
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assign q0 = q[0];
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assign q1 = q[1];
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assign q2 = q[2];
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assign q3 = q[3];
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reg [1:0] ptr;
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reg dqs_q;
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always @(dqs) begin
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if (dqs ^ dqs_q) begin
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#(TDQSQ + 1);
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q[ptr] <= dq;
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ptr <= (ptr + 1)%4;
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end
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dqs_q <= dqs;
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end
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endmodule
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