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1018 lines
13 KiB
Plaintext
1018 lines
13 KiB
Plaintext
# EESchema Netlist Version 1.1 created Sun 18 Jul 2010 08:11:46 PM COT
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( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001}
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( 1 ? )
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( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
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( P7 ? )
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( N7 ? )
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( M7 ? )
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( L7 N-000096 )
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( K7 ? )
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( J7 /FPGA_Spartan6/M0_DQ1 )
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( G7 /DDR_Banks/M0_DQ5 )
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( F7 ? )
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( P6 ? )
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( F6 N-000096 )
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( J5 N-000096 )
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( U4 ? )
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( H21 ? )
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( G21 N-000095 )
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( C21 N-000095 )
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( B21 ? )
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( U20 ? )
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( A20 ? )
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( P8 ? )
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( M8 ? )
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( K8 ? )
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( H8 /FPGA_Spartan6/M0_DQ2 )
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( B3 ? )
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( W2 N-000096 )
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( V2 ? )
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( G2 N-000096 )
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( F2 ? )
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( C2 N-000096 )
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( B2 /FPGA_Spartan6/M0_DQ3 )
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( A2 ? )
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( Y1 ? )
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( F4 N-000096 )
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( E4 /FPGA_Spartan6/M0_DQ0 )
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( C4 ? )
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( G10 N-000093 )
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( A10 ? )
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( E9 N-000093 )
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( D8 ? )
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( D7 ? )
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( C7 ? )
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( B7 N-000093 )
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( D6 ? )
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( B6 ? )
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( A6 ? )
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( C5 ? )
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( A5 ? )
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( B4 N-000093 )
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( A4 ? )
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( U19 ? )
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( R19 ? )
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( P19 ? )
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( N19 ? )
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( B19 N-000093 )
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( B18 ? )
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( E17 N-000093 )
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( B15 N-000093 )
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( D14 ? )
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( B14 ? )
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( E13 N-000093 )
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( A13 ? )
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( C12 ? )
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( B12 ? )
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( A12 ? )
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( B11 N-000093 )
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( A11 ? )
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( H16 ? )
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( G16 ? )
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( F16 ? )
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( L15 ? )
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( N22 ? )
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( M22 ? )
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( L22 ? )
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( E22 ? )
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( D22 ? )
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( C22 ? )
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( B22 ? )
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( W21 N-000095 )
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( V21 ? )
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( T21 ? )
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( R21 N-000095 )
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( P21 ? )
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( M21 ? )
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( L21 N-000095 )
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( L19 ? )
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( K19 ? )
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( J19 ? )
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( H19 ? )
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( G19 ? )
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( F19 ? )
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( E19 N-000095 )
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( D19 ? )
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( U18 N-000095 )
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( P18 ? )
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( N18 N-000095 )
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( M18 ? )
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( K18 ? )
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( J18 N-000095 )
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( H18 /FPGA_Spartan6/M1_DQ0 )
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( F18 ? )
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( P17 ? )
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( M17 ? )
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( L17 ? )
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( K17 ? )
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( J17 ? )
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( H17 ? )
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( G17 ? )
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( F17 ? )
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( N16 ? )
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( M16 ? )
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( L16 N-000095 )
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( K16 ? )
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( J16 ? )
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( J14 N-000098 )
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( H14 ? )
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( F14 ? )
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( E14 ? )
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( P13 N-000098 )
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( N13 GND )
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( M13 N-000098 )
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( L13 GND )
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( K13 N-000098 )
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( J13 GND )
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( H13 ? )
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( G13 ? )
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( F13 ? )
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( D13 ? )
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( B13 GND )
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( Y22 ? )
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( A22 GND )
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( R12 N-000097 )
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( P12 GND )
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( N12 N-000098 )
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( M12 GND )
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( L12 N-000098 )
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( K12 GND )
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( J12 N-000098 )
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( H12 ? )
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( G12 N-000097 )
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( F12 ? )
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( E12 ? )
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( D12 ? )
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( AB1 GND )
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( A19 ? )
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( R18 GND )
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( L18 GND )
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( G18 GND )
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( E18 ? )
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( D18 GND )
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( C18 ? )
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( R17 ? )
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( N17 GND )
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( B17 GND )
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( W16 GND )
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( P16 ? )
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( D16 N-000097 )
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( AA5 GND )
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( P15 ? )
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( N15 ? )
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( M15 N-000097 )
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( K15 N-000097 )
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( J15 GND )
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( H15 N-000097 )
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( G15 ? )
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( F15 ? )
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( E15 GND )
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( V14 GND )
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( R14 N-000098 )
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( P14 GND )
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( N14 N-000098 )
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( M14 GND )
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( L14 N-000098 )
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( K14 GND )
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( L9 GND )
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( K9 N-000098 )
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( J9 GND )
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( H9 N-000097 )
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( G9 ? )
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( F9 ? )
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( B9 GND )
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( N8 N-000097 )
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( L8 N-000097 )
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( J8 N-000098 )
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( G8 ? )
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( F8 ? )
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( E8 ? )
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( W7 GND )
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( U7 GND )
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( H7 GND )
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( E7 GND )
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( V6 N-000097 )
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( R6 N-000097 )
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( R5 GND )
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( L5 GND )
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( G5 GND )
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( B5 GND )
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( V4 GND )
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( D4 GND )
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( U2 GND )
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( N2 GND )
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( J2 GND )
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( E2 GND )
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( A1 GND )
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( AA1 ? )
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( U21 GND )
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( N21 GND )
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( J21 GND )
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( E21 GND )
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( U11 N-000097 )
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( P11 N-000098 )
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( N11 GND )
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( M11 N-000098 )
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( L11 GND )
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( K11 N-000098 )
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( J11 GND )
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( H11 ? )
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( G11 ? )
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( F11 N-000097 )
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( E11 GND )
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( V10 GND )
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( R10 N-000097 )
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( P10 GND )
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( N10 N-000098 )
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( M10 GND )
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( L10 N-000098 )
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( K10 GND )
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( J10 N-000098 )
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( H10 ? )
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( F10 ? )
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( E10 ? )
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( P9 N-000098 )
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( N9 GND )
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( M9 N-000098 )
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( V19 ? )
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( AB8 ? )
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( AA8 ? )
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( Y18 ? )
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( W18 ? )
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( V18 ? )
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( T18 ? )
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( AB7 ? )
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( AA7 N-000094 )
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( Y17 ? )
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( W17 ? )
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( V17 ? )
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( U17 ? )
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( T17 ? )
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( AB6 ? )
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( AA6 ? )
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( Y16 ? )
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( V16 N-000094 )
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( U16 ? )
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( T16 ? )
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( R16 ? )
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( AB5 ? )
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( Y15 ? )
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( W15 ? )
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( V15 ? )
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( U15 ? )
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( T15 ? )
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( R15 ? )
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( AB4 ? )
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( AA4 ? )
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( F1 ? )
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( E1 ? )
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( D1 ? )
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( C1 ? )
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( B1 /DDR_Banks/M0_DQ4 )
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( AB19 ? )
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( AA19 N-000094 )
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( AB18 ? )
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( AA18 ? )
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( AB17 ? )
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( AB16 ? )
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( AA16 ? )
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( AB15 ? )
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( AA15 N-000094 )
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( AB14 ? )
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( AA14 ? )
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( AB13 ? )
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( AA22 ? )
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( AB12 ? )
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( AA12 ? )
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( AB21 ? )
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( AA21 ? )
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( AB11 ? )
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( AA11 N-000094 )
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( AB20 ? )
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( AA20 ? )
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( AB10 ? )
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( AA10 ? )
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( AB9 ? )
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( Y19 ? )
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( V9 ? )
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( U9 ? )
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( T9 N-000094 )
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( R9 ? )
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( Y8 ? )
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( W8 ? )
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( V8 N-000094 )
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( U8 ? )
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( T8 ? )
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( R8 ? )
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( Y7 ? )
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( V7 ? )
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( T7 ? )
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( R7 ? )
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( Y6 ? )
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( W6 ? )
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( U6 ? )
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( T6 ? )
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( Y5 ? )
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( W5 N-000094 )
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( V5 ? )
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( T5 ? )
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( Y4 ? )
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( W4 ? )
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( Y3 ? )
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( AA17 GND )
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( AA13 GND )
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( AB22 GND )
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( AA9 GND )
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( W19 GND )
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( Y14 ? )
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( W14 ? )
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( U14 ? )
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( T14 ? )
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( AB3 ? )
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( AA3 N-000094 )
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( Y13 ? )
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( W13 ? )
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( V13 ? )
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( U13 ? )
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( T13 N-000094 )
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( R13 ? )
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( AB2 ? )
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( AA2 ? )
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( Y12 ? )
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( W12 ? )
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( V12 N-000094 )
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( U12 ? )
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( T12 ? )
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( Y11 ? )
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( W11 ? )
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( V11 ? )
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( T11 ? )
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( R11 ? )
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( Y10 ? )
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( W10 ? )
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( U10 ? )
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( T10 ? )
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( Y9 ? )
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( W9 ? )
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)
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( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD}
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( CASE GND )
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( COM GND )
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( CD ? )
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( 1 ? )
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( 2 ? )
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( 3 ? )
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( 4 ? )
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( 5 ? )
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( 6 ? )
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( 7 ? )
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( 8 ? )
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)
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( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M}
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( 1 ? )
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( 2 ? )
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( 3 ? )
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( 4 ? )
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( 5 ? )
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( 6 /Non_volatile_memories/FRB_N )
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( 7 /Non_volatile_memories/FRB_N )
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( 8 ? )
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( 9 ? )
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( 10 ? )
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( 11 ? )
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( 12 3.3V )
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( 13 GND )
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( 14 ? )
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( 15 ? )
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( 16 ? )
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( 17 ? )
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( 18 ? )
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( 19 3.3V )
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( 20 ? )
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( 21 ? )
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( 22 ? )
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( 23 ? )
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( 24 ? )
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( 25 ? )
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( 26 ? )
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( 27 ? )
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( 28 ? )
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( 29 ? )
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( 30 ? )
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( 31 ? )
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( 32 ? )
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( 33 ? )
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( 34 ? )
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( 35 ? )
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( 36 GND )
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( 37 3.3V )
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( 38 ? )
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( 39 ? )
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( 40 ? )
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( 41 ? )
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( 42 ? )
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( 43 ? )
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( 44 ? )
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( 45 ? )
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( 46 ? )
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( 47 ? )
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( 48 ? )
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|
)
|
|
( /4C421DD3/4C432040 $noname U3 MT46HC64M32LFCM {Lib=MT46HC64M32LFCM}
|
|
( G8 ? )
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|
( F8 ? )
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|
( E8 ? )
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|
( D8 ? )
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|
( C8 ? )
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( B8 ? )
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|
( A8 ? )
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|
( R7 N-000018 )
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|
( P7 ? )
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( N7 ? )
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( M7 ? )
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( L7 ? )
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|
( K7 ? )
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|
( J7 ? )
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|
( H7 ? )
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( G7 ? )
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|
( F7 ? )
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( E7 ? )
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|
( D7 ? )
|
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( C7 ? )
|
|
( B7 ? )
|
|
( A7 N-000018 )
|
|
( R9 N-000017 )
|
|
( P9 GND )
|
|
( N9 N-000018 )
|
|
( M9 GND )
|
|
( L9 N-000018 )
|
|
( K9 ? )
|
|
( J9 ? )
|
|
( H9 ? )
|
|
( G9 ? )
|
|
( F9 GND )
|
|
( E9 N-000018 )
|
|
( D9 GND )
|
|
( C9 N-000018 )
|
|
( B9 GND )
|
|
( A9 N-000017 )
|
|
( R8 /FPGA_Spartan6/M1_DQ0 )
|
|
( P8 ? )
|
|
( N8 ? )
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|
( M8 ? )
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|
( L8 ? )
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|
( K8 ? )
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|
( J8 ? )
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|
( H8 ? )
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|
( G2 ? )
|
|
( F2 ? )
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|
( E2 ? )
|
|
( D2 ? )
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|
( C2 ? )
|
|
( B2 ? )
|
|
( A2 ? )
|
|
( R1 GND )
|
|
( P1 N-000018 )
|
|
( N1 GND )
|
|
( M1 N-000018 )
|
|
( L1 GND )
|
|
( K1 ? )
|
|
( J1 ? )
|
|
( H1 ? )
|
|
( G1 ? )
|
|
( F1 N-000017 )
|
|
( E1 GND )
|
|
( D1 N-000018 )
|
|
( C1 GND )
|
|
( B1 N-000018 )
|
|
( A1 GND )
|
|
( R3 GND )
|
|
( P3 ? )
|
|
( N3 ? )
|
|
( M3 ? )
|
|
( L3 ? )
|
|
( K3 ? )
|
|
( J3 ? )
|
|
( H3 ? )
|
|
( G3 ? )
|
|
( F3 ? )
|
|
( E3 ? )
|
|
( D3 ? )
|
|
( C3 ? )
|
|
( B3 ? )
|
|
( A3 GND )
|
|
( R2 ? )
|
|
( P2 ? )
|
|
( N2 ? )
|
|
( M2 ? )
|
|
( L2 ? )
|
|
( K2 ? )
|
|
( J2 ? )
|
|
( H2 ? )
|
|
)
|
|
( /4C421DD3/4C43203A $noname U2 MT46HC64M32LFCM {Lib=MT46HC64M32LFCM}
|
|
( G8 ? )
|
|
( F8 ? )
|
|
( E8 ? )
|
|
( D8 ? )
|
|
( C8 ? )
|
|
( B8 ? )
|
|
( A8 ? )
|
|
( R7 N-000015 )
|
|
( P7 /FPGA_Spartan6/M0_DQ1 )
|
|
( N7 /FPGA_Spartan6/M0_DQ3 )
|
|
( M7 /DDR_Banks/M0_DQ5 )
|
|
( L7 ? )
|
|
( K7 ? )
|
|
( J7 ? )
|
|
( H7 ? )
|
|
( G7 ? )
|
|
( F7 ? )
|
|
( E7 ? )
|
|
( D7 ? )
|
|
( C7 ? )
|
|
( B7 ? )
|
|
( A7 N-000015 )
|
|
( R9 N-000019 )
|
|
( P9 GND )
|
|
( N9 N-000015 )
|
|
( M9 GND )
|
|
( L9 N-000015 )
|
|
( K9 ? )
|
|
( J9 ? )
|
|
( H9 ? )
|
|
( G9 ? )
|
|
( F9 GND )
|
|
( E9 N-000015 )
|
|
( D9 GND )
|
|
( C9 N-000015 )
|
|
( B9 GND )
|
|
( A9 N-000019 )
|
|
( R8 /FPGA_Spartan6/M0_DQ0 )
|
|
( P8 /FPGA_Spartan6/M0_DQ2 )
|
|
( N8 /DDR_Banks/M0_DQ4 )
|
|
( M8 ? )
|
|
( L8 ? )
|
|
( K8 ? )
|
|
( J8 ? )
|
|
( H8 ? )
|
|
( G2 ? )
|
|
( F2 ? )
|
|
( E2 ? )
|
|
( D2 ? )
|
|
( C2 ? )
|
|
( B2 ? )
|
|
( A2 ? )
|
|
( R1 GND )
|
|
( P1 N-000015 )
|
|
( N1 GND )
|
|
( M1 N-000015 )
|
|
( L1 GND )
|
|
( K1 ? )
|
|
( J1 ? )
|
|
( H1 ? )
|
|
( G1 ? )
|
|
( F1 N-000019 )
|
|
( E1 GND )
|
|
( D1 N-000015 )
|
|
( C1 GND )
|
|
( B1 N-000015 )
|
|
( A1 GND )
|
|
( R3 GND )
|
|
( P3 ? )
|
|
( N3 ? )
|
|
( M3 ? )
|
|
( L3 ? )
|
|
( K3 ? )
|
|
( J3 ? )
|
|
( H3 ? )
|
|
( G3 ? )
|
|
( F3 ? )
|
|
( E3 ? )
|
|
( D3 ? )
|
|
( C3 ? )
|
|
( B3 ? )
|
|
( A3 GND )
|
|
( R2 ? )
|
|
( P2 ? )
|
|
( N2 ? )
|
|
( M2 ? )
|
|
( L2 ? )
|
|
( K2 ? )
|
|
( J2 ? )
|
|
( H2 ? )
|
|
)
|
|
)
|
|
*
|
|
{ Pin List by Nets
|
|
Net 15 "" ""
|
|
U2 N9
|
|
U2 L9
|
|
U2 E9
|
|
U2 C9
|
|
U2 P1
|
|
U2 R7
|
|
U2 M1
|
|
U2 A7
|
|
U2 D1
|
|
U2 B1
|
|
Net 17 "" ""
|
|
U3 R9
|
|
U3 A9
|
|
U3 F1
|
|
Net 18 "" ""
|
|
U3 B1
|
|
U3 D1
|
|
U3 L9
|
|
U3 N9
|
|
U3 E9
|
|
U3 R7
|
|
U3 A7
|
|
U3 C9
|
|
U3 P1
|
|
U3 M1
|
|
Net 19 "" ""
|
|
U2 R9
|
|
U2 F1
|
|
U2 A9
|
|
Net 40 "GND" "GND"
|
|
U1 A1
|
|
U1 E2
|
|
U1 J2
|
|
U1 N2
|
|
U1 U2
|
|
U1 D4
|
|
U2 E1
|
|
U2 C1
|
|
U2 A1
|
|
U3 P9
|
|
U3 M9
|
|
U3 F9
|
|
U3 B9
|
|
U5 36
|
|
U1 L9
|
|
U1 N9
|
|
U1 K10
|
|
U1 M10
|
|
U1 P10
|
|
U1 V10
|
|
U1 E11
|
|
U1 J11
|
|
U1 V4
|
|
U1 B5
|
|
U1 G5
|
|
U1 L5
|
|
U1 R5
|
|
U1 E7
|
|
U1 H7
|
|
U1 U7
|
|
U1 W7
|
|
U1 B9
|
|
U1 J9
|
|
U3 A1
|
|
U3 C1
|
|
U5 13
|
|
U3 E1
|
|
U3 L1
|
|
U3 N1
|
|
U3 R1
|
|
J1 CASE
|
|
U2 A3
|
|
U2 R3
|
|
U2 L1
|
|
U2 N1
|
|
U2 R1
|
|
U2 B9
|
|
U2 D9
|
|
U2 F9
|
|
U2 M9
|
|
U2 P9
|
|
U3 R3
|
|
U3 A3
|
|
U3 D9
|
|
J1 CASE
|
|
J1 CASE
|
|
J1 COM
|
|
U1 R18
|
|
U1 J21
|
|
U1 E21
|
|
U1 N11
|
|
U1 L11
|
|
U1 N13
|
|
U1 W19
|
|
U1 J15
|
|
U1 K14
|
|
U1 M14
|
|
U1 AA9
|
|
U1 AB22
|
|
U1 AA13
|
|
U1 AA17
|
|
U1 P14
|
|
U1 E15
|
|
U1 V14
|
|
U1 J13
|
|
U1 L13
|
|
U1 AA5
|
|
U1 W16
|
|
U1 B17
|
|
U1 N17
|
|
U1 D18
|
|
U1 B13
|
|
U1 A22
|
|
U1 P12
|
|
U1 M12
|
|
U1 K12
|
|
U1 AB1
|
|
U1 G18
|
|
U1 U21
|
|
U1 N21
|
|
U1 L18
|
|
Net 81 "3.3V" "3.3V"
|
|
U5 12
|
|
U5 19
|
|
U5 37
|
|
Net 82 "/Non volatile memories/FRB_N" "FRB_N"
|
|
U5 6
|
|
U5 7
|
|
Net 93 "" ""
|
|
U1 G14
|
|
U1 B15
|
|
U1 E17
|
|
U1 B19
|
|
U1 B4
|
|
U1 E13
|
|
U1 B7
|
|
U1 E9
|
|
U1 G10
|
|
U1 B11
|
|
Net 94 "" ""
|
|
U1 AA7
|
|
U1 V8
|
|
U1 V16
|
|
U1 AA3
|
|
U1 T13
|
|
U1 W5
|
|
U1 T9
|
|
U1 V12
|
|
U1 AA11
|
|
U1 AA15
|
|
U1 AA19
|
|
Net 95 "" ""
|
|
U1 J18
|
|
U1 U18
|
|
U1 G21
|
|
U1 E19
|
|
U1 C21
|
|
U1 N18
|
|
U1 R21
|
|
U1 L21
|
|
U1 L16
|
|
U1 W21
|
|
Net 96 "" ""
|
|
U1 L2
|
|
U1 N5
|
|
U1 F6
|
|
U1 U5
|
|
U1 L7
|
|
U1 W2
|
|
U1 G2
|
|
U1 R2
|
|
U1 C2
|
|
U1 F4
|
|
U1 J5
|
|
Net 97 "" ""
|
|
U1 G12
|
|
U1 M15
|
|
U1 K15
|
|
U1 R12
|
|
U1 H15
|
|
U1 U11
|
|
U1 H9
|
|
U1 N8
|
|
U1 L8
|
|
U1 D16
|
|
U1 V6
|
|
U1 R6
|
|
U1 R10
|
|
U1 F11
|
|
Net 98 "" ""
|
|
U1 K9
|
|
U1 M9
|
|
U1 P9
|
|
U1 K13
|
|
U1 M13
|
|
U1 P13
|
|
U1 J14
|
|
U1 L14
|
|
U1 N14
|
|
U1 R14
|
|
U1 J10
|
|
U1 L10
|
|
U1 N10
|
|
U1 K11
|
|
U1 J8
|
|
U1 N12
|
|
U1 L12
|
|
U1 J12
|
|
U1 M11
|
|
U1 P11
|
|
Net 501 "/FPGA Spartan6/M0_DQ0" "M0_DQ0"
|
|
U2 R8
|
|
U1 E4
|
|
Net 502 "/FPGA Spartan6/M0_DQ1" "M0_DQ1"
|
|
U2 P7
|
|
U1 J7
|
|
Net 503 "/FPGA Spartan6/M0_DQ2" "M0_DQ2"
|
|
U2 P8
|
|
U1 H8
|
|
Net 504 "/FPGA Spartan6/M0_DQ3" "M0_DQ3"
|
|
U1 B2
|
|
U2 N7
|
|
Net 505 "/DDR Banks/M0_DQ4" "M0_DQ4"
|
|
U2 N8
|
|
U1 B1
|
|
Net 506 "/DDR Banks/M0_DQ5" "M0_DQ5"
|
|
U2 M7
|
|
U1 G7
|
|
Net 566 "/FPGA Spartan6/M1_DQ0" "M1_DQ0"
|
|
U1 H18
|
|
U3 R8
|
|
}
|
|
#End
|