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33 lines
875 B
Systemverilog
33 lines
875 B
Systemverilog
initial begin:test
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//ck <= 1'b0;
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cke <= 1'b0;
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cs_n <= 1'bz;
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ras_n <= 1'bz;
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cas_n <= 1'bz;
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we_n <= 1'bz;
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a <= {ADDR_BITS{1'bz}};
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ba <= {BA_BITS{1'bz}};
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dq_en <= 1'b0;
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dqs_en <= 1'b0;
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power_up;
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nop (10); // wait 10 clocks intead of 200 us for simulation purposes
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precharge('h00000000, 1);
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nop(trp);
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refresh;
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nop(trfc);
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refresh;
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nop(trfc);
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load_mode('h0, 'h00000032);
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nop(tmrd);
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load_mode('h2, 'h00004000);
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nop(tmrd);
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activate('h00000000, 'h00000000);
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nop(trcd-1);
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write('h00000000, 'h00000000, 0, { {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}}, { 16'h3000, 16'h2000, 16'h1000, 16'h0});
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nop(bl/2+twr);
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read('h00000000, 'h00000000, 1);
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nop(bl/2-1);
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nop('h00000014);
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test_done;
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end
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