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588 lines
20 KiB
Verilog
588 lines
20 KiB
Verilog
/****************************************************************************************
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*
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* File Name: tb.v
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* Version: 6.00
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* Model: BUS Functional
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*
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* Dependencies: mobile_ddr.v, mobile_ddr_parameters.vh, subtest.vh
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*
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* Description: Micron SDRAM DDR (Double Data Rate) test bench
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*
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* Note: -Set simulator resolution to "ps" accuracy
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* -Set Debug = 0 to disable $display messages
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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* Rev Author Date Changes
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* --- ------ ---------- ---------------------------------------
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* 4.1 JMK 01/14/2001 -Grouped specify parameters by speed grade
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* -Fixed mem_sizes parameter
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* 2.1 SPH 03/19/2002 -Second Release
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* -Fix tWR and several incompatability
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* between different simulators
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* 3.0 TFK 02/18/2003 -Added tDSS and tDSH timing checks.
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* -Added tDQSH and tDQSL timing checks.
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* 3.1 CAH 05/28/2003 -update all models to release version 3.1
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* (no changes to this model)
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* 3.2 JMK 06/16/2003 -updated all DDR400 models to support CAS Latency 3
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* 3.3 JMK 09/11/2003 -Added initialization sequence checks.
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* 4.0 JMK 12/01/2003 -Grouped parameters into "ddr_parameters.v"
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* -Fixed tWTR check
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* 4.2 JMK 03/19/2004 -Fixed pulse width checking on dqs
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* 4.3 JMK 04/27/2004 -Changed bl wire size in tb module
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* -Changed Dq_buf size to [15:0]
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* 5.0 JMK 06/16/2004 -Added read to write checking.
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* -Added read with precharge truncation to write checking.
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* -Added associative memory array to reduce memory consumption.
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* -Added checking for required DQS edges during write.
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* 6.0 DMR 12/03/2004 -new density
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* 6.01 BAAB 05/18/2006 -assimilating into Minneapolis site organization
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* 3.11 BAS 10/18/2006 -added read_verify
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* 3.35 bas 02/28/07 -mobile_ddr.v file uses tAC correctly to calculate strobe/data launch
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* 3.36 bas 03/05/07 -fixed error messages for different banks interrupting
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reads/writes w/autoprecharge
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* 3.37 bas 03/21/07 -added T47M part for 512Mb in parameters file,
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modified tXP check to measure in tCLK for T47M
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* 3.60 clk 09/19/07 -fixed dm/dq verification fifo's
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* 3.60 clk 09/19/07 -fixed dqrx module delay statement
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* 3.80 clk 10/29/07 - Support for 1024Mb T48M
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* 4.00 clk 12/30/07 - Fixed Read terminated by precharge testcase
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* 4.70 clk 03/30/08 - Fixed typo in SRR code
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* 4.80 clk 04/03/08 - Disable clk checking during initialization
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* 4.90 clk 04/16/08 - Fixed tInit, added mpc support, updated t35m timing
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* 5.00 clk 05/14/08 - Fixed back to back auto precharge commands
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* 5.20 clk 05/21/08 - Fixed read interrupt by pre (BL8), fixed 1024Mb parameter file
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* 5.30 clk 05/22/08 - Fixed DM signal which cause false tWTR errors
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05/27/08 - Rewrote write and read pipelins, strobes
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* 5.40 clk 05/28/08 - Fixed Addressing problem in Burst Order logic
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* 5.50 clk 07/25/08 - Added T36N part type
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* 5.60 clk 09/05/08 - Fixed tXP in 256Mb part type
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* 5.70 clk 09/17/08 - Fixed burst term check for write w/ all DM active
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* 5.80 clk 11/18/08 - Fixed internally latched dq & mask widths
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* 5.90 clk 12/10/08 - Updated T36N parameters to latest datasheet
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* 6.00 clk 03/05/09 - Fixed DQS problem w/ CL = 2
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****************************************************************************************/
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`timescale 1ns / 1ps
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module tb;
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`ifdef den128Mb
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`include "128Mb_mobile_ddr_parameters.vh"
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`elsif den256Mb
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`include "256Mb_mobile_ddr_parameters.vh"
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`elsif den512Mb
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`include "512Mb_mobile_ddr_parameters.vh"
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`elsif den1024Mb
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`include "1024Mb_mobile_ddr_parameters.vh"
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`elsif den2048Mb
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`include "2048Mb_mobile_ddr_parameters.vh"
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`else
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// NOTE: Intentionally cause a compile fail here to force the users
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// to select the correct component density before continuing
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ERROR: You must specify component density with +define+den____Mb.
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`endif
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reg ck_tb ;
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reg ck_enable = 1'b1 ;
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// ports
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wire ck;
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wire ck_n = ~ck;
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reg cke = 1'b0;
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reg cs_n;
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reg ras_n;
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reg cas_n;
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reg we_n;
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reg [BA_BITS-1:0] ba;
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reg [ADDR_BITS-1:0] a;
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wire [DM_BITS-1:0] dm;
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wire [DQ_BITS-1:0] dq;
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wire [DQS_BITS-1:0] dqs;
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// mode registers
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reg [ADDR_BITS-1:0] mode_reg0; //Mode Register
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reg [ADDR_BITS-1:0] mode_reg1; //Extended Mode Register
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wire [2:0] cl = mode_reg0[6:4]; //CAS Latency
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wire bo = mode_reg0[3]; //Burst Order
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wire [7:0] bl = (1<<mode_reg0[2:0]); //Burst Length
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wire wl = 1; //Write Latency
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// dq transmit
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reg dq_en;
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reg [DM_BITS-1:0] dm_out;
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reg [DQ_BITS-1:0] dq_out;
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reg dqs_en;
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reg [DQS_BITS-1:0] dqs_out;
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assign dm = dq_en ? dm_out : {DM_BITS{1'b0}};
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assign dq = dq_en ? dq_out : {DQ_BITS{1'bz}};
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assign dqs = dqs_en ? dqs_out : {DQS_BITS{1'bz}};
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// dq receive
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reg [DM_BITS-1:0] dm_fifo [2*CL_MAX+16:0];
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reg [DQ_BITS-1:0] dq_fifo [2*CL_MAX+16:0];
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wire [DQ_BITS-1:0] q0, q1, q2, q3;
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reg ptr_rst_n;
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reg [1:0] burst_cntr;
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// timing definition in tCK units
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real tck;
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wire [11:0] trc = tRC;
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wire [11:0] trrd = ceil(tRRD/tck);
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wire [11:0] trcd = ceil(tRCD/tck);
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wire [11:0] tras = ceil(tRAS/tck);
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wire [11:0] twr = ceil(tWR/tck);
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wire [11:0] trp = ceil(tRP/tck);
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wire [11:0] tmrd = tMRD;
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wire [11:0] trfc = ceil(tRFC/tck);
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wire [11:0] tsrr = ceil(tSRR);
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wire [11:0] tsrc = ceil(tSRC);
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wire [11:0] tdqsq = tDQSQ;
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wire [11:0] twtr = tWTR;
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initial begin
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$timeformat (-9, 1, " ns", 1);
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`ifdef period
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tck <= `period;
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`else
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tck <= tCK;
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`endif
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ck_tb <= 1'b1;
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dq_en <= 1'b0;
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dqs_en <= 1'b0;
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end
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// component instantiation
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mobile_ddr mobile_ddr (
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.Clk ( ck ) ,
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.Clk_n ( ck_n ) ,
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.Cke ( cke ) ,
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.Cs_n ( cs_n ) ,
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.Ras_n ( ras_n ) ,
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.Cas_n ( cas_n ) ,
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.We_n ( we_n ) ,
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.Addr ( a ) ,
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.Ba ( ba ) ,
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.Dq ( dq ) ,
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.Dqs ( dqs ) ,
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.Dm ( dm )
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);
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// clock generator
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assign ck = ck_enable & ck_tb ;
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always @(posedge ck_tb) begin
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ck_tb <= #(tck/2) 1'b0;
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ck_tb <= #(tck) 1'b1;
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end
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function integer ceil;
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input number;
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real number;
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if (number > $rtoi(number))
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ceil = $rtoi(number) + 1;
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else
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ceil = number;
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endfunction
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function integer max;
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input arg1;
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input arg2;
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integer arg1;
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integer arg2;
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if (arg1 > arg2)
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max = arg1;
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else
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max = arg2;
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endfunction
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function [8*DQ_BITS-1:0] burst_order;
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input [8-1:0] col;
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input [8*DQ_BITS-1:0] dq;
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reg [3:0] i;
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reg [2:0] j;
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integer k;
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begin
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burst_order = dq;
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for (i=0; i<bl; i=i+1) begin
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j = ((col%bl) ^ i);
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if (!bo)
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j[1:0] = (col + i);
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for (k=0; k<DQ_BITS; k=k+1) begin
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burst_order[i*DQ_BITS + k] = dq[j*DQ_BITS + k];
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end
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end
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end
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endfunction
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task power_up;
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begin
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cke <= 1'b0;
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cs_n <= 1'b1;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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ba <= {BA_BITS{1'b0}};
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a <= {ADDR_BITS{1'b0}};
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repeat(10) @(negedge ck_tb);
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@ (negedge ck_tb) cke <= 1'b1;
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$display ("%m at time %t TB: A 200 us delay is required after cke is brought high.", $time);
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end
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endtask
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task stop_clock_enter ;
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begin
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@ (negedge ck_tb);
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ck_enable = 1'b0 ;
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end
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endtask
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task stop_clock_exit ;
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begin
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@ (negedge ck_tb);
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ck_enable = 1'b1 ;
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end
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endtask
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task load_mode;
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input [BA_BITS-1:0] bank;
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input [ROW_BITS-1:0] row;
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begin
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case (bank)
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0: mode_reg0 = row;
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1: mode_reg1 = row;
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endcase
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b0;
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we_n <= 1'b0;
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ba <= bank;
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a <= row;
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@(negedge ck_tb);
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end
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endtask
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task refresh;
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b0;
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we_n <= 1'b1;
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@(negedge ck_tb);
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end
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endtask
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task precharge;
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input [BA_BITS-1:0] bank;
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input ap; //precharge all
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b1;
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we_n <= 1'b0;
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ba <= bank;
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a <= (ap<<10);
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@(negedge ck_tb);
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end
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endtask
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task activate;
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input [BA_BITS-1:0] bank;
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input [ROW_BITS-1:0] row;
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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ba <= bank;
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a <= row;
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@(negedge ck_tb);
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end
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endtask
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//write task supports burst lengths <= 8
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task write;
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input [BA_BITS-1:0] bank;
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input [COL_BITS-1:0] col;
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input ap; //Auto Precharge
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input [16*DM_BITS-1:0] dm;
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input [16*DQ_BITS-1:0] dq;
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reg [ADDR_BITS-1:0] atemp [1:0];
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integer i;
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b1;
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cas_n <= 1'b0;
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we_n <= 1'b0;
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ba <= bank;
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atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0]
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atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10]
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a <= atemp[0] | atemp[1] | (ap<<10);
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for (i=0; i<=bl; i=i+1) begin
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dqs_en <= #(wl*tck + i*tck/2) 1'b1;
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if (i%2 == 0) begin
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dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b0}};
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end else begin
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dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b1}};
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end
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dq_en <= #(wl*tck + i*tck/2 + tck/4) 1'b1;
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dm_out <= #(wl*tck + i*tck/2 + tck/4) dm>>i*DM_BITS;
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dq_out <= #(wl*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
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end
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dqs_en <= #(wl*tck + bl*tck/2 + tck/2) 1'b0;
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dq_en <= #(wl*tck + bl*tck/2 + tck/4) 1'b0;
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@(negedge ck_tb);
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end
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endtask
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// read without data verification
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task read;
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input [BA_BITS-1:0] bank;
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input [COL_BITS-1:0] col;
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input ap; //Auto Precharge
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reg [ADDR_BITS-1:0] atemp [1:0];
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b1;
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cas_n <= 1'b0;
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we_n <= 1'b1;
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ba <= bank;
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atemp[0] = col & 10'h3ff; //addr[ 9: 0] = COL[ 9: 0]
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atemp[1] = (col>>10)<<11; //addr[ N:11] = COL[ N:10]
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a <= atemp[0] | atemp[1] | (ap<<10);
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@(negedge ck_tb);
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end
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endtask
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task burst_term;
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integer i;
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b0;
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@(negedge ck_tb);
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for (i=0; i<bl; i=i+1) begin
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dm_fifo[2*cl + i] <= {DM_BITS{1'bx}};
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dq_fifo[2*cl + i] <= {DQ_BITS{1'bx}};
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end
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end
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endtask
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task nop;
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input [31:0] count;
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begin
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cke <= 1'b1;
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cs_n <= 1'b0;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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repeat(count) @(negedge ck_tb);
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end
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endtask
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task deselect;
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input [31:0] count;
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begin
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cke <= 1'b1;
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cs_n <= 1'b1;
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// ras_n <= 1'b1;
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// cas_n <= 1'b1;
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// we_n <= 1'b1;
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repeat(count) @(negedge ck_tb);
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end
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endtask
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task power_down;
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input [31:0] count;
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begin
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cke <= 1'b0;
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cs_n <= 1'b1;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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repeat(count) @(negedge ck_tb);
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end
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endtask
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task deep_power_down;
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input [31:0] count;
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begin
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cke <= 1'b0;
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cs_n <= 1'b0;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b0;
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repeat(count) @(negedge ck_tb);
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end
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endtask
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task self_refresh;
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input [31:0] count;
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begin
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cke <= 1'b0;
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cs_n <= 1'b0;
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ras_n <= 1'b0;
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cas_n <= 1'b0;
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we_n <= 1'b1;
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repeat(count) @(negedge ck_tb);
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end
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endtask
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// read with data verification
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task read_verify;
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input [BA_BITS-1:0] bank;
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input [COL_BITS-1:0] col;
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input ap; //Auto Precharge
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input [16*DM_BITS-1:0] dm; //Expected Data Mask
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input [16*DQ_BITS-1:0] dq; //Expected Data
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integer i;
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begin
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read (bank, col, ap);
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for (i=0; i<bl; i=i+1) begin
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dm_fifo[2*cl + i] <= dm>>(i*DM_BITS);
|
|
dq_fifo[2*cl + i] <= dq>>(i*DQ_BITS);
|
|
end
|
|
end
|
|
endtask
|
|
|
|
// receiver(s) for data_verify process
|
|
dqrx dqrx[DQS_BITS-1:0] (ptr_rst_n, dqs, dq, q0, q1, q2, q3);
|
|
|
|
// perform data verification as a result of read_verify task call
|
|
reg [DQ_BITS-1:0] bit_mask;
|
|
reg [DM_BITS-1:0] dm_temp;
|
|
reg [DQ_BITS-1:0] dq_temp;
|
|
always @(ck) begin:data_verify
|
|
integer i;
|
|
integer j;
|
|
|
|
for (i=!ck; (i<2/(2.0 - !ck)); i=i+1) begin
|
|
if (dm_fifo[i] === {DM_BITS{1'bx}}) begin
|
|
burst_cntr = 0;
|
|
end else begin
|
|
|
|
dm_temp = dm_fifo[i];
|
|
for (j=0; j<DQ_BITS; j=j+1) begin
|
|
bit_mask[j] = !dm_temp[j/(DQ_BITS/DM_BITS)];
|
|
end
|
|
|
|
case (burst_cntr)
|
|
0: dq_temp = q0;
|
|
1: dq_temp = q1;
|
|
2: dq_temp = q2;
|
|
3: dq_temp = q3;
|
|
endcase
|
|
//if ( ((dq_temp & bit_mask) === (dq_fifo[i] & bit_mask)))
|
|
// $display ("%m at time %t: INFO: Successful read data compare. Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
|
|
if ((dq_temp & bit_mask) !== (dq_fifo[i] & bit_mask))
|
|
$display ("%m at time %t: ERROR: Read data miscompare. Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
|
|
|
|
burst_cntr = burst_cntr + 1;
|
|
end
|
|
end
|
|
|
|
if (ck_tb) begin
|
|
ptr_rst_n <= (dm_fifo[4] !== {DM_BITS{1'bx}});
|
|
end else begin
|
|
//ptr_rst_n <= ptr_rst_n & (dm_fifo[6] !== {DM_BITS{1'bx}});
|
|
for (i=0; i<=2*CL_MAX+16; i=i+1) begin
|
|
dm_fifo[i] = dm_fifo[i+2];
|
|
dq_fifo[i] = dq_fifo[i+2];
|
|
end
|
|
end
|
|
end
|
|
|
|
// End-of-test triggered in 'subtest.vh'
|
|
task test_done;
|
|
begin
|
|
$display ("%m at time %t: INFO: Simulation is Complete", $time);
|
|
$stop(0);
|
|
end
|
|
endtask
|
|
|
|
// Test included from external file
|
|
`include "subtest.vh"
|
|
|
|
endmodule
|
|
|
|
module dqrx (
|
|
ptr_rst_n, dqs, dq, q0, q1, q2, q3
|
|
);
|
|
|
|
`ifdef den128Mb
|
|
`include "128Mb_mobile_ddr_parameters.vh"
|
|
`elsif den256Mb
|
|
`include "256Mb_mobile_ddr_parameters.vh"
|
|
`elsif den512Mb
|
|
`include "512Mb_mobile_ddr_parameters.vh"
|
|
`elsif den1024Mb
|
|
`include "1024Mb_mobile_ddr_parameters.vh"
|
|
`elsif den2048Mb
|
|
`include "2048Mb_mobile_ddr_parameters.vh"
|
|
`else
|
|
// NOTE: Intentionally cause a compile fail here to force the users
|
|
// to select the correct component density before continuing
|
|
ERROR: You must specify component density with +define+den____Mb.
|
|
`endif
|
|
|
|
input ptr_rst_n;
|
|
input dqs;
|
|
input [DQ_BITS/DQS_BITS-1:0] dq;
|
|
output [DQ_BITS/DQS_BITS-1:0] q0;
|
|
output [DQ_BITS/DQS_BITS-1:0] q1;
|
|
output [DQ_BITS/DQS_BITS-1:0] q2;
|
|
output [DQ_BITS/DQS_BITS-1:0] q3;
|
|
|
|
reg [1:0] ptr;
|
|
reg [DQ_BITS/DQS_BITS-1:0] q [3:0];
|
|
|
|
reg ptr_rst_dly_n;
|
|
always @(posedge ptr_rst_n) ptr_rst_dly_n <= #(tAC2_min + tDQSQ) ptr_rst_n;
|
|
always @(negedge ptr_rst_n) ptr_rst_dly_n <= #(tAC2_max + tDQSQ + 0.002) ptr_rst_n;
|
|
|
|
reg dqs_dly;
|
|
always @(dqs) dqs_dly <= #(tDQSQ + 0.001) dqs;
|
|
|
|
always @(negedge ptr_rst_dly_n or posedge dqs_dly or negedge dqs_dly) begin
|
|
if (!ptr_rst_dly_n) begin
|
|
ptr <= 0;
|
|
end else if (dqs_dly || ptr) begin
|
|
q[ptr] <= dq;
|
|
ptr <= ptr + 1;
|
|
end
|
|
end
|
|
|
|
assign q0 = q[0];
|
|
assign q1 = q[1];
|
|
assign q2 = q[2];
|
|
assign q3 = q[3];
|
|
endmodule
|