qi-hardware/xue
1
0
Fork 0
mirror of git://projects.qi-hardware.com/xue.git synced 2024-09-16 17:30:14 +03:00
Code
e40b97f200
xue/kicad/xue-rnc/xue-rnc.net
Andres Calderon eaf3abb511 40 pins connector added
2010-10-10 09:28:33 -05:00

4814 lines
86 KiB
Plaintext
Raw Blame History

# EESchema Netlist Version 1.1 created Sun 10 Oct 2010 09:15:11 AM COT
(
( /4CB0D95D/4CB0D9BF header20x2_smd_100mil P2 CONN_20X2 {Lib=CONN_20X2}
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 ? )
( 7 ? )
( 8 ? )
( 9 ? )
( 10 ? )
( 11 ? )
( 12 ? )
( 13 ? )
( 14 ? )
( 15 ? )
( 16 ? )
( 17 ? )
( 18 ? )
( 19 ? )
( 20 ? )
( 21 ? )
( 22 ? )
( 23 ? )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 ? )
( 32 ? )
( 33 ? )
( 34 ? )
( 35 ? )
( 36 ? )
( 37 ? )
( 38 ? )
( 39 ? )
( 40 ? )
)
( /4C9E2AF4/4CAF29D5 $noname MP1 M12-TU400A {Lib=M12-TU400A}
( 1 ? )
( 2 ? )
)
( /4C9E2AF4/4C9E3C76 $noname C140 100nF {Lib=C}
( 1 +2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C71 $noname C142 100nF {Lib=C}
( 1 +2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C70 $noname C144 10uF {Lib=CAPAPOL}
( 1 +2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C6F $noname C143 100nF {Lib=C}
( 1 +2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C6E $noname C141 100nF {Lib=C}
( 1 +2.8_VDDIO )
( 2 GND )
)
( /4C9E2AF4/4C9E3C65 $noname C136 100nF {Lib=C}
( 1 /Image_Sensor/+1.8_VDD )
( 2 GND )
)
( /4C9E2AF4/4C9E3C5F $noname C138 100nF {Lib=C}
( 1 /Image_Sensor/+1.8_VDD )
( 2 GND )
)
( /4C9E2AF4/4C9E3C5E $noname C139 10uF {Lib=CAPAPOL}
( 1 /Image_Sensor/+1.8_VDD )
( 2 GND )
)
( /4C9E2AF4/4C9E3C5D $noname C137 100nF {Lib=C}
( 1 /Image_Sensor/+1.8_VDD )
( 2 GND )
)
( /4C9E2AF4/4C9E3C32 $noname C133 100nF {Lib=C}
( 1 +2.8_VAA )
( 2 GND )
)
( /4C9E2AF4/4C9E3C2E $noname C135 10uF {Lib=CAPAPOL}
( 1 +2.8_VAA )
( 2 GND )
)
( /4C9E2AF4/4C9E3C2D $noname C134 100nF {Lib=C}
( 1 +2.8_VAA )
( 2 GND )
)
( /4C9E2AF4/4C9E3C27 $noname C131 100nF {Lib=C}
( 1 +2.8_VAAPIX )
( 2 GND )
)
( /4C9E2AF4/4C9E3C26 $noname C132 10uF {Lib=CAPAPOL}
( 1 +2.8_VAAPIX )
( 2 GND )
)
( /4C9E2AF4/4C9E3C04 $noname C130 10uF {Lib=CAPAPOL}
( 1 +2.8_VDDPLL )
( 2 GND )
)
( /4C9E2AF4/4C9E3C00 $noname C129 100nF {Lib=C}
( 1 +2.8_VDDPLL )
( 2 GND )
)
( /4C9E2AF4/4C9E3B7C $noname U24 MT9M033 {Lib=MT9M033}
( 1 /Image_Sensor/IS_DOUT4 )
( 2 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5 )
( 3 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT6 )
( 4 +2.8_VDDPLL )
( 5 /Image_Sensor/IS_EXTCLK )
( 6 GND )
( 7 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT7 )
( 8 /Image_Sensor/IS_DOUT8 )
( 9 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9 )
( 10 /Image_Sensor/IS_DOUT10 )
( 11 /Image_Sensor/IS_DOUT11 )
( 12 +2.8_VDDIO )
( 13 /Image_Sensor/IS_PIXEL )
( 14 /Image_Sensor/+1.8_VDD )
( 15 /FPGA,_Port0,_Port2,_PROG_IF/IS_SCL )
( 16 /Image_Sensor/IS_SDA )
( 17 /Image_Sensor/IS_RESET_N )
( 18 +2.8_VDDIO )
( 19 /Image_Sensor/+1.8_VDD )
( 20 ? )
( 21 ? )
( 22 /FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY )
( 23 /FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N )
( 24 /Image_Sensor/IS_I2C_ADDR )
( 25 /FPGA,_Port0,_Port2,_PROG_IF/IS_TEST )
( 26 /Image_Sensor/IS_FLASH )
( 27 /Image_Sensor/IS_TRIGGER )
( 28 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME )
( 29 /FPGA,_Port0,_Port2,_PROG_IF/IS_LINE )
( 30 GND )
( 31 ? )
( 32 ? )
( 33 ? )
( 34 +2.8_VAA )
( 35 GND )
( 36 +2.8_VAA )
( 37 +2.8_VAAPIX )
( 38 +2.8_VAAPIX )
( 39 GND )
( 40 +2.8_VAA )
( 41 ? )
( 42 ? )
( 43 ? )
( 44 GND )
( 45 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0 )
( 46 /Image_Sensor/IS_DOUT1 )
( 47 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2 )
( 48 /Image_Sensor/IS_DOUT3 )
)
( /4C9E2B0F/4C9E2BAA $noname C107 10uF {Lib=CAPAPOL}
( 1 N-000498 )
( 2 GND )
)
( /4C9E2B0F/4C9E2BA9 $noname C110 10nF {Lib=C}
( 1 N-000486 )
( 2 GND )
)
( /4C9E2B0F/4C9E2BA8 $noname R64 R {Lib=R}
( 1 N-000485 )
( 2 GND )
)
( /4C9E2B0F/4C9E2BA7 $noname R63 R {Lib=R}
( 1 /Image_Sensor/+1.8_VDD )
( 2 N-000485 )
)
( /4C9E2B0F/4C9E2BA6 $noname C116 10uF {Lib=CAPAPOL}
( 1 /Image_Sensor/+1.8_VDD )
( 2 GND )
)
( /4C9E2B0F/4C9E2BA5 $noname C113 22pF {Lib=C}
( 1 /Image_Sensor/+1.8_VDD )
( 2 N-000485 )
)
( /4C9E2B0F/4C9E2BA4 $noname U20 TPS793XX {Lib=TPS793XX}
( 1 N-000498 )
( 2 GND )
( 3 N-000498 )
( 4 N-000486 )
( 5 N-000485 )
( 6 /Image_Sensor/+1.8_VDD )
)
( /4C9E2B0F/4C9E2B96 $noname U23 TPS793XX {Lib=TPS793XX}
( 1 N-000487 )
( 2 GND )
( 3 N-000487 )
( 4 N-000495 )
( 5 N-000494 )
( 6 +2.8_VDDPLL )
)
( /4C9E2B0F/4C9E2B95 $noname C125 22pF {Lib=C}
( 1 +2.8_VDDPLL )
( 2 N-000494 )
)
( /4C9E2B0F/4C9E2B94 $noname C128 10uF {Lib=CAPAPOL}
( 1 +2.8_VDDPLL )
( 2 GND )
)
( /4C9E2B0F/4C9E2B93 $noname R67 R {Lib=R}
( 1 +2.8_VDDPLL )
( 2 N-000494 )
)
( /4C9E2B0F/4C9E2B92 $noname R68 R {Lib=R}
( 1 N-000494 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B91 $noname C121 10nF {Lib=C}
( 1 N-000495 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B90 $noname C118 10uF {Lib=CAPAPOL}
( 1 N-000487 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B86 $noname C117 10uF {Lib=CAPAPOL}
( 1 N-000496 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B85 $noname C120 10nF {Lib=C}
( 1 N-000497 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B84 $noname R66 R {Lib=R}
( 1 N-000500 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B83 $noname R65 R {Lib=R}
( 1 +2.8_VDDIO )
( 2 N-000500 )
)
( /4C9E2B0F/4C9E2B82 $noname C127 10uF {Lib=CAPAPOL}
( 1 +2.8_VDDIO )
( 2 GND )
)
( /4C9E2B0F/4C9E2B81 $noname C124 22pF {Lib=C}
( 1 +2.8_VDDIO )
( 2 N-000500 )
)
( /4C9E2B0F/4C9E2B80 $noname U22 TPS793XX {Lib=TPS793XX}
( 1 N-000496 )
( 2 GND )
( 3 N-000496 )
( 4 N-000497 )
( 5 N-000500 )
( 6 +2.8_VDDIO )
)
( /4C9E2B0F/4C9E2B72 $noname U19 TPS793XX {Lib=TPS793XX}
( 1 N-000493 )
( 2 GND )
( 3 N-000493 )
( 4 N-000492 )
( 5 N-000491 )
( 6 +2.8_VAAPIX )
)
( /4C9E2B0F/4C9E2B71 $noname C112 22pF {Lib=C}
( 1 +2.8_VAAPIX )
( 2 N-000491 )
)
( /4C9E2B0F/4C9E2B70 $noname C115 10uF {Lib=CAPAPOL}
( 1 +2.8_VAAPIX )
( 2 GND )
)
( /4C9E2B0F/4C9E2B6F $noname R61 R {Lib=R}
( 1 +2.8_VAAPIX )
( 2 N-000491 )
)
( /4C9E2B0F/4C9E2B6E $noname R62 R {Lib=R}
( 1 N-000491 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B6D $noname C109 10nF {Lib=C}
( 1 N-000492 )
( 2 GND )
)
( /4C9E2B0F/4C9E2B6C $noname C106 10uF {Lib=CAPAPOL}
( 1 N-000493 )
( 2 GND )
)
( /4C9E2B0F/4C9E28CB $noname C105 10uF {Lib=CAPAPOL}
( 1 N-000499 )
( 2 GND )
)
( /4C9E2B0F/4C9E28C1 $noname C108 10nF {Lib=C}
( 1 N-000490 )
( 2 GND )
)
( /4C9E2B0F/4C9E289D $noname R60 R {Lib=R}
( 1 N-000488 )
( 2 GND )
)
( /4C9E2B0F/4C9E287F $noname R59 R {Lib=R}
( 1 +2.8_VAA )
( 2 N-000488 )
)
( /4C9E2B0F/4C9E286D $noname C114 10uF {Lib=CAPAPOL}
( 1 +2.8_VAA )
( 2 GND )
)
( /4C9E2B0F/4C9E2857 $noname C111 22pF {Lib=C}
( 1 +2.8_VAA )
( 2 N-000488 )
)
( /4C9E2B0F/4C9E2848 $noname U18 TPS793XX {Lib=TPS793XX}
( 1 N-000499 )
( 2 GND )
( 3 N-000499 )
( 4 N-000490 )
( 5 N-000488 )
( 6 +2.8_VAA )
)
( /4C7BC2B2/4C749A0C 0402 C94 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C748EDB 0402 C92 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C748EDA 0402 C93 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C73D252 0402 C91 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C73D074 0402 C90 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C7168DD 0402 R30 330 {Lib=R}
( 1 +3.3V )
( 2 N-000395 )
)
( /4C7BC2B2/4C716877 0402 R29 4.7k {Lib=R}
( 1 +3.3V )
( 2 N-000397 )
)
( /4C7BC2B2/4C6B29DA 0402 C77 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C6B29A3 0402 C76 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C656D9D $noname C66 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D9A $noname C63 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D99 $noname C60 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D98 $noname C57 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D97 $noname C54 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656D53 $noname C69 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D49 $noname C67 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D46 $noname C64 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D45 $noname C61 470nF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D44 $noname C58 4.7uF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D43 $noname C55 100uF {Lib=C}
( 1 VCCO2 )
( 2 GND )
)
( /4C7BC2B2/4C656D08 $noname C68 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CFC $noname C65 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CFB $noname C62 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CFA $noname C59 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CF9 $noname C56 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656CBB $noname C50 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C656CBA $noname C47 470nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C656CB9 $noname C44 4.7uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C656CB7 $noname C41 100uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C7BC2B2/4C656C49 $noname C53 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656C27 $noname C51 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656C24 $noname C49 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656C16 $noname C46 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656BFA $noname C52 470nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656BF9 $noname C43 4.7uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656BF8 $noname C40 100uF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C7BC2B2/4C656AC2 $noname C48 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C656AC0 $noname C45 470nF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C656ABD $noname C42 4.7uF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C656A80 $noname C39 100uF {Lib=C}
( 1 +1.2V )
( 2 GND )
)
( /4C7BC2B2/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
( A1 GND )
( A2 ? )
( A3 ? )
( A4 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK )
( A5 /Ethernet_Phy/ETH_RXD1 )
( A6 /Ethernet_Phy/ETH_RXDV )
( A7 /Ethernet_Phy/ETH_RXC )
( A8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 )
( A9 /Ethernet_Phy/ETH_COL )
( A10 /Ethernet_Phy/ETH_INT )
( A11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D6 )
( A12 /Non_volatile_memories/NF_D4 )
( A13 /Non_volatile_memories/NF_D2 )
( A14 /FPGA,_Port0,_Port2,_PROG_IF/NF_ALE )
( A15 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB )
( A16 /Non_volatile_memories/SD_DAT2 )
( A17 /FPGA,_Port0,_Port2,_PROG_IF/SD_CLK )
( A18 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0 )
( A19 /DBG_PRG/FPGA_TDO )
( A20 /USB/USBD_RCV )
( A21 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N )
( A22 GND )
( AA1 N-000397 )
( AA2 /FPGA,_Port0,_Port2,_PROG_IF/IS_LINE )
( AA3 VCCO2 )
( AA4 /FPGA,_Port0,_Port2,_PROG_IF/IS_TEST )
( AA5 GND )
( AA6 /Image_Sensor/IS_SDA )
( AA7 VCCO2 )
( AA8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT7 )
( AA9 GND )
( AA10 /Image_Sensor/IS_DOUT4 )
( AA11 VCCO2 )
( AA12 /Image_Sensor/IS_DOUT1 )
( AA13 GND )
( AA14 ? )
( AA15 VCCO2 )
( AA16 ? )
( AA17 GND )
( AA18 ? )
( AA19 VCCO2 )
( AA20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 )
( AA21 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK )
( AA22 ? )
( AB1 GND )
( AB2 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME )
( AB3 /Image_Sensor/IS_FLASH )
( AB4 /Image_Sensor/IS_I2C_ADDR )
( AB5 /Image_Sensor/IS_RESET_N )
( AB6 /Image_Sensor/IS_PIXEL )
( AB7 /Image_Sensor/IS_DOUT11 )
( AB8 /Image_Sensor/IS_DOUT8 )
( AB9 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5 )
( AB10 /Image_Sensor/IS_DOUT3 )
( AB11 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2 )
( AB12 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0 )
( AB13 ? )
( AB14 ? )
( AB15 ? )
( AB16 ? )
( AB17 ? )
( AB18 ? )
( AB19 ? )
( AB20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0 )
( AB21 ? )
( AB22 GND )
( B1 ? )
( B2 ? )
( B3 ? )
( B4 +3.3V )
( B5 GND )
( B6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 )
( B7 +3.3V )
( B8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER )
( B9 GND )
( B10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS )
( B11 +3.3V )
( B12 /Non_volatile_memories/NF_D3 )
( B13 GND )
( B14 /FPGA,_Port0,_Port2,_PROG_IF/NF_CLE )
( B15 +3.3V )
( B16 /Non_volatile_memories/SD_DAT3 )
( B17 GND )
( B18 /Non_volatile_memories/SD_DAT1 )
( B19 +3.3V )
( B20 /USB/USBD_SPD )
( B21 /USB/USBD_VP )
( B22 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM )
( C1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11 )
( C2 +2.5V )
( C3 ? )
( C4 ? )
( C5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3 )
( C6 /Ethernet_Phy/ETH_RXD2 )
( C7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N )
( C8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC )
( C9 /Ethernet_Phy/ETH_TXD1 )
( C10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 )
( C11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 )
( C12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D0 )
( C13 ? )
( C14 /FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N )
( C15 /Non_volatile_memories/NF_RE_N )
( C16 /FPGA,_Port0,_Port2,_PROG_IF/SD_CMD )
( C17 ? )
( C18 /DBG_PRG/FPGA_TMS )
( C19 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N )
( C20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 )
( C21 +2.5V )
( C22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9 )
( D1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12 )
( D2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE )
( D3 ? )
( D4 GND )
( D5 ? )
( D6 /Ethernet_Phy/ETH_MDIO )
( D7 /Ethernet_Phy/ETH_MDC )
( D8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER )
( D9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN )
( D10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 )
( D11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D7 )
( D12 ? )
( D13 ? )
( D14 /FPGA,_Port0,_Port2,_PROG_IF/NF_D1 )
( D15 /FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N )
( D16 +2.5V )
( D17 ? )
( D18 GND )
( D19 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP )
( D20 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM )
( D21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE )
( D22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12 )
( E1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9 )
( E2 GND )
( E3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8 )
( E4 ? )
( E5 ? )
( E6 ? )
( E7 GND )
( E8 ? )
( E9 +3.3V )
( E10 ? )
( E11 GND )
( E12 ? )
( E13 +3.3V )
( E14 ? )
( E15 GND )
( E16 ? )
( E17 +3.3V )
( E18 /DBG_PRG/FPGA_TDI )
( E19 +2.5V )
( E20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7 )
( E21 GND )
( E22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2 )
( F1 ? )
( F2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE# )
( F3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4 )
( F4 +2.5V )
( F5 ? )
( F6 +2.5V )
( F7 ? )
( F8 ? )
( F9 ? )
( F10 ? )
( F11 +2.5V )
( F12 ? )
( F13 ? )
( F14 ? )
( F15 ? )
( F16 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD )
( F17 /USB/USBA_RCV )
( F18 ? )
( F19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11 )
( F20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4 )
( F21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0 )
( F22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1 )
( G1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1 )
( G2 +2.5V )
( G3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0 )
( G4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10 )
( G5 GND )
( G6 ? )
( G7 ? )
( G8 ? )
( G9 ? )
( G10 +3.3V )
( G11 ? )
( G12 +2.5V )
( G13 ? )
( G14 +3.3V )
( G15 /DBG_PRG/FPGA_TCK )
( G16 ? )
( G17 ? )
( G18 GND )
( G19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10 )
( G20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3 )
( G21 +2.5V )
( G22 ? )
( H1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1 )
( H2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0 )
( H3 /DDR_Banks/M0_CLK# )
( H4 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK )
( H5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2 )
( H6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7 )
( H7 GND )
( H8 ? )
( H9 +2.5V )
( H10 ? )
( H11 ? )
( H12 ? )
( H13 ? )
( H14 ? )
( H15 +2.5V )
( H16 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS# )
( H17 ? )
( H18 ? )
( H19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE# )
( H20 /DDR_Banks/M1_CLK )
( H21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS# )
( H22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS# )
( J1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5 )
( J2 GND )
( J3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4 )
( J4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6 )
( J5 +2.5V )
( J6 ? )
( J7 ? )
( J8 +1.2V )
( J9 GND )
( J10 +1.2V )
( J11 GND )
( J12 +1.2V )
( J13 GND )
( J14 +1.2V )
( J15 GND )
( J16 ? )
( J17 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0 )
( J18 +2.5V )
( J19 /DDR_Banks/M1_CLK# )
( J20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4 )
( J21 GND )
( J22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5 )
( K1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7 )
( K2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6 )
( K3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5 )
( K4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS# )
( K5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS# )
( K6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3 )
( K7 ? )
( K8 ? )
( K9 +1.2V )
( K10 GND )
( K11 +1.2V )
( K12 GND )
( K13 +1.2V )
( K14 GND )
( K15 +2.5V )
( K16 ? )
( K17 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1 )
( K18 ? )
( K19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6 )
( K20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5 )
( K21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6 )
( K22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7 )
( L1 ? )
( L2 +2.5V )
( L3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS )
( L4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM )
( L5 GND )
( L6 ? )
( L7 +2.5V )
( L8 +2.5V )
( L9 GND )
( L10 +1.2V )
( L11 GND )
( L12 +1.2V )
( L13 GND )
( L14 +1.2V )
( L15 ? )
( L16 +2.5V )
( L17 ? )
( L18 GND )
( L19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM )
( L20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS )
( L21 +2.5V )
( L22 ? )
( M1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3 )
( M2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2 )
( M3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM )
( M4 ? )
( M5 ? )
( M6 ? )
( M7 ? )
( M8 ? )
( M9 +1.2V )
( M10 GND )
( M11 +1.2V )
( M12 GND )
( M13 +1.2V )
( M14 GND )
( M15 +2.5V )
( M16 ? )
( M17 ? )
( M18 ? )
( M19 ? )
( M20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM )
( M21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2 )
( M22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3 )
( N1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1 )
( N2 GND )
( N3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0 )
( N4 ? )
( N5 +2.5V )
( N6 ? )
( N7 ? )
( N8 +2.5V )
( N9 GND )
( N10 +1.2V )
( N11 GND )
( N12 +1.2V )
( N13 GND )
( N14 +1.2V )
( N15 GND )
( N16 ? )
( N17 GND )
( N18 +2.5V )
( N19 ? )
( N20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0 )
( N21 GND )
( N22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1 )
( P1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9 )
( P2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8 )
( P3 ? )
( P4 ? )
( P5 ? )
( P6 ? )
( P7 ? )
( P8 ? )
( P9 +1.2V )
( P10 GND )
( P11 +1.2V )
( P12 GND )
( P13 +1.2V )
( P14 GND )
( P15 ? )
( P16 ? )
( P17 ? )
( P18 ? )
( P19 ? )
( P20 ? )
( P21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8 )
( P22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9 )
( R1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11 )
( R2 +2.5V )
( R3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10 )
( R4 ? )
( R5 GND )
( R6 +2.5V )
( R7 ? )
( R8 ? )
( R9 ? )
( R10 +2.5V )
( R11 ? )
( R12 +2.5V )
( R13 ? )
( R14 +1.2V )
( R15 ? )
( R16 ? )
( R17 ? )
( R18 GND )
( R19 ? )
( R20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10 )
( R21 +2.5V )
( R22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11 )
( T1 ? )
( T2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS )
( T3 ? )
( T4 ? )
( T5 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO )
( T6 ? )
( T7 ? )
( T8 ? )
( T9 VCCO2 )
( T10 ? )
( T11 ? )
( T12 ? )
( T13 VCCO2 )
( T14 ? )
( T15 ? )
( T16 ? )
( T17 ? )
( T18 ? )
( T19 ? )
( T20 ? )
( T21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS )
( T22 ? )
( U1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13 )
( U2 GND )
( U3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12 )
( U4 ? )
( U5 +2.5V )
( U6 ? )
( U7 GND )
( U8 ? )
( U9 ? )
( U10 ? )
( U11 +2.5V )
( U12 ? )
( U13 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3 )
( U14 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 )
( U15 ? )
( U16 ? )
( U17 ? )
( U18 +2.5V )
( U19 ? )
( U20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12 )
( U21 GND )
( U22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13 )
( V1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15 )
( V2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14 )
( V3 ? )
( V4 GND )
( V5 ? )
( V6 +2.5V )
( V7 ? )
( V8 VCCO2 )
( V9 ? )
( V10 GND )
( V11 ? )
( V12 VCCO2 )
( V13 ? )
( V14 GND )
( V15 ? )
( V16 VCCO2 )
( V17 ? )
( V18 ? )
( V19 ? )
( V20 ? )
( V21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14 )
( V22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15 )
( W1 ? )
( W2 +2.5V )
( W3 ? )
( W4 ? )
( W5 VCCO2 )
( W6 ? )
( W7 GND )
( W8 ? )
( W9 ? )
( W10 ? )
( W11 ? )
( W12 /Image_Sensor/IS_EXTCLK )
( W13 ? )
( W14 ? )
( W15 ? )
( W16 GND )
( W17 ? )
( W18 ? )
( W19 GND )
( W20 ? )
( W21 +2.5V )
( W22 ? )
( Y1 ? )
( Y2 ? )
( Y3 /Image_Sensor/IS_TRIGGER )
( Y4 /FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N )
( Y5 /FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY )
( Y6 /Image_Sensor/IS_DOUT10 )
( Y7 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9 )
( Y8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT6 )
( Y9 ? )
( Y10 ? )
( Y11 ? )
( Y12 /FPGA,_Port0,_Port2,_PROG_IF/IS_SCL )
( Y13 ? )
( Y14 ? )
( Y15 ? )
( Y16 ? )
( Y17 ? )
( Y18 ? )
( Y19 ? )
( Y20 +3.3V )
( Y21 ? )
( Y22 N-000395 )
)
( /4C7BC2A2/4C6B216E 0402 R23 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM )
)
( /4C7BC2A2/4C6B216D 0402 R22 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS )
( 2 /DDR_Banks/M0_UDQS )
)
( /4C7BC2A2/4C6B216B 0402 R24 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE )
( 2 /DDR_Banks/M0_CKE )
)
( /4C7BC2A2/4C6B1B90 0402 R21 120 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK )
( 2 /DDR_Banks/M0_CLK# )
)
( /4C7BC2A2/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A3 )
( 6 /DDR_Banks/M0_A2 )
( 7 /DDR_Banks/M0_A1 )
( 8 /DDR_Banks/M0_A0 )
)
( /4C7BC2A2/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS# )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10 )
( 5 /DDR_Banks/M0_A10 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1 )
( 7 /DDR_Banks/M0_BA0 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# )
)
( /4C7BC2A2/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE# )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS# )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# )
( 6 /DDR_Banks/M0_WE# )
( 7 /DDR_Banks/M0_LDM )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS )
)
( /4C7BC2A2/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A4 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A5 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A6 )
( 8 /DDR_Banks/M0_A7 )
)
( /4C7BC2A2/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A8 )
( 6 /DDR_Banks/M0_A9 )
( 7 /DDR_Banks/M0_A11 )
( 8 /DDR_Banks/M0_A12 )
)
( /4C7BC2A2/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7 )
( 6 /DDR_Banks/M0_DQ6 )
( 7 /DDR_Banks/M0_DQ5 )
( 8 /DDR_Banks/M0_DQ4 )
)
( /4C7BC2A2/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 )
( 6 /DDR_Banks/M0_DQ2 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0 )
)
( /4C7BC2A2/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11 )
( 5 /DDR_Banks/M0_DQ11 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 )
( 8 /DDR_Banks/M0_DQ8 )
)
( /4C7BC2A2/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15 )
( 5 /DDR_Banks/M0_DQ15 )
( 6 /DDR_Banks/M0_DQ14 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13 )
( 8 /DDR_Banks/M0_DQ12 )
)
( /4C7BC2A2/4C69E7DD 0402 R19 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS )
( 2 /DDR_Banks/M1_UDQS )
)
( /4C7BC2A2/4C69E92D 0402 R20 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS# )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CS# )
)
( /4C7BC2A2/4C69E7F8 0402 R17 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE )
( 2 /DDR_Banks/M1_CKE )
)
( /4C7BC2A2/4C69E7C2 0402 R18 33 {Lib=R}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM )
)
( /4C7BC2A2/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11 )
)
( /4C7BC2A2/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4}
( 1 /DDR_Banks/M1_DQ15 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14 )
( 3 /DDR_Banks/M1_DQ13 )
( 4 /DDR_Banks/M1_DQ12 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15 )
)
( /4C7BC2A2/4C69DF7A 0402 R16 120 {Lib=R}
( 1 /DDR_Banks/M1_CLK# )
( 2 /DDR_Banks/M1_CLK )
)
( /4C7BC2A2/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4}
( 1 /DDR_Banks/M1_A12 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A11 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12 )
)
( /4C7BC2A2/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A7 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A6 )
( 3 /DDR_Banks/M1_A5 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A4 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6 )
( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7 )
)
( /4C7BC2A2/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3 )
( 5 /DDR_Banks/M1_DQ3 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1 )
( 8 /DDR_Banks/M1_DQ0 )
)
( /4C7BC2A2/4C69D3A4 $noname RP3 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE# )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS# )
( 5 /DDR_Banks/M1_CAS# )
( 6 /DDR_Banks/M1_WE# )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM )
( 8 /DDR_Banks/M1_LDQS )
)
( /4C7BC2A2/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 )
( 8 /DDR_Banks/M1_DQ4 )
)
( /4C7BC2A2/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS# )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10 )
( 5 /DDR_Banks/M1_A10 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1 )
( 7 /DDR_Banks/M1_BA0 )
( 8 /DDR_Banks/M1_RAS# )
)
( /4C7BC2A2/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0 )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1 )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2 )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3 )
( 5 /DDR_Banks/M1_A3 )
( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 )
( 7 /DDR_Banks/M1_A1 )
( 8 /DDR_Banks/M1_A0 )
)
( /4C716A4D/4C716CAB $noname J6 CONN_8X2 {Lib=CONN_8X2}
( 1 /DBG_PRG/FPGA_TCK )
( 2 ? )
( 3 /DBG_PRG/FPGA_TMS )
( 4 ? )
( 5 /DBG_PRG/FPGA_TDO )
( 6 ? )
( 7 /DBG_PRG/FPGA_TDI )
( 8 ? )
( 9 ? )
( 10 ? )
( 11 ? )
( 12 ? )
( 13 ? )
( 14 ? )
( 15 ? )
( 16 ? )
)
( /4C69ED5F/4C7FD562 $noname P1 AVR/PROG {Lib=CONN_4}
( 1 GND )
( 2 /PSU/AVR_SCK )
( 3 /PSU/AVR_MISO )
( 4 /PSU/AVR_MOSI )
)
( /4C69ED5F/4C7FD266 0402 C104 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C69ED5F/4C7FD244 $noname R57 15K {Lib=R}
( 1 /PSU/AVR_RST )
( 2 +3.3V )
)
( /4C69ED5F/4C7FC13A $noname R56 R {Lib=R}
( 1 /PSU/3.3V_EN )
( 2 /PSU/VIN_DC-DC-3.3 )
)
( /4C69ED5F/4C7FC041 $noname R58 1M {Lib=R}
( 1 /PSU/1.2V_EN )
( 2 /PSU/VIN_DC-DC-1.2 )
)
( /4C69ED5F/4C7D02E3 MLP6 U17 FAN4010 {Lib=FAN4010}
( 1 +BATT )
( 2 ? )
( 3 /PSU/lout_2.5 )
( 5 GND )
( 6 ? )
)
( /4C69ED5F/4C7D02E2 1206 R45 R {Lib=R}
( 1 /PSU/VIN_DC-DC-2.5 )
( 2 +BATT )
)
( /4C69ED5F/4C7D02E1 0402 R44 R {Lib=R}
( 1 /PSU/lout_2.5 )
( 2 GND )
)
( /4C69ED5F/4C7C4DAA $noname R41 160K {Lib=R}
( 1 /PSU/2.5V_EN )
( 2 GND )
)
( /4C69ED5F/4C7C4D9E $noname R40 47K {Lib=R}
( 1 N-000219 )
( 2 N-000214 )
)
( /4C69ED5F/4C7C4D94 $noname C100 220pF {Lib=C}
( 1 N-000214 )
( 2 GND )
)
( /4C69ED5F/4C7C4D8E $noname C99 22uF {Lib=C}
( 1 /PSU/VIN_DC-DC-2.5 )
( 2 GND )
)
( /4C69ED5F/4C7C4CF1 0402 C103 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C69ED5F/4C7C4CF0 1210 L11 2.2uH {Lib=INDUCTOR}
( 1 +2.5V )
( 2 /PSU/SW_2.5 )
)
( /4C69ED5F/4C7C4CEF 0402 R43 51K {Lib=R}
( 1 +2.5V )
( 2 /PSU/VFB2.5 )
)
( /4C69ED5F/4C7C4CEE 0402 R42 24K {Lib=R}
( 1 /PSU/VFB2.5 )
( 2 GND )
)
( /4C69ED5F/4C7C4CED 1206 C102 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C69ED5F/4C7C4CEC 0402 C101 22pF {Lib=CAP}
( 1 +2.5V )
( 2 /PSU/VFB2.5 )
)
( /4C69ED5F/4C79C99E 0805 C95 4.7uF {Lib=CAP}
( 1 /PSU/VIN_DC-DC-5.0 )
( 2 GND )
)
( /4C69ED5F/4C79C99C 0402 R35 R {Lib=R}
( 1 /PSU/lout_5.0 )
( 2 GND )
)
( /4C69ED5F/4C79C99B 1206 R36 R {Lib=R}
( 1 /PSU/VIN_DC-DC-5.0 )
( 2 +BATT )
)
( /4C69ED5F/4C79C99A MLP6 U16 FAN4010 {Lib=FAN4010}
( 1 +BATT )
( 2 ? )
( 3 /PSU/lout_5.0 )
( 5 GND )
( 6 ? )
)
( /4C69ED5F/4C79C8B2 0402 C98 100nF {Lib=CAP}
( 1 +5V )
( 2 GND )
)
( /4C69ED5F/4C79C8B1 0402 R39 1.02M {Lib=R}
( 1 +5V )
( 2 /PSU/VFB5.0 )
)
( /4C69ED5F/4C79C8B0 0402 R38 332K {Lib=R}
( 1 /PSU/VFB5.0 )
( 2 GND )
)
( /4C69ED5F/4C79C8AF 1206 C97 10uF {Lib=CAP}
( 1 +5V )
( 2 GND )
)
( /4C69ED5F/4C79C8AE 0402 C96 22pF {Lib=CAP}
( 1 +5V )
( 2 /PSU/VFB5.0 )
)
( /4C69ED5F/4C79C828 1210 L10 4.7uH {Lib=INDUCTOR}
( 1 N-000205 )
( 2 /PSU/VIN_DC-DC-5.0 )
)
( /4C69ED5F/4C79C7C0 0402 R37 1M {Lib=R}
( 1 /PSU/5V_EN )
( 2 /PSU/VIN_DC-DC-5.0 )
)
( /4C69ED5F/4C79C65B SOT23_6 U15 A7117 {Lib=A7117}
( 1 N-000205 )
( 2 GND )
( 3 /PSU/VFB5.0 )
( 4 /PSU/5V_EN )
( 5 +5V )
( 6 /PSU/VIN_DC-DC-5.0 )
)
( /4C69ED5F/4C770714 MLP6 U14 FAN4010 {Lib=FAN4010}
( 1 +BATT )
( 2 ? )
( 3 /PSU/Iout_1.2 )
( 5 GND )
( 6 ? )
)
( /4C69ED5F/4C770713 1206 R34 R {Lib=R}
( 1 /PSU/VIN_DC-DC-1.2 )
( 2 +BATT )
)
( /4C69ED5F/4C770712 0402 R33 R {Lib=R}
( 1 /PSU/Iout_1.2 )
( 2 GND )
)
( /4C69ED5F/4C77067B 0402 R31 R {Lib=R}
( 1 /PSU/lout_3.3 )
( 2 GND )
)
( /4C69ED5F/4C77060E 1206 R32 R {Lib=R}
( 1 /PSU/VIN_DC-DC-3.3 )
( 2 +BATT )
)
( /4C69ED5F/4C7705B0 MLP6 U13 FAN4010 {Lib=FAN4010}
( 1 +BATT )
( 2 ? )
( 3 /PSU/lout_3.3 )
( 5 GND )
( 6 ? )
)
( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF {Lib=CAP}
( 1 /PSU/VIN_DC-DC-1.2 )
( 2 GND )
)
( /4C69ED5F/4C6D2FD6 0402 C83 22pF {Lib=CAP}
( 1 +1.2V )
( 2 /PSU/VFB1.2 )
)
( /4C69ED5F/4C6D2FD5 1206 C84 10uF {Lib=CAP}
( 1 +1.2V )
( 2 GND )
)
( /4C69ED5F/4C6D2FD3 0402 R27 200K {Lib=R}
( 1 /PSU/VFB1.2 )
( 2 GND )
)
( /4C69ED5F/4C6D2FD2 0402 R28 200K {Lib=R}
( 1 +1.2V )
( 2 /PSU/VFB1.2 )
)
( /4C69ED5F/4C6D2FD1 1210 L9 2.2uH {Lib=INDUCTOR}
( 1 +1.2V )
( 2 /PSU/SW_1.2 )
)
( /4C69ED5F/4C6D2FD0 0402 C85 100nF {Lib=CAP}
( 1 +1.2V )
( 2 GND )
)
( /4C69ED5F/4C6D2F0B 0402 C81 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C69ED5F/4C6D2E6A 1210 L8 2.2uH {Lib=INDUCTOR}
( 1 +3.3V )
( 2 /PSU/SW_3.3 )
)
( /4C69ED5F/4C6D2DDD 0402 R26 900K {Lib=R}
( 1 +3.3V )
( 2 /PSU/VFB3.3 )
)
( /4C69ED5F/4C6D2DBC 0402 R25 200K {Lib=R}
( 1 /PSU/VFB3.3 )
( 2 GND )
)
( /4C69ED5F/4C6D2C83 1206 C80 10uF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C69ED5F/4C6D2C7F 0402 C79 22pF {Lib=CAP}
( 1 +3.3V )
( 2 /PSU/VFB3.3 )
)
( /4C69ED5F/4C6D2C7C 0805 C78 4.7uF {Lib=CAP}
( 1 /PSU/VIN_DC-DC-3.3 )
( 2 GND )
)
( /4C69ED5F/4C6D2AE0 SOT23-5 U12 A7108 {Lib=A7108}
( 1 /PSU/1.2V_EN )
( 2 GND )
( 3 /PSU/SW_1.2 )
( 4 /PSU/VIN_DC-DC-1.2 )
( 5 /PSU/VFB1.2 )
)
( /4C69ED5F/4C6D2AA5 SOT23-5 U11 A7108 {Lib=A7108}
( 1 /PSU/3.3V_EN )
( 2 GND )
( 3 /PSU/SW_3.3 )
( 4 /PSU/VIN_DC-DC-3.3 )
( 5 /PSU/VFB3.3 )
)
( /4C69ED5F/4C6C9DB9 DFN10 U10 A7130 {Lib=A7130}
( 1 /PSU/2.5V_EN )
( 2 GND )
( 3 /PSU/SW_2.5 )
( 4 /PSU/SW_2.5 )
( 5 GND )
( 6 /PSU/VIN_DC-DC-2.5 )
( 7 /PSU/VIN_DC-DC-2.5 )
( 8 /PSU/VIN_DC-DC-2.5 )
( 9 /PSU/VFB2.5 )
( 10 N-000219 )
( PAD GND )
)
( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF}
( 1 /PSU/AVR_SCK )
( 2 /PSU/Iout_1.2 )
( 3 /PSU/1.2V_EN )
( 4 /PSU/lout_3.3 )
( 5 /PSU/3.3V_EN )
( 6 ? )
( 7 ? )
( 8 GND )
( 9 +3.3V )
( 10 ? )
( 11 /PSU/lout_2.5 )
( 12 /PSU/2.5V_EN )
( 13 /PSU/AVR_RST )
( 14 /PSU/lout_5.0 )
( 15 /PSU/5V_EN )
( 16 /PSU/AVR_MOSI )
( 17 ? )
( 18 ? )
( 19 ? )
( 20 /PSU/AVR_MISO )
( PAD GND )
)
( /4C4227FE/4C6969AB $noname C75 100nF {Lib=C}
( 1 GND )
( 2 +3.3V )
)
( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D67C 0402 C73 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65D661 0402 C72 100nF {Lib=CAP}
( 1 +3.3V )
( 2 GND )
)
( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB}
( 1 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO )
( 2 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 )
( 3 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 )
( 4 GND )
( 5 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0 )
( 6 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK )
( 7 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3 )
( 8 VCCO2 )
)
( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD}
( 1 /Non_volatile_memories/SD_DAT2 )
( 2 /Non_volatile_memories/SD_DAT3 )
( 3 /FPGA,_Port0,_Port2,_PROG_IF/SD_CMD )
( 4 +3.3V )
( 5 /FPGA,_Port0,_Port2,_PROG_IF/SD_CLK )
( 6 GND )
( 7 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0 )
( 8 /Non_volatile_memories/SD_DAT1 )
( CASE GND )
( CD ? )
( COM GND )
)
( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M}
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB )
( 7 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB )
( 8 /Non_volatile_memories/NF_RE_N )
( 9 /FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N )
( 10 ? )
( 11 ? )
( 12 +3.3V )
( 13 GND )
( 14 ? )
( 15 ? )
( 16 /FPGA,_Port0,_Port2,_PROG_IF/NF_CLE )
( 17 /FPGA,_Port0,_Port2,_PROG_IF/NF_ALE )
( 18 /FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N )
( 19 +3.3V )
( 20 ? )
( 21 ? )
( 22 ? )
( 23 ? )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 ? )
( 29 /FPGA,_Port0,_Port2,_PROG_IF/NF_D0 )
( 30 /FPGA,_Port0,_Port2,_PROG_IF/NF_D1 )
( 31 /Non_volatile_memories/NF_D2 )
( 32 /Non_volatile_memories/NF_D3 )
( 33 ? )
( 34 ? )
( 35 ? )
( 36 GND )
( 37 +3.3V )
( 38 ? )
( 39 ? )
( 40 ? )
( 41 /Non_volatile_memories/NF_D4 )
( 42 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 )
( 43 /FPGA,_Port0,_Port2,_PROG_IF/NF_D6 )
( 44 /FPGA,_Port0,_Port2,_PROG_IF/NF_D7 )
( 45 ? )
( 46 ? )
( 47 ? )
( 48 ? )
)
( /4C5F1EDC/4C7D3661 $noname R53 15k {Lib=R}
( 1 GND )
( 2 /USB/USBD_D+ )
)
( /4C5F1EDC/4C7D3660 $noname R54 15k {Lib=R}
( 1 GND )
( 2 /USB/USBD_D- )
)
( /4C5F1EDC/4C7D365F $noname R55 15k {Lib=R}
( 1 +3.3V )
( 2 /USB/USBD_D+ )
)
( /4C5F1EDC/4C7D354D $noname R49 24 {Lib=R}
( 1 /USB/USBD_D+ )
( 2 N-000189 )
)
( /4C5F1EDC/4C7D354C $noname R50 24 {Lib=R}
( 1 /USB/USBD_D- )
( 2 N-000198 )
)
( /4C5F1EDC/4C7D350E $noname R52 24 {Lib=R}
( 1 /USB/USBA_D- )
( 2 N-000188 )
)
( /4C5F1EDC/4C7D3508 $noname R51 24 {Lib=R}
( 1 /USB/USBA_D+ )
( 2 N-000197 )
)
( /4C5F1EDC/4C7D32A3 $noname R48 15k {Lib=R}
( 1 +3.3V )
( 2 /USB/USBA_D+ )
)
( /4C5F1EDC/4C7D3098 $noname R47 15k {Lib=R}
( 1 GND )
( 2 /USB/USBA_D+ )
)
( /4C5F1EDC/4C7D3075 $noname R46 15k {Lib=R}
( 1 GND )
( 2 /USB/USBA_D- )
)
( /4C5F1EDC/4C75F027 ZX62D-B-5P8 J7 ZX62D-B-5P8 {Lib=ZX62D-B-5P8}
( 1 N-000195 )
( 2 /USB/USBD_D- )
( 3 /USB/USBD_D+ )
( 4 N-000190 )
( 5 N-000190 )
( 6 /USB/USB_CASE_DEV )
( 7 /USB/USB_CASE_DEV )
( 8 /USB/USB_CASE_DEV )
( 9 /USB/USB_CASE_DEV )
)
( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF {Lib=MIC2550-MLF}
( 1 /USB/USBD_SPD )
( 2 /USB/USBD_RCV )
( 3 /USB/USBD_VP )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM )
( 6 GND )
( 7 GND )
( 9 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N )
( 10 N-000198 )
( 11 N-000189 )
( 12 +3.3V )
( 14 +3.3V )
( 15 +2.5V )
)
( /4C5F1EDC/4C71BA1D MLF16 U6 MIC2550-MLF {Lib=MIC2550-MLF}
( 1 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD )
( 2 /USB/USBA_RCV )
( 3 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM )
( 6 GND )
( 7 GND )
( 9 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N )
( 10 N-000188 )
( 11 N-000197 )
( 12 +3.3V )
( 14 +3.3V )
( 15 +2.5V )
)
( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BD 0402 C36 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C6552BC 0402 C37 100nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03}
( 1 /USB/USBD_D- )
( 2 GND )
)
( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03}
( 1 /USB/USBD_D+ )
( 2 GND )
)
( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C}
( 1 /USB/USB_CASE_DEV )
( 2 GND )
)
( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R}
( 1 /USB/USB_CASE_DEV )
( 2 GND )
)
( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR}
( 1 N-000195 )
( 2 GND )
)
( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR}
( 1 N-000193 )
( 2 N-000192 )
)
( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR}
( 1 N-000191 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R}
( 1 /USB/USB_CASE_HOST )
( 2 GND )
)
( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C}
( 1 /USB/USB_CASE_HOST )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 {Lib=V0402MHS03}
( 1 /USB/USBA_D+ )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 {Lib=V0402MHS03}
( 1 /USB/USBA_D- )
( 2 GND )
)
( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F}
( 1 N-000193 )
( 2 +5V )
)
( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001}
( 1 N-000192 )
( 2 /USB/USBA_D- )
( 3 /USB/USBA_D+ )
( 4 N-000191 )
( S1 /USB/USB_CASE_HOST )
( S2 /USB/USB_CASE_HOST )
( S3 /USB/USB_CASE_HOST )
( S4 /USB/USB_CASE_HOST )
)
( /4C5F1EDC/4C5F2039 $noname C15 100nF {Lib=C}
( 1 +2.5V )
( 2 GND )
)
( /4C5F1EDC/4C5F2037 0402 C14 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D8114 $noname C9 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_PLL1.8V )
( 2 GND )
)
( /4C4320F3/4C5D810A 0402 L3 FB {Lib=INDUCTOR}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 /Ethernet_Phy/ETH_PLL1.8V )
)
( /4C4320F3/4C5D8104 $noname C6 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 GND )
)
( /4C4320F3/4C5D80F3 0402 L1 FB {Lib=INDUCTOR}
( 1 +1.8V )
( 2 /Ethernet_Phy/ETH_A1.8V )
)
( /4C4320F3/4C5D80F0 $noname C4 100nF {Lib=C}
( 1 +1.8V )
( 2 GND )
)
( /4C4320F3/4C5D80ED $noname C2 1uF {Lib=C}
( 1 +1.8V )
( 2 GND )
)
( /4C4320F3/4C5D7FB7 0402 L2 FB {Lib=INDUCTOR}
( 1 +3.3V )
( 2 /Ethernet_Phy/ETH_A3.3V )
)
( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R}
( 1 /Ethernet_Phy/ETH_MDIO )
( 2 +3.3V )
)
( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R}
( 1 N-000167 )
( 2 GND )
)
( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C}
( 1 +3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C}
( 1 /Ethernet_Phy/MAG_SHIELD )
( 2 GND )
)
( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R}
( 1 /Ethernet_Phy/MAG_SHIELD )
( 2 GND )
)
( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001}
( 1 /Ethernet_Phy/ETH_MDIO )
( 2 /Ethernet_Phy/ETH_MDC )
( 3 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3 )
( 4 /Ethernet_Phy/ETH_RXD2 )
( 5 /Ethernet_Phy/ETH_RXD1 )
( 6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 )
( 7 +3.3V )
( 8 GND )
( 9 /Ethernet_Phy/ETH_RXDV )
( 10 /Ethernet_Phy/ETH_RXC )
( 11 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER )
( 12 GND )
( 13 +1.8V )
( 14 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER )
( 15 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC )
( 16 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN )
( 17 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 )
( 18 /Ethernet_Phy/ETH_TXD1 )
( 19 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 )
( 20 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 )
( 21 /Ethernet_Phy/ETH_COL )
( 22 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS )
( 23 GND )
( 24 +3.3V )
( 25 /Ethernet_Phy/ETH_INT )
( 26 /Ethernet_Phy/ETH_LED0 )
( 27 /Ethernet_Phy/ETH_LED1 )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 /Ethernet_Phy/ETH_A1.8V )
( 32 /Ethernet_Phy/MAG_RX- )
( 33 /Ethernet_Phy/MAG_RX+ )
( 34 ? )
( 35 GND )
( 36 GND )
( 37 N-000167 )
( 38 /Ethernet_Phy/ETH_A3.3V )
( 39 GND )
( 40 /Ethernet_Phy/MAG_TX- )
( 41 /Ethernet_Phy/MAG_TX+ )
( 42 ? )
( 43 ? )
( 44 GND )
( 45 ? )
( 46 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK )
( 47 /Ethernet_Phy/ETH_PLL1.8V )
( 48 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N )
)
( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R}
( 1 +3.3V )
( 2 /Ethernet_Phy/MAG_TX+ )
)
( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R}
( 1 +3.3V )
( 2 /Ethernet_Phy/MAG_TX- )
)
( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R}
( 1 +3.3V )
( 2 /Ethernet_Phy/MAG_RX- )
)
( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R}
( 1 +3.3V )
( 2 /Ethernet_Phy/MAG_RX+ )
)
( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R}
( 1 N-000180 )
( 2 /Ethernet_Phy/ETH_LED1 )
)
( /4C4320F3/4C5D719D $noname R7 220 {Lib=R}
( 1 N-000179 )
( 2 /Ethernet_Phy/ETH_LED0 )
)
( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025}
( 1 /Ethernet_Phy/MAG_TX+ )
( 2 /Ethernet_Phy/MAG_TX- )
( 3 +3.3V )
( 4 GND )
( 5 GND )
( 6 +3.3V )
( 7 /Ethernet_Phy/MAG_RX+ )
( 8 /Ethernet_Phy/MAG_RX- )
( 9 +3.3V )
( 10 N-000179 )
( 11 +3.3V )
( 12 N-000180 )
( 13 /Ethernet_Phy/MAG_SHIELD )
( 14 /Ethernet_Phy/MAG_SHIELD )
)
( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /DDR_Banks/M1_DQ0 )
( 3 +2.5V )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1 )
( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2 )
( 6 GND )
( 7 /DDR_Banks/M1_DQ3 )
( 8 /DDR_Banks/M1_DQ4 )
( 9 +2.5V )
( 10 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 )
( 11 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 )
( 12 GND )
( 13 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /DDR_Banks/M1_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM )
( 21 /DDR_Banks/M1_WE# )
( 22 /DDR_Banks/M1_CAS# )
( 23 /DDR_Banks/M1_RAS# )
( 24 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CS# )
( 25 ? )
( 26 /DDR_Banks/M1_BA0 )
( 27 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1 )
( 28 /DDR_Banks/M1_A10 )
( 29 /DDR_Banks/M1_A0 )
( 30 /DDR_Banks/M1_A1 )
( 31 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 )
( 32 /DDR_Banks/M1_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A4 )
( 36 /DDR_Banks/M1_A5 )
( 37 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A6 )
( 38 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A7 )
( 39 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 )
( 40 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 )
( 41 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A11 )
( 42 /DDR_Banks/M1_A12 )
( 43 ? )
( 44 /DDR_Banks/M1_CLK# )
( 45 /DDR_Banks/M1_CKE )
( 46 /DDR_Banks/M1_CLK )
( 47 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM )
( 48 GND )
( 49 /DDR_Banks/M1_VREF )
( 50 ? )
( 51 /DDR_Banks/M1_UDQS )
( 52 GND )
( 53 ? )
( 54 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 )
( 55 +2.5V )
( 56 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9 )
( 57 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10 )
( 58 GND )
( 59 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 )
( 60 /DDR_Banks/M1_DQ12 )
( 61 +2.5V )
( 62 /DDR_Banks/M1_DQ13 )
( 63 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14 )
( 64 GND )
( 65 /DDR_Banks/M1_DQ15 )
( 66 GND )
)
( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D151 1206 C33 10uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R}
( 1 +2.5V )
( 2 /DDR_Banks/M1_VREF )
)
( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R}
( 1 /DDR_Banks/M1_VREF )
( 2 GND )
)
( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R}
( 1 /DDR_Banks/M0_VREF )
( 2 GND )
)
( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R}
( 1 +2.5V )
( 2 /DDR_Banks/M0_VREF )
)
( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP}
( 1 +2.5V )
( 2 /DDR_Banks/M1_VREF )
)
( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP}
( 1 /DDR_Banks/M1_VREF )
( 2 GND )
)
( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP}
( 1 /DDR_Banks/M0_VREF )
( 2 GND )
)
( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP}
( 1 +2.5V )
( 2 /DDR_Banks/M0_VREF )
)
( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0 )
( 3 +2.5V )
( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1 )
( 5 /DDR_Banks/M0_DQ2 )
( 6 GND )
( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 )
( 8 /DDR_Banks/M0_DQ4 )
( 9 +2.5V )
( 10 /DDR_Banks/M0_DQ5 )
( 11 /DDR_Banks/M0_DQ6 )
( 12 GND )
( 13 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /DDR_Banks/M0_LDM )
( 21 /DDR_Banks/M0_WE# )
( 22 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# )
( 23 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# )
( 24 GND )
( 25 ? )
( 26 /DDR_Banks/M0_BA0 )
( 27 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1 )
( 28 /DDR_Banks/M0_A10 )
( 29 /DDR_Banks/M0_A0 )
( 30 /DDR_Banks/M0_A1 )
( 31 /DDR_Banks/M0_A2 )
( 32 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A4 )
( 36 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A5 )
( 37 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A6 )
( 38 /DDR_Banks/M0_A7 )
( 39 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A8 )
( 40 /DDR_Banks/M0_A9 )
( 41 /DDR_Banks/M0_A11 )
( 42 /DDR_Banks/M0_A12 )
( 43 ? )
( 44 /DDR_Banks/M0_CLK# )
( 45 /DDR_Banks/M0_CKE )
( 46 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK )
( 47 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM )
( 48 GND )
( 49 /DDR_Banks/M0_VREF )
( 50 ? )
( 51 /DDR_Banks/M0_UDQS )
( 52 GND )
( 53 ? )
( 54 /DDR_Banks/M0_DQ8 )
( 55 +2.5V )
( 56 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 )
( 57 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10 )
( 58 GND )
( 59 /DDR_Banks/M0_DQ11 )
( 60 /DDR_Banks/M0_DQ12 )
( 61 +2.5V )
( 62 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13 )
( 63 /DDR_Banks/M0_DQ14 )
( 64 GND )
( 65 /DDR_Banks/M0_DQ15 )
( 66 GND )
)
)
*
{ Allowed footprints by component:
$component C140
SM*
C?
C1-1
$endlist
$component C142
SM*
C?
C1-1
$endlist
$component C144
CP*
SM*
$endlist
$component C143
SM*
C?
C1-1
$endlist
$component C141
SM*
C?
C1-1
$endlist
$component C136
SM*
C?
C1-1
$endlist
$component C138
SM*
C?
C1-1
$endlist
$component C139
CP*
SM*
$endlist
$component C137
SM*
C?
C1-1
$endlist
$component C133
SM*
C?
C1-1
$endlist
$component C135
CP*
SM*
$endlist
$component C134
SM*
C?
C1-1
$endlist
$component C131
SM*
C?
C1-1
$endlist
$component C132
CP*
SM*
$endlist
$component C130
CP*
SM*
$endlist
$component C129
SM*
C?
C1-1
$endlist
$component C107
CP*
SM*
$endlist
$component C110
SM*
C?
C1-1
$endlist
$component R64
R?
SM0603
SM0805
R?-*
$endlist
$component R63
R?
SM0603
SM0805
R?-*
$endlist
$component C116
CP*
SM*
$endlist
$component C113
SM*
C?
C1-1
$endlist
$component C125
SM*
C?
C1-1
$endlist
$component C128
CP*
SM*
$endlist
$component R67
R?
SM0603
SM0805
R?-*
$endlist
$component R68
R?
SM0603
SM0805
R?-*
$endlist
$component C121
SM*
C?
C1-1
$endlist
$component C118
CP*
SM*
$endlist
$component C117
CP*
SM*
$endlist
$component C120
SM*
C?
C1-1
$endlist
$component R66
R?
SM0603
SM0805
R?-*
$endlist
$component R65
R?
SM0603
SM0805
R?-*
$endlist
$component C127
CP*
SM*
$endlist
$component C124
SM*
C?
C1-1
$endlist
$component C112
SM*
C?
C1-1
$endlist
$component C115
CP*
SM*
$endlist
$component R61
R?
SM0603
SM0805
R?-*
$endlist
$component R62
R?
SM0603
SM0805
R?-*
$endlist
$component C109
SM*
C?
C1-1
$endlist
$component C106
CP*
SM*
$endlist
$component C105
CP*
SM*
$endlist
$component C108
SM*
C?
C1-1
$endlist
$component R60
R?
SM0603
SM0805
R?-*
$endlist
$component R59
R?
SM0603
SM0805
R?-*
$endlist
$component C114
CP*
SM*
$endlist
$component C111
SM*
C?
C1-1
$endlist
$component C94
SM*
C?
C1-1
$endlist
$component C92
SM*
C?
C1-1
$endlist
$component C93
SM*
C?
C1-1
$endlist
$component C91
SM*
C?
C1-1
$endlist
$component C90
SM*
C?
C1-1
$endlist
$component R30
R?
SM0603
SM0805
R?-*
$endlist
$component R29
R?
SM0603
SM0805
R?-*
$endlist
$component C77
SM*
C?
C1-1
$endlist
$component C76
SM*
C?
C1-1
$endlist
$component C66
SM*
C?
C1-1
$endlist
$component C63
SM*
C?
C1-1
$endlist
$component C60
SM*
C?
C1-1
$endlist
$component C57
SM*
C?
C1-1
$endlist
$component C54
SM*
C?
C1-1
$endlist
$component C69
SM*
C?
C1-1
$endlist
$component C67
SM*
C?
C1-1
$endlist
$component C64
SM*
C?
C1-1
$endlist
$component C61
SM*
C?
C1-1
$endlist
$component C58
SM*
C?
C1-1
$endlist
$component C55
SM*
C?
C1-1
$endlist
$component C68
SM*
C?
C1-1
$endlist
$component C65
SM*
C?
C1-1
$endlist
$component C62
SM*
C?
C1-1
$endlist
$component C59
SM*
C?
C1-1
$endlist
$component C56
SM*
C?
C1-1
$endlist
$component C50
SM*
C?
C1-1
$endlist
$component C47
SM*
C?
C1-1
$endlist
$component C44
SM*
C?
C1-1
$endlist
$component C41
SM*
C?
C1-1
$endlist
$component C53
SM*
C?
C1-1
$endlist
$component C51
SM*
C?
C1-1
$endlist
$component C49
SM*
C?
C1-1
$endlist
$component C46
SM*
C?
C1-1
$endlist
$component C52
SM*
C?
C1-1
$endlist
$component C43
SM*
C?
C1-1
$endlist
$component C40
SM*
C?
C1-1
$endlist
$component C48
SM*
C?
C1-1
$endlist
$component C45
SM*
C?
C1-1
$endlist
$component C42
SM*
C?
C1-1
$endlist
$component C39
SM*
C?
C1-1
$endlist
$component R23
R?
SM0603
SM0805
R?-*
$endlist
$component R22
R?
SM0603
SM0805
R?-*
$endlist
$component R24
R?
SM0603
SM0805
R?-*
$endlist
$component R21
R?
SM0603
SM0805
R?-*
$endlist
$component R19
R?
SM0603
SM0805
R?-*
$endlist
$component R20
R?
SM0603
SM0805
R?-*
$endlist
$component R17
R?
SM0603
SM0805
R?-*
$endlist
$component R18
R?
SM0603
SM0805
R?-*
$endlist
$component R16
R?
SM0603
SM0805
R?-*
$endlist
$component C104
SM*
C?
C1-1
$endlist
$component R57
R?
SM0603
SM0805
R?-*
$endlist
$component R56
R?
SM0603
SM0805
R?-*
$endlist
$component R58
R?
SM0603
SM0805
R?-*
$endlist
$component R45
R?
SM0603
SM0805
R?-*
$endlist
$component R44
R?
SM0603
SM0805
R?-*
$endlist
$component R41
R?
SM0603
SM0805
R?-*
$endlist
$component R40
R?
SM0603
SM0805
R?-*
$endlist
$component C100
SM*
C?
C1-1
$endlist
$component C99
SM*
C?
C1-1
$endlist
$component C103
SM*
C?
C1-1
$endlist
$component R43
R?
SM0603
SM0805
R?-*
$endlist
$component R42
R?
SM0603
SM0805
R?-*
$endlist
$component C102
SM*
C?
C1-1
$endlist
$component C101
SM*
C?
C1-1
$endlist
$component C95
SM*
C?
C1-1
$endlist
$component R35
R?
SM0603
SM0805
R?-*
$endlist
$component R36
R?
SM0603
SM0805
R?-*
$endlist
$component C98
SM*
C?
C1-1
$endlist
$component R39
R?
SM0603
SM0805
R?-*
$endlist
$component R38
R?
SM0603
SM0805
R?-*
$endlist
$component C97
SM*
C?
C1-1
$endlist
$component C96
SM*
C?
C1-1
$endlist
$component R37
R?
SM0603
SM0805
R?-*
$endlist
$component R34
R?
SM0603
SM0805
R?-*
$endlist
$component R33
R?
SM0603
SM0805
R?-*
$endlist
$component R31
R?
SM0603
SM0805
R?-*
$endlist
$component R32
R?
SM0603
SM0805
R?-*
$endlist
$component C82
SM*
C?
C1-1
$endlist
$component C83
SM*
C?
C1-1
$endlist
$component C84
SM*
C?
C1-1
$endlist
$component R27
R?
SM0603
SM0805
R?-*
$endlist
$component R28
R?
SM0603
SM0805
R?-*
$endlist
$component C85
SM*
C?
C1-1
$endlist
$component C81
SM*
C?
C1-1
$endlist
$component R26
R?
SM0603
SM0805
R?-*
$endlist
$component R25
R?
SM0603
SM0805
R?-*
$endlist
$component C80
SM*
C?
C1-1
$endlist
$component C79
SM*
C?
C1-1
$endlist
$component C78
SM*
C?
C1-1
$endlist
$component C75
SM*
C?
C1-1
$endlist
$component C74
SM*
C?
C1-1
$endlist
$component C73
SM*
C?
C1-1
$endlist
$component C72
SM*
C?
C1-1
$endlist
$component R53
R?
SM0603
SM0805
R?-*
$endlist
$component R54
R?
SM0603
SM0805
R?-*
$endlist
$component R55
R?
SM0603
SM0805
R?-*
$endlist
$component R49
R?
SM0603
SM0805
R?-*
$endlist
$component R50
R?
SM0603
SM0805
R?-*
$endlist
$component R52
R?
SM0603
SM0805
R?-*
$endlist
$component R51
R?
SM0603
SM0805
R?-*
$endlist
$component R48
R?
SM0603
SM0805
R?-*
$endlist
$component R47
R?
SM0603
SM0805
R?-*
$endlist
$component R46
R?
SM0603
SM0805
R?-*
$endlist
$component C35
SM*
C?
C1-1
$endlist
$component C36
SM*
C?
C1-1
$endlist
$component C37
SM*
C?
C1-1
$endlist
$component C38
SM*
C?
C1-1
$endlist
$component R15
R?
SM0603
SM0805
R?-*
$endlist
$component R10
R?
SM0603
SM0805
R?-*
$endlist
$component C16
SM*
C?
C1-1
$endlist
$component C15
SM*
C?
C1-1
$endlist
$component C14
SM*
C?
C1-1
$endlist
$component C13
SM*
C?
C1-1
$endlist
$component C9
SM*
C?
C1-1
$endlist
$component C6
SM*
C?
C1-1
$endlist
$component C4
SM*
C?
C1-1
$endlist
$component C2
SM*
C?
C1-1
$endlist
$component C8
SM*
C?
C1-1
$endlist
$component C7
SM*
C?
C1-1
$endlist
$component C5
SM*
C?
C1-1
$endlist
$component C3
SM*
C?
C1-1
$endlist
$component C1
SM*
C?
C1-1
$endlist
$component R1
R?
SM0603
SM0805
R?-*
$endlist
$component R2
R?
SM0603
SM0805
R?-*
$endlist
$component C11
SM*
C?
C1-1
$endlist
$component C10
SM*
C?
C1-1
$endlist
$component C12
SM*
C?
C1-1
$endlist
$component R9
R?
SM0603
SM0805
R?-*
$endlist
$component R3
R?
SM0603
SM0805
R?-*
$endlist
$component R4
R?
SM0603
SM0805
R?-*
$endlist
$component R6
R?
SM0603
SM0805
R?-*
$endlist
$component R5
R?
SM0603
SM0805
R?-*
$endlist
$component R8
R?
SM0603
SM0805
R?-*
$endlist
$component R7
R?
SM0603
SM0805
R?-*
$endlist
$component C70
SM*
C?
C1-1
$endlist
$component C71
SM*
C?
C1-1
$endlist
$component C34
SM*
C?
C1-1
$endlist
$component C33
SM*
C?
C1-1
$endlist
$component C28
SM*
C?
C1-1
$endlist
$component C29
SM*
C?
C1-1
$endlist
$component C31
SM*
C?
C1-1
$endlist
$component C30
SM*
C?
C1-1
$endlist
$component C32
SM*
C?
C1-1
$endlist
$component C27
SM*
C?
C1-1
$endlist
$component C21
SM*
C?
C1-1
$endlist
$component C26
SM*
C?
C1-1
$endlist
$component C24
SM*
C?
C1-1
$endlist
$component C25
SM*
C?
C1-1
$endlist
$component C23
SM*
C?
C1-1
$endlist
$component C22
SM*
C?
C1-1
$endlist
$component R13
R?
SM0603
SM0805
R?-*
$endlist
$component R14
R?
SM0603
SM0805
R?-*
$endlist
$component R12
R?
SM0603
SM0805
R?-*
$endlist
$component R11
R?
SM0603
SM0805
R?-*
$endlist
$component C19
SM*
C?
C1-1
$endlist
$component C20
SM*
C?
C1-1
$endlist
$component C18
SM*
C?
C1-1
$endlist
$component C17
SM*
C?
C1-1
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 16 "/FPGA, Port0, Port2, PROG IF/PROG_CCLK" "PROG_CCLK"
U1 AA21
U8 6
Net 17 "/FPGA, Port0, Port2, PROG IF/NF_RNB" "NF_RNB"
U1 A15
U5 7
U5 6
Net 18 "/Non volatile memories/NF_RE_N" "NF_RE_N"
U5 8
U1 C15
Net 19 "/FPGA, Port0, Port2, PROG IF/NF_CS1_N" "NF_CS1_N"
U5 9
U1 D15
Net 20 "/FPGA, Port0, Port2, PROG IF/NF_WE_N" "NF_WE_N"
U1 C14
U5 18
Net 21 "/FPGA, Port0, Port2, PROG IF/NF_CLE" "NF_CLE"
U1 B14
U5 16
Net 22 "/FPGA, Port0, Port2, PROG IF/NF_ALE" "NF_ALE"
U1 A14
U5 17
Net 23 "/FPGA, Port0, Port2, PROG IF/SD_CLK" "SD_CLK"
U1 A17
J1 5
Net 24 "/FPGA, Port0, Port2, PROG IF/SD_CMD" "SD_CMD"
U1 C16
J1 3
Net 25 "/DBG_PRG/FPGA_TCK" "FPGA_TCK"
J6 1
U1 G15
Net 26 "/DBG_PRG/FPGA_TMS" "FPGA_TMS"
U1 C18
J6 3
Net 27 "/DBG_PRG/FPGA_TDI" "FPGA_TDI"
U1 E18
J6 7
Net 28 "/DBG_PRG/FPGA_TDO" "FPGA_TDO"
U1 A19
J6 5
Net 34 "/FPGA Port 1, Port 3 DDR, USB/M1_UDM" "M1_UDM"
R18 2
U3 47
Net 35 "/DDR Banks/M1_LDQS" "M1_LDQS"
U3 16
RP3 8
Net 36 "/FPGA Port 1, Port 3 DDR, USB/M1_LDM" "M1_LDM"
U3 20
RP3 7
Net 37 "/DDR Banks/M1_UDQS" "M1_UDQS"
R19 2
U3 51
Net 38 "/DDR Banks/M0_UDQS" "M0_UDQS"
U2 51
R22 2
Net 39 "/DDR Banks/M0_LDM" "M0_LDM"
RP16 7
U2 20
Net 40 "/FPGA Port 1, Port 3 DDR, USB/M0_LDQS" "M0_LDQS"
RP16 8
U2 16
Net 41 "/FPGA Port 1, Port 3 DDR, USB/M0_UDM" "M0_UDM"
U2 47
R23 2
Net 42 "/FPGA Port 1, Port 3 DDR, USB/M1_CS#" "M1_CS#"
R20 2
U3 24
Net 43 "/FPGA, Port0, Port2, PROG IF/ETH_TXC" "ETH_TXC"
U4 15
U1 C8
Net 44 "/FPGA, Port0, Port2, PROG IF/ETH_RXER" "ETH_RXER"
U1 B8
U4 11
Net 45 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV"
U1 A6
U4 9
Net 46 "/Ethernet Phy/ETH_MDC" "ETH_MDC"
U1 D7
U4 2
Net 47 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO"
U4 1
U1 D6
R1 1
Net 48 "/Ethernet Phy/ETH_COL" "ETH_COL"
U1 A9
U4 21
Net 49 "/FPGA, Port0, Port2, PROG IF/ETH_CRS" "ETH_CRS"
U4 22
U1 B10
Net 50 "/FPGA, Port0, Port2, PROG IF/ETH_RESET_N" "ETH_RESET_N"
U4 48
U1 C7
Net 51 "/Ethernet Phy/ETH_RXC" "ETH_RXC"
U1 A7
U4 10
Net 52 "/FPGA Port 1, Port 3 DDR, USB/USBD_VM" "USBD_VM"
U1 B22
U7 4
Net 53 "/USB/USBD_VP" "USBD_VP"
U1 B21
U7 3
Net 54 "/USB/USBD_RCV" "USBD_RCV"
U1 A20
U7 2
Net 55 "/FPGA Port 1, Port 3 DDR, USB/USBD_OE_N" "USBD_OE_N"
U7 9
U1 A21
Net 56 "/USB/USBD_SPD" "USBD_SPD"
U7 1
U1 B20
Net 57 "/FPGA Port 1, Port 3 DDR, USB/USBA_VM" "USBA_VM"
U1 D20
U6 4
Net 58 "/FPGA Port 1, Port 3 DDR, USB/USBA_VP" "USBA_VP"
U1 D19
U6 3
Net 59 "/USB/USBA_RCV" "USBA_RCV"
U1 F17
U6 2
Net 60 "/FPGA Port 1, Port 3 DDR, USB/USBA_OE_N" "USBA_OE_N"
U1 C19
U6 9
Net 61 "/FPGA Port 1, Port 3 DDR, USB/USBA_SPD" "USBA_SPD"
U6 1
U1 F16
Net 62 "/FPGA, Port0, Port2, PROG IF/PROG_CSO" "PROG_CSO"
U8 1
U1 T5
Net 63 "/DDR Banks/M1_CAS#" "M1_CAS#"
RP3 5
U3 22
Net 64 "/DDR Banks/M1_CKE" "M1_CKE"
U3 45
R17 2
Net 65 "/DDR Banks/M1_CLK" "M1_CLK"
U3 46
R16 2
U1 H20
Net 66 "/DDR Banks/M1_CLK#" "M1_CLK#"
U3 44
U1 J19
R16 1
Net 67 "GND" "GND"
J1 6
J1 COM
C53 2
U1 R18
U1 L18
U1 G18
U1 D18
U1 N17
U1 B17
J1 CASE
J1 CASE
J1 CASE
U1 AA17
U1 AA13
U1 AB22
U1 AA9
U1 W19
C48 2
C10 2
C11 2
R2 2
C142 2
U4 36
C140 2
C74 2
C138 2
C136 2
U5 36
U5 13
C7 2
C5 2
C141 2
C3 2
C1 2
U4 23
C143 2
U4 44
C8 2
U4 35
R9 2
C12 2
C144 2
U4 39
C51 2
J4 5
J4 4
C75 1
U4 8
C40 2
C43 2
C52 2
U4 12
C46 2
C49 2
C65 2
C78 2
C80 2
C68 2
R25 2
C55 2
C58 2
C61 2
C81 2
C92 2
R33 2
C94 2
U14 5
C93 2
C91 2
U10 2
C90 2
U11 2
U12 2
C50 2
C47 2
C44 2
C41 2
C66 2
C63 2
C60 2
C57 2
C54 2
P1 1
C69 2
C64 2
C67 2
C62 2
C59 2
C56 2
C95 2
C104 2
C99 2
C100 2
R41 2
R44 2
U17 5
C45 2
C42 2
C39 2
C98 2
R38 2
C97 2
U15 2
C103 2
R42 2
C102 2
U16 5
R35 2
U10 PAD
U1 N9
U10 5
C85 2
R27 2
C84 2
C82 2
C77 2
C76 2
U13 5
R31 2
U1 U7
U1 H7
U1 E7
U9 8
U1 R5
U1 L5
U1 G5
U1 B5
U1 V4
U1 D4
U1 U2
U1 N2
U1 J2
U1 E2
U1 A1
U9 PAD
U1 W7
U1 B9
U1 J9
U1 L9
U1 V10
U1 E11
U1 J11
U1 L11
C35 2
C36 2
C37 2
U6 7
U1 N11
U1 E21
U1 J21
U1 N21
U1 U21
U1 AB1
U1 N13
C15 2
C14 2
C13 2
R10 2
C16 2
V1 2
U7 6
U7 7
U1 K14
U1 M14
U1 P14
U1 K10
U6 6
U1 M10
R47 1
R46 1
U1 P10
C9 2
U1 V14
U1 E15
C6 2
U1 J15
C4 2
C2 2
U1 N15
U1 AA5
U1 W16
L7 2
U1 B13
L5 2
U1 A22
V4 2
U1 P12
V3 2
C38 2
U1 M12
R15 2
V2 2
U1 K12
U1 J13
U1 L13
R53 1
R54 1
U23 2
C106 2
C105 2
U3 66
C108 2
R60 2
U3 48
U3 12
U3 52
C114 2
U3 34
U3 64
U3 6
C115 2
R62 2
C109 2
C110 2
R64 2
C116 2
U20 2
U2 48
U2 58
C107 2
C121 2
C118 2
C117 2
U18 2
C128 2
R68 2
C120 2
U19 2
U22 2
C127 2
R66 2
C25 2
U24 6
U2 52
C24 2
U2 24
U2 34
C26 2
C28 2
C130 2
C21 2
C70 2
C29 2
C71 2
C34 2
C31 2
U3 58
C131 2
C134 2
C22 2
R14 2
R12 2
C20 2
C18 2
U2 64
C135 2
C23 2
C132 2
C133 2
C33 2
C137 2
U2 66
C139 2
U24 30
U2 12
C73 2
C72 2
U24 39
U2 6
C129 2
U24 35
U24 44
C30 2
U8 4
C27 2
C32 2
Net 68 "/DDR Banks/M0_CLK#" "M0_CLK#"
R21 2
U2 44
U1 H3
Net 69 "/FPGA Port 1, Port 3 DDR, USB/M0_CLK" "M0_CLK"
R21 1
U1 H4
U2 46
Net 70 "/DDR Banks/M0_CKE" "M0_CKE"
U2 45
R24 2
Net 71 "/FPGA Port 1, Port 3 DDR, USB/M0_CAS#" "M0_CAS#"
RP16 5
U2 22
Net 72 "/DDR Banks/M1_WE#" "M1_WE#"
RP3 6
U3 21
Net 73 "/DDR Banks/M1_RAS#" "M1_RAS#"
U3 23
RP2 8
Net 74 "/FPGA Port 1, Port 3 DDR, USB/M0_RAS#" "M0_RAS#"
RP15 8
U2 23
Net 75 "/DDR Banks/M0_WE#" "M0_WE#"
RP16 6
U2 21
Net 76 "/Ethernet Phy/ETH_INT" "ETH_INT"
U4 25
U1 A10
Net 77 "/FPGA, Port0, Port2, PROG IF/ETH_CLK" "ETH_CLK"
U1 A4
U4 46
Net 78 "/FPGA, Port0, Port2, PROG IF/ETH_TXER" "ETH_TXER"
U4 14
U1 D8
Net 79 "/FPGA, Port0, Port2, PROG IF/ETH_TXEN" "ETH_TXEN"
U1 D9
U4 16
Net 80 "/FPGA, Port0, Port2, PROG IF/IS_LINE" "IS_LINE"
U24 29
U1 AA2
Net 81 "/Image Sensor/IS_FLASH" "IS_FLASH"
U24 26
U1 AB3
Net 82 "/FPGA, Port0, Port2, PROG IF/IS_TEST" "IS_TEST"
U24 25
U1 AA4
Net 83 "/FPGA, Port0, Port2, PROG IF/IS_OE_N" "IS_OE_N"
U1 Y4
U24 23
Net 84 "/Image Sensor/IS_EXTCLK" "IS_EXTCLK"
U1 W12
U24 5
Net 85 "/FPGA, Port0, Port2, PROG IF/IS_SCL" "IS_SCL"
U24 15
U1 Y12
Net 86 "+2.8_VAA" "+2.8_VAA"
U24 34
U24 36
U18 6
C135 1
C111 1
C133 1
U24 40
R59 1
C114 1
C134 1
Net 87 "/Image Sensor/+1.8_VDD" "+1.8_VDD"
C138 1
U24 19
C116 1
C139 1
C113 1
C136 1
R63 1
U24 14
U20 6
C137 1
Net 88 "+2.8_VDDPLL" "+2.8_VDDPLL"
C130 1
C129 1
U24 4
R67 1
U23 6
C125 1
C128 1
Net 89 "/FPGA, Port0, Port2, PROG IF/IS_FRAME" "IS_FRAME"
U24 28
U1 AB2
Net 90 "/Image Sensor/IS_PIXEL" "IS_PIXEL"
U1 AB6
U24 13
Net 91 "/FPGA, Port0, Port2, PROG IF/IS_STANDBY" "IS_STANDBY"
U24 22
U1 Y5
Net 92 "/Image Sensor/IS_RESET_N" "IS_RESET_N"
U1 AB5
U24 17
Net 93 "/Image Sensor/IS_I2C_ADDR" "IS_I2C_ADDR"
U1 AB4
U24 24
Net 94 "/Image Sensor/IS_SDA" "IS_SDA"
U1 AA6
U24 16
Net 95 "/Image Sensor/IS_TRIGGER" "IS_TRIGGER"
U1 Y3
U24 27
Net 96 "+2.8_VAAPIX" "+2.8_VAAPIX"
C132 1
U19 6
C112 1
R61 1
C115 1
C131 1
U24 38
U24 37
Net 97 "+2.8_VDDIO" "+2.8_VDDIO"
C142 1
C140 1
U24 12
U24 18
R65 1
C127 1
C124 1
U22 6
C144 1
C141 1
C143 1
Net 122 "+2.5V" "+2.5V"
U1 R10
C34 1
U1 F4
C28 1
C71 1
U1 C2
U1 G2
U1 L2
U1 U11
U1 L21
U1 R21
U1 W21
C37 1
U1 C21
U1 G21
U1 J18
U1 N18
U1 U18
U1 E19
U1 F11
U1 L16
U1 U5
U1 F6
C62 1
C59 1
C56 1
U1 R2
U7 15
U1 W2
U1 L7
C70 1
U1 J5
C15 1
U1 N5
U1 V6
U1 R6
C27 1
U1 L8
U1 N8
U1 H9
C103 1
L11 1
R43 1
C102 1
C101 1
U1 D16
U1 M15
U1 K15
U1 H15
C21 1
C94 1
C30 1
C31 1
C29 1
C65 1
C68 1
U2 9
U6 15
C32 1
C77 1
C17 1
U2 1
U2 3
U3 1
U3 61
U1 R12
U2 55
C23 1
C49 1
R13 1
U2 33
C25 1
R11 1
C19 1
U2 15
U3 55
C57 1
C33 1
U2 18
U2 61
C54 1
C51 1
C22 1
U3 18
C26 1
C66 1
U3 33
C63 1
C60 1
U3 15
C53 1
U1 G12
U3 9
C52 1
C24 1
C46 1
U3 3
C40 1
C43 1
Net 125 "/DDR Banks/M0_VREF" "M0_VREF"
C17 2
C18 1
R12 1
U2 49
R11 2
Net 126 "/DDR Banks/M1_VREF" "M1_VREF"
C19 2
C20 1
R14 1
U3 49
R13 2
Net 135 "VCCO2" "VCCO2"
U1 AA15
U8 8
U1 AA19
U1 V16
C55 1
U1 V8
C58 1
C61 1
U1 T13
U1 AA3
U1 AA11
U1 AA7
C67 1
C69 1
C64 1
U1 T9
U1 W5
U1 V12
Net 142 "+3.3V" "+3.3V"
U1 E17
U1 B19
U1 B4
R29 1
C41 1
C44 1
C47 1
C50 1
R30 1
C90 1
C91 1
U1 E9
U1 Y20
U1 B7
U1 B15
U1 G14
U1 G10
U1 B11
U1 E13
R1 2
C1 1
C3 1
C5 1
C10 1
C11 1
J4 11
J4 9
R5 1
R6 1
R4 1
R3 1
J4 6
J4 3
R55 1
C81 1
L8 1
U4 24
U4 7
R26 1
C80 1
C79 1
U6 14
U6 12
C36 1
C35 1
R48 1
C14 1
C13 1
U7 12
U7 14
L2 1
C104 1
C75 2
C74 1
U5 37
U5 19
U5 12
U9 9
J1 4
R57 2
C72 1
C73 1
Net 167 "" ""
R2 1
U4 37
Net 168 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
U4 27
R8 2
Net 169 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
L3 2
C9 1
U4 47
Net 170 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
L2 2
U4 38
C7 1
C8 1
Net 178 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD"
R9 1
J4 13
J4 14
C12 1
Net 179 "" ""
R7 1
J4 10
Net 180 "" ""
R8 1
J4 12
Net 181 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
U4 26
R7 2
Net 182 "/Ethernet Phy/MAG_TX-" "MAG_TX-"
R4 2
U4 40
J4 2
Net 183 "/Ethernet Phy/MAG_TX+" "MAG_TX+"
U4 41
R3 2
J4 1
Net 184 "/Ethernet Phy/MAG_RX+" "MAG_RX+"
J4 7
R5 2
U4 33
Net 185 "/Ethernet Phy/MAG_RX-" "MAG_RX-"
J4 8
U4 32
R6 2
Net 186 "+1.8V" "+1.8V"
U4 13
L1 1
C4 1
C2 1
Net 187 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
L3 1
C6 1
U4 31
L1 2
Net 188 "" ""
U6 10
R52 2
Net 189 "" ""
U7 11
R49 2
Net 190 "" ""
J7 5
J7 4
Net 191 "" ""
L5 1
J5 4
Net 192 "" ""
J5 1
L4 2
Net 193 "" ""
L4 1
F1 1
Net 194 "+5V" "+5V"
C98 1
F1 2
U15 5
C96 1
C97 1
R39 1
Net 195 "" ""
L7 1
J7 1
Net 196 "/USB/USB_CASE_HOST" "USB_CASE_HOST"
R10 1
J5 S4
C16 1
J5 S1
J5 S2
J5 S3
Net 197 "" ""
R51 2
U6 11
Net 198 "" ""
U7 10
R50 2
Net 199 "/USB/USBD_D-" "USBD_D-"
J7 2
R50 1
V4 1
R54 2
V4 1
Net 200 "/USB/USBA_D-" "USBA_D-"
R46 2
V2 1
V2 1
R52 1
J5 2
Net 201 "/USB/USB_CASE_DEV" "USB_CASE_DEV"
J7 9
J7 8
J7 7
J7 6
C38 1
R15 1
Net 202 "/USB/USBA_D+" "USBA_D+"
J5 3
R51 1
R47 2
R48 2
V1 1
V1 1
Net 203 "/USB/USBD_D+" "USBD_D+"
V3 1
V3 1
R55 2
J7 3
R53 2
R49 1
Net 204 "/PSU/VFB2.5" "VFB2.5"
U10 9
R43 2
R42 1
C101 2
Net 205 "" ""
U15 1
L10 1
Net 206 "/PSU/1.2V_EN" "1.2V_EN"
R58 1
U12 1
U9 3
Net 207 "/PSU/VFB3.3" "VFB3.3"
U11 5
R26 2
R25 1
C79 2
Net 208 "/PSU/3.3V_EN" "3.3V_EN"
U11 1
R56 1
U9 5
Net 209 "/PSU/lout_5.0" "lout_5.0"
R35 1
U16 3
U9 14
Net 210 "/PSU/lout_2.5" "lout_2.5"
U9 11
R44 1
U17 3
Net 211 "/PSU/AVR_SCK" "AVR_SCK"
U9 1
P1 2
Net 212 "/PSU/AVR_MISO" "AVR_MISO"
U9 20
P1 3
Net 213 "/PSU/AVR_MOSI" "AVR_MOSI"
P1 4
U9 16
Net 214 "" ""
C100 1
R40 2
Net 215 "/PSU/Iout_1.2" "Iout_1.2"
U9 2
R33 1
U14 3
Net 216 "/PSU/5V_EN" "5V_EN"
U15 4
R37 1
U9 15
Net 217 "/PSU/2.5V_EN" "2.5V_EN"
U10 1
U9 12
R41 1
Net 218 "+BATT" "+BATT"
R34 2
U17 1
R32 2
R45 2
U13 1
R36 2
U14 1
U16 1
Net 219 "" ""
R40 1
U10 10
Net 220 "/PSU/SW_2.5" "SW_2.5"
U10 3
U10 4
L11 2
Net 221 "/PSU/lout_3.3" "lout_3.3"
U9 4
U13 3
R31 1
Net 222 "/PSU/SW_3.3" "SW_3.3"
L8 2
U11 3
Net 223 "/PSU/VFB1.2" "VFB1.2"
R28 2
R27 1
U12 5
C83 2
Net 224 "+1.2V" "+1.2V"
C48 1
U1 P11
U1 M11
U1 K11
U1 N10
U1 L10
U1 J10
U1 P9
U1 R14
U1 N14
U1 L14
U1 J14
U1 P13
U1 M13
U1 K13
U1 J12
U1 L12
U1 N12
C84 1
C83 1
C39 1
C42 1
C45 1
U1 M9
C76 1
U1 K9
U1 J8
C85 1
R28 1
L9 1
C92 1
C93 1
Net 225 "/PSU/VFB5.0" "VFB5.0"
R39 2
R38 1
C96 2
U15 3
Net 226 "/PSU/SW_1.2" "SW_1.2"
L9 2
U12 3
Net 231 "/PSU/VIN_DC-DC-3.3" "VIN_DC-DC-3.3"
R56 2
U11 4
R32 1
U13 6
C78 1
Net 232 "/PSU/VIN_DC-DC-1.2" "VIN_DC-DC-1.2"
U14 6
U12 4
R34 1
C82 1
R58 2
Net 241 "/PSU/VIN_DC-DC-2.5" "VIN_DC-DC-2.5"
U10 8
U10 6
U10 7
U17 6
R45 1
C99 1
Net 242 "/PSU/AVR_RST" "AVR_RST"
U9 13
R57 1
Net 245 "/PSU/VIN_DC-DC-5.0" "VIN_DC-DC-5.0"
U15 6
L10 2
U16 6
R37 2
R36 1
C95 1
Net 262 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ11" "R_M0_DQ11"
RP11 4
U1 R1
Net 263 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ9" "R_M0_DQ9"
U1 P1
RP11 2
Net 264 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ13" "R_M0_DQ13"
RP10 2
U1 U1
Net 265 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ15" "R_M0_DQ15"
RP10 4
U1 V1
Net 266 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA1" "R_M0_BA1"
RP15 3
U1 G1
Net 267 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A1" "R_M0_A1"
RP14 2
U1 H1
Net 268 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A12" "R_M0_A12"
U1 D1
RP18 1
Net 269 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A11" "R_M0_A11"
U1 C1
RP18 2
Net 270 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A9" "R_M0_A9"
U1 E1
RP18 3
Net 271 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ7" "R_M0_DQ7"
RP12 4
U1 K1
Net 272 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ5" "R_M0_DQ5"
U1 J1
RP12 2
Net 273 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ3" "R_M0_DQ3"
U1 M1
RP13 4
Net 274 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ1" "R_M0_DQ1"
RP13 2
U1 N1
Net 275 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A9" "R_M1_A9"
U1 C22
RP7 6
Net 276 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A12" "R_M1_A12"
RP7 8
U1 D22
Net 277 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A2" "R_M1_A2"
RP1 3
U1 E22
Net 278 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A1" "R_M1_A1"
U1 F22
RP1 2
Net 281 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A4" "R_M1_A4"
U1 F20
RP6 5
Net 282 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A3" "R_M1_A3"
RP1 4
U1 G20
Net 283 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A5" "R_M1_A5"
RP6 6
U1 K20
Net 284 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDM" "R_M1_UDM"
R18 1
U1 M20
Net 286 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CKE" "R_M1_CKE"
U1 D21
R17 1
Net 287 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A0" "R_M1_A0"
U1 F21
RP1 1
Net 291 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A11" "R_M1_A11"
RP7 7
U1 F19
Net 292 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A10" "R_M1_A10"
RP2 4
U1 G19
Net 293 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A6" "R_M1_A6"
RP6 7
U1 K19
Net 308 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A4" "R_M0_A4"
U1 F3
RP17 4
Net 309 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA0" "R_M0_BA0"
U1 G3
RP15 2
Net 310 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ4" "R_M0_DQ4"
RP12 1
U1 J3
Net 311 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A5" "R_M0_A5"
RP17 3
U1 K3
Net 312 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ0" "R_M0_DQ0"
U1 N3
RP13 1
Net 314 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ10" "R_M0_DQ10"
RP11 3
U1 R3
Net 315 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ12" "R_M0_DQ12"
RP10 1
U1 U3
Net 318 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A10" "R_M0_A10"
RP15 4
U1 G4
Net 319 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A6" "R_M0_A6"
RP17 2
U1 J4
Net 322 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A0" "R_M0_A0"
RP14 1
U1 H2
Net 323 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ6" "R_M0_DQ6"
RP12 3
U1 K2
Net 324 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ2" "R_M0_DQ2"
RP13 3
U1 M2
Net 325 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ8" "R_M0_DQ8"
RP11 1
U1 P2
Net 326 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDQS" "R_M0_UDQS"
U1 T2
R22 1
Net 327 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ14" "R_M0_DQ14"
RP10 3
U1 V2
Net 331 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A8" "R_M0_A8"
RP18 4
U1 E3
Net 332 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A3" "R_M0_A3"
U1 K6
RP14 4
Net 346 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A8" "R_M1_A8"
U1 C20
RP7 5
Net 347 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A7" "R_M1_A7"
U1 E20
RP6 8
Net 355 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A2" "R_M0_A2"
U1 H5
RP14 3
Net 360 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A7" "R_M0_A7"
RP17 1
U1 H6
Net 362 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDQS" "R_M1_LDQS"
U1 L20
RP3 1
Net 363 "/FPGA Port 1, Port 3 DDR, USB/R_M1_WE#" "R_M1_WE#"
U1 H19
RP3 3
Net 364 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA0" "R_M1_BA0"
U1 J17
RP2 2
Net 365 "/FPGA Port 1, Port 3 DDR, USB/R_M0_RAS#" "R_M0_RAS#"
U1 K5
RP15 1
Net 366 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CAS#" "R_M0_CAS#"
RP16 4
U1 K4
Net 367 "/FPGA Port 1, Port 3 DDR, USB/R_M0_WE#" "R_M0_WE#"
RP16 3
U1 F2
Net 368 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDM" "R_M0_LDM"
U1 L4
RP16 2
Net 369 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDQS" "R_M0_LDQS"
RP16 1
U1 L3
Net 370 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ9" "R_M1_DQ9"
RP9 6
U1 P22
Net 371 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ11" "R_M1_DQ11"
U1 R22
RP9 8
Net 372 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ10" "R_M1_DQ10"
RP9 7
U1 R20
Net 373 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ8" "R_M1_DQ8"
RP9 5
U1 P21
Net 374 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA1" "R_M1_BA1"
RP2 3
U1 K17
Net 375 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CAS#" "R_M1_CAS#"
U1 H22
RP3 4
Net 376 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ12" "R_M1_DQ12"
RP8 5
U1 U20
Net 377 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ14" "R_M1_DQ14"
U1 V21
RP8 7
Net 378 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ15" "R_M1_DQ15"
U1 V22
RP8 8
Net 379 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ13" "R_M1_DQ13"
U1 U22
RP8 6
Net 380 "/FPGA Port 1, Port 3 DDR, USB/R_M1_RAS#" "R_M1_RAS#"
RP2 1
U1 H21
Net 381 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ3" "R_M1_DQ3"
RP5 4
U1 M22
Net 382 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ1" "R_M1_DQ1"
RP5 2
U1 N22
Net 383 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ0" "R_M1_DQ0"
RP5 1
U1 N20
Net 384 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ2" "R_M1_DQ2"
RP5 3
U1 M21
Net 385 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ6" "R_M1_DQ6"
RP4 3
U1 K21
Net 386 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ4" "R_M1_DQ4"
RP4 1
U1 J20
Net 387 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ5" "R_M1_DQ5"
RP4 2
U1 J22
Net 388 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ7" "R_M1_DQ7"
RP4 4
U1 K22
Net 389 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDM" "R_M1_LDM"
RP3 2
U1 L19
Net 390 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CKE" "R_M0_CKE"
U1 D2
R24 1
Net 391 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDM" "R_M0_UDM"
U1 M3
R23 1
Net 392 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDQS" "R_M1_UDQS"
U1 T21
R19 1
Net 393 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CS#" "R_M1_CS#"
U1 H16
R20 1
Net 395 "" ""
U1 Y22
R30 2
Net 397 "" ""
U1 AA1
R29 2
Net 485 "" ""
R64 1
R63 2
C113 2
U20 5
Net 486 "" ""
U20 4
C110 1
Net 487 "" ""
U23 1
U23 3
C118 1
Net 488 "" ""
U18 5
R60 1
R59 2
C111 2
Net 490 "" ""
C108 1
U18 4
Net 491 "" ""
U19 5
C112 2
R61 2
R62 1
Net 492 "" ""
U19 4
C109 1
Net 493 "" ""
C106 1
U19 1
U19 3
Net 494 "" ""
C125 2
R67 2
R68 1
U23 5
Net 495 "" ""
C121 1
U23 4
Net 496 "" ""
U22 1
U22 3
C117 1
Net 497 "" ""
C120 1
U22 4
Net 498 "" ""
C107 1
U20 3
U20 1
Net 499 "" ""
U18 3
C105 1
U18 1
Net 500 "" ""
R65 2
C124 2
R66 1
U22 5
Net 541 "/DDR Banks/M1_A12" "M1_A12"
U3 42
RP7 1
Net 542 "/FPGA Port 1, Port 3 DDR, USB/M1_A11" "M1_A11"
RP7 2
U3 41
Net 543 "/DDR Banks/M1_A10" "M1_A10"
U3 28
RP2 5
Net 544 "/FPGA Port 1, Port 3 DDR, USB/M1_A9" "M1_A9"
RP7 3
U3 40
Net 545 "/FPGA Port 1, Port 3 DDR, USB/M1_A8" "M1_A8"
U3 39
RP7 4
Net 546 "/FPGA Port 1, Port 3 DDR, USB/M1_A7" "M1_A7"
RP6 1
U3 38
Net 547 "/FPGA Port 1, Port 3 DDR, USB/M1_A6" "M1_A6"
U3 37
RP6 2
Net 548 "/DDR Banks/M1_A5" "M1_A5"
RP6 3
U3 36
Net 549 "/FPGA Port 1, Port 3 DDR, USB/M1_A4" "M1_A4"
RP6 4
U3 35
Net 550 "/DDR Banks/M1_A3" "M1_A3"
U3 32
RP1 5
Net 551 "/FPGA Port 1, Port 3 DDR, USB/M1_A2" "M1_A2"
U3 31
RP1 6
Net 552 "/FPGA, Port0, Port2, PROG IF/NF_D7" "NF_D7"
U5 44
U1 D11
Net 553 "/FPGA, Port0, Port2, PROG IF/NF_D6" "NF_D6"
U5 43
U1 A11
Net 554 "/FPGA, Port0, Port2, PROG IF/NF_D5" "NF_D5"
U5 42
U1 C11
Net 555 "/Non volatile memories/NF_D4" "NF_D4"
U5 41
U1 A12
Net 556 "/Non volatile memories/NF_D3" "NF_D3"
U1 B12
U5 32
Net 557 "/Non volatile memories/NF_D2" "NF_D2"
U1 A13
U5 31
Net 558 "/FPGA, Port0, Port2, PROG IF/NF_D1" "NF_D1"
U5 30
U1 D14
Net 559 "/FPGA, Port0, Port2, PROG IF/NF_D0" "NF_D0"
U5 29
U1 C12
Net 560 "/Non volatile memories/SD_DAT3" "SD_DAT3"
U1 B16
J1 2
Net 561 "/Non volatile memories/SD_DAT2" "SD_DAT2"
U1 A16
J1 1
Net 562 "/Non volatile memories/SD_DAT1" "SD_DAT1"
U1 B18
J1 8
Net 563 "/FPGA, Port0, Port2, PROG IF/SD_DAT0" "SD_DAT0"
J1 7
U1 A18
Net 564 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ0" "M0_DQ0"
RP13 8
U2 2
Net 565 "/DDR Banks/M1_DQ15" "M1_DQ15"
U3 65
RP8 1
Net 566 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ14" "M1_DQ14"
RP8 2
U3 63
Net 567 "/DDR Banks/M1_DQ13" "M1_DQ13"
RP8 3
U3 62
Net 568 "/DDR Banks/M1_DQ12" "M1_DQ12"
RP8 4
U3 60
Net 569 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ11" "M1_DQ11"
U3 59
RP9 1
Net 570 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ10" "M1_DQ10"
RP9 2
U3 57
Net 571 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ9" "M1_DQ9"
RP9 3
U3 56
Net 572 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ8" "M1_DQ8"
U3 54
RP9 4
Net 573 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ7" "M1_DQ7"
U3 13
RP4 5
Net 574 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ6" "M1_DQ6"
U3 11
RP4 6
Net 575 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ5" "M1_DQ5"
RP4 7
U3 10
Net 576 "/DDR Banks/M1_DQ4" "M1_DQ4"
U3 8
RP4 8
Net 577 "/DDR Banks/M1_DQ3" "M1_DQ3"
U3 7
RP5 5
Net 578 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ2" "M1_DQ2"
U3 5
RP5 6
Net 579 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ1" "M1_DQ1"
RP5 7
U3 4
Net 580 "/DDR Banks/M1_DQ0" "M1_DQ0"
RP5 8
U3 2
Net 581 "/FPGA Port 1, Port 3 DDR, USB/M1_BA1" "M1_BA1"
U3 27
RP2 6
Net 582 "/DDR Banks/M1_BA0" "M1_BA0"
RP2 7
U3 26
Net 583 "/DDR Banks/M1_A1" "M1_A1"
RP1 7
U3 30
Net 584 "/DDR Banks/M1_A0" "M1_A0"
RP1 8
U3 29
Net 585 "/DDR Banks/M0_A12" "M0_A12"
RP18 8
U2 42
Net 586 "/DDR Banks/M0_A11" "M0_A11"
RP18 7
U2 41
Net 587 "/DDR Banks/M0_A10" "M0_A10"
U2 28
RP15 5
Net 588 "/DDR Banks/M0_A9" "M0_A9"
U2 40
RP18 6
Net 589 "/FPGA Port 1, Port 3 DDR, USB/M0_A8" "M0_A8"
U2 39
RP18 5
Net 590 "/DDR Banks/M0_A7" "M0_A7"
RP17 8
U2 38
Net 591 "/FPGA Port 1, Port 3 DDR, USB/M0_A6" "M0_A6"
U2 37
RP17 7
Net 592 "/FPGA Port 1, Port 3 DDR, USB/M0_A5" "M0_A5"
RP17 6
U2 36
Net 593 "/FPGA Port 1, Port 3 DDR, USB/M0_A4" "M0_A4"
RP17 5
U2 35
Net 594 "/FPGA Port 1, Port 3 DDR, USB/M0_A3" "M0_A3"
RP14 5
U2 32
Net 595 "/DDR Banks/M0_A2" "M0_A2"
U2 31
RP14 6
Net 596 "/DDR Banks/M0_A1" "M0_A1"
RP14 7
U2 30
Net 597 "/DDR Banks/M0_A0" "M0_A0"
U2 29
RP14 8
Net 598 "/DDR Banks/M0_DQ15" "M0_DQ15"
RP10 5
U2 65
Net 599 "/DDR Banks/M0_DQ14" "M0_DQ14"
RP10 6
U2 63
Net 600 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ13" "M0_DQ13"
U2 62
RP10 7
Net 601 "/DDR Banks/M0_DQ12" "M0_DQ12"
RP10 8
U2 60
Net 602 "/DDR Banks/M0_DQ11" "M0_DQ11"
RP11 5
U2 59
Net 603 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ10" "M0_DQ10"
RP11 6
U2 57
Net 604 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ9" "M0_DQ9"
U2 56
RP11 7
Net 605 "/DDR Banks/M0_DQ8" "M0_DQ8"
U2 54
RP11 8
Net 606 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ7" "M0_DQ7"
RP12 5
U2 13
Net 607 "/DDR Banks/M0_DQ6" "M0_DQ6"
RP12 6
U2 11
Net 608 "/DDR Banks/M0_DQ5" "M0_DQ5"
RP12 7
U2 10
Net 609 "/DDR Banks/M0_DQ4" "M0_DQ4"
RP12 8
U2 8
Net 610 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ3" "M0_DQ3"
U2 7
RP13 5
Net 611 "/DDR Banks/M0_DQ2" "M0_DQ2"
U2 5
RP13 6
Net 612 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ1" "M0_DQ1"
RP13 7
U2 4
Net 613 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1"
U1 C9
U4 18
Net 614 "/FPGA, Port0, Port2, PROG IF/ETH_TXD0" "ETH_TXD0"
U4 17
U1 D10
Net 615 "/FPGA, Port0, Port2, PROG IF/ETH_RXD3" "ETH_RXD3"
U4 3
U1 C5
Net 616 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2"
U1 C6
U4 4
Net 617 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1"
U1 A5
U4 5
Net 618 "/FPGA, Port0, Port2, PROG IF/ETH_RXD0" "ETH_RXD0"
U1 B6
U4 6
Net 619 "/FPGA, Port0, Port2, PROG IF/PROG_MISO3" "PROG_MISO3"
U8 7
U1 U13
Net 620 "/FPGA, Port0, Port2, PROG IF/PROG_MISO2" "PROG_MISO2"
U8 3
U1 U14
Net 621 "/FPGA, Port0, Port2, PROG IF/PROG_MISO1" "PROG_MISO1"
U8 2
U1 AA20
Net 622 "/FPGA, Port0, Port2, PROG IF/PROG_MISO0" "PROG_MISO0"
U8 5
U1 AB20
Net 623 "/FPGA Port 1, Port 3 DDR, USB/M0_BA1" "M0_BA1"
U2 27
RP15 6
Net 624 "/DDR Banks/M0_BA0" "M0_BA0"
RP15 7
U2 26
Net 625 "/FPGA, Port0, Port2, PROG IF/ETH_TXD3" "ETH_TXD3"
U1 A8
U4 20
Net 626 "/FPGA, Port0, Port2, PROG IF/ETH_TXD2" "ETH_TXD2"
U4 19
U1 C10
Net 627 "/Image Sensor/IS_DOUT11" "IS_DOUT11"
U1 AB7
U24 11
Net 628 "/Image Sensor/IS_DOUT10" "IS_DOUT10"
U24 10
U1 Y6
Net 629 "/FPGA, Port0, Port2, PROG IF/IS_DOUT9" "IS_DOUT9"
U1 Y7
U24 9
Net 630 "/Image Sensor/IS_DOUT8" "IS_DOUT8"
U1 AB8
U24 8
Net 631 "/FPGA, Port0, Port2, PROG IF/IS_DOUT7" "IS_DOUT7"
U1 AA8
U24 7
Net 632 "/FPGA, Port0, Port2, PROG IF/IS_DOUT6" "IS_DOUT6"
U24 3
U1 Y8
Net 633 "/FPGA, Port0, Port2, PROG IF/IS_DOUT5" "IS_DOUT5"
U1 AB9
U24 2
Net 634 "/Image Sensor/IS_DOUT4" "IS_DOUT4"
U1 AA10
U24 1
Net 635 "/Image Sensor/IS_DOUT3" "IS_DOUT3"
U1 AB10
U24 48
Net 636 "/FPGA, Port0, Port2, PROG IF/IS_DOUT2" "IS_DOUT2"
U1 AB11
U24 47
Net 637 "/Image Sensor/IS_DOUT1" "IS_DOUT1"
U24 46
U1 AA12
Net 638 "/FPGA, Port0, Port2, PROG IF/IS_DOUT0" "IS_DOUT0"
U24 45
U1 AB12
}
#End
View Git Blame Copy Permalink