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Code
e678c0e51a
xue/kicad/xue-rnc/xue-rnc.net
Andres Calderon e678c0e51a fixed placement
2010-08-12 16:12:57 -05:00

1978 lines
32 KiB
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# EESchema Netlist Version 1.1 created Thu 12 Aug 2010 08:51:33 AM COT
(
( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR}
( 1 N-000357 )
( 2 N-000362 )
)
( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR}
( 1 N-000358 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R}
( 1 N-000361 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C}
( 1 N-000361 )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000360 )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03}
( 1 N-000356 )
( 2 GND )
)
( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F}
( 1 N-000357 )
( 2 +5V )
)
( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001}
( S1 N-000361 )
( S2 N-000361 )
( S3 N-000361 )
( S4 N-000361 )
( 1 N-000362 )
( 2 N-000356 )
( 3 N-000360 )
( 4 N-000358 )
)
( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C}
( 1 N-000363 )
( 2 GND )
)
( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C}
( 1 N-000363 )
( 2 GND )
)
( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C}
( 1 N-000363 )
( 2 GND )
)
( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS}
( 1 +2.5V )
( 2 /USB/USBA_SPD )
( 3 /USB/USBA_RCV )
( 4 /FPGA_Spartan6/USBA_VP )
( 5 /FPGA_Spartan6/USBA_VM )
( 7 GND )
( 8 GND )
( 9 /FPGA_Spartan6/USBA_OE_N )
( 10 N-000356 )
( 11 N-000360 )
( 12 3.3V )
( 14 3.3V )
)
( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
( P7 ? )
( N7 ? )
( M7 ? )
( L7 +2.5V )
( K7 ? )
( J7 ? )
( G7 ? )
( F7 ? )
( P6 ? )
( N6 ? )
( M6 ? )
( L6 ? )
( K6 /FPGA_Spartan6/M0_A3 )
( J6 ? )
( H6 /DDR_Banks/M0_A7 )
( G6 ? )
( F6 +2.5V )
( E6 ? )
( U5 +2.5V )
( P5 ? )
( N5 +2.5V )
( M5 ? )
( K5 /FPGA_Spartan6/M0_RAS# )
( J5 +2.5V )
( H5 /FPGA_Spartan6/M0_A2 )
( F5 ? )
( E5 ? )
( D5 ? )
( U4 ? )
( H21 /DDR_Banks/M1_RAS# )
( G21 +2.5V )
( F21 /FPGA_Spartan6/M1_A0 )
( D21 /DDR_Banks/M1_CKE )
( C21 +2.5V )
( B21 ? )
( A21 ? )
( W20 ? )
( V20 ? )
( U20 /FPGA_Spartan6/M1_DQ12 )
( T20 ? )
( R20 /FPGA_Spartan6/M1_DQ10 )
( P20 ? )
( N20 /DDR_Banks/M1_DQ0 )
( M20 /FPGA_Spartan6/M1_UDM )
( L20 /FPGA_Spartan6/M1_LDQS )
( K20 /DDR_Banks/M1_A5 )
( J20 /FPGA_Spartan6/M1_DQ4 )
( H20 /FPGA_Spartan6/M1_CLK )
( G20 /FPGA_Spartan6/M1_A3 )
( F20 /DDR_Banks/M1_A4 )
( E20 /FPGA_Spartan6/M1_A7 )
( D20 ? )
( C20 /FPGA_Spartan6/M1_A8 )
( B20 ? )
( A20 ? )
( P8 ? )
( M8 ? )
( K8 ? )
( H8 ? )
( B3 ? )
( W2 +2.5V )
( V2 /FPGA_Spartan6/M0_DQ14 )
( T2 /DDR_Banks/M0_UDQS )
( R2 +2.5V )
( P2 /FPGA_Spartan6/M0_DQ8 )
( M2 /FPGA_Spartan6/M0_DQ2 )
( L2 +2.5V )
( K2 /DDR_Banks/M0_DQ6 )
( H2 /FPGA_Spartan6/M0_A0 )
( G2 +2.5V )
( F2 /FPGA_Spartan6/M0_WE# )
( D2 /FPGA_Spartan6/M0_CKE )
( C2 +2.5V )
( B2 ? )
( A2 ? )
( Y1 ? )
( W1 ? )
( V1 /FPGA_Spartan6/M0_DQ15 )
( U1 /DDR_Banks/M0_DQ13 )
( T1 ? )
( R1 /FPGA_Spartan6/M0_DQ11 )
( P1 /DDR_Banks/M0_DQ9 )
( N1 /FPGA_Spartan6/M0_DQ1 )
( M1 /FPGA_Spartan6/M0_DQ3 )
( L1 ? )
( K1 /FPGA_Spartan6/M0_DQ7 )
( J1 /DDR_Banks/M0_DQ5 )
( H1 /FPGA_Spartan6/M0_A1 )
( G1 /FPGA_Spartan6/M0_BA1 )
( T4 ? )
( R4 ? )
( P4 ? )
( N4 ? )
( M4 ? )
( L4 /DDR_Banks/M0_LDM )
( K4 /FPGA_Spartan6/M0_CAS# )
( J4 /FPGA_Spartan6/M0_A6 )
( H4 /DDR_Banks/M0_CLK )
( G4 /DDR_Banks/M0_A10 )
( F4 +2.5V )
( E4 ? )
( C4 ? )
( W3 ? )
( V3 ? )
( U3 /FPGA_Spartan6/M0_DQ12 )
( T3 ? )
( R3 /DDR_Banks/M0_DQ10 )
( P3 ? )
( N3 /FPGA_Spartan6/M0_DQ0 )
( M3 /DDR_Banks/M0_UDM )
( L3 /DDR_Banks/M0_LDQS )
( K3 /DDR_Banks/M0_A5 )
( J3 /FPGA_Spartan6/M0_DQ4 )
( H3 /FPGA_Spartan6/M0_CLK# )
( G3 /DDR_Banks/M0_BA0 )
( F3 /FPGA_Spartan6/M0_A4 )
( E3 /FPGA_Spartan6/M0_A8 )
( D3 ? )
( C3 ? )
( G10 +3.3V )
( D10 /Ethernet_Phy/ETH_RXC )
( C10 /FPGA_Spartan6/ETH_CLK )
( B10 /Ethernet_Phy/ETH_CRS )
( A10 /Ethernet_Phy/ETH_COL )
( E9 +3.3V )
( D9 /Ethernet_Phy/ETH_TXEN )
( C9 /Ethernet_Phy/ETH_TXD1 )
( A9 /Ethernet_Phy/ETH_TXD2 )
( D8 /Ethernet_Phy/ETH_TXC )
( C8 /FPGA_Spartan6/ETH_TXD0 )
( B8 /Ethernet_Phy/ETH_RXER )
( A8 /Ethernet_Phy/ETH_TXER )
( D7 /FPGA_Spartan6/ETH_TXD3 )
( C7 /Ethernet_Phy/ETH_RXD0 )
( B7 +3.3V )
( A7 /Ethernet_Phy/ETH_RXDV )
( D6 /FPGA_Spartan6/ETH_RESET_N )
( C6 /FPGA_Spartan6/ETH_RXD3 )
( B6 /FPGA_Spartan6/ETH_RXD2 )
( A6 /Ethernet_Phy/ETH_RXD1 )
( C5 /Ethernet_Phy/ETH_MDC )
( A5 /FPGA_Spartan6/ETH_MDIO )
( B4 +3.3V )
( A4 /Ethernet_Phy/ETH_INT )
( U19 ? )
( T19 ? )
( R19 ? )
( P19 ? )
( N19 ? )
( B19 +3.3V )
( B18 /FPGA_Spartan6/USBA_VP )
( A18 /USB/USBA_RCV )
( E17 +3.3V )
( D17 /USB/USBA_SPD )
( C17 /Non_volatile_memories/SD_CMD )
( A17 /FPGA_Spartan6/USBA_VM )
( E16 /FPGA_Spartan6/USBA_OE_N )
( C16 /Non_volatile_memories/SD_DAT1 )
( B16 /Non_volatile_memories/SD_DAT0 )
( A16 /Non_volatile_memories/SD_CLK )
( D15 /Non_volatile_memories/SD_DAT2 )
( C15 ? )
( B15 +3.3V )
( A15 /FPGA_Spartan6/SD_DAT3 )
( G14 +3.3V )
( D14 ? )
( C14 ? )
( B14 ? )
( A14 ? )
( E13 +3.3V )
( C13 ? )
( A13 ? )
( C12 ? )
( B12 ? )
( A12 ? )
( D11 ? )
( C11 ? )
( B11 +3.3V )
( A11 ? )
( H16 ? )
( G16 ? )
( F16 ? )
( L15 ? )
( W22 ? )
( V22 /FPGA_Spartan6/M1_DQ15 )
( U22 /DDR_Banks/M1_DQ13 )
( T22 ? )
( R22 /FPGA_Spartan6/M1_DQ11 )
( P22 /FPGA_Spartan6/M1_DQ9 )
( N22 /FPGA_Spartan6/M1_DQ1 )
( M22 /DDR_Banks/M1_DQ3 )
( L22 ? )
( K22 /FPGA_Spartan6/M1_DQ7 )
( J22 /DDR_Banks/M1_DQ5 )
( H22 /DDR_Banks/M1_CAS# )
( G22 ? )
( F22 /FPGA_Spartan6/M1_A1 )
( E22 /FPGA_Spartan6/M1_A2 )
( D22 /FPGA_Spartan6/M1_A12 )
( C22 /DDR_Banks/M1_A9 )
( B22 ? )
( W21 +2.5V )
( V21 /FPGA_Spartan6/M1_DQ14 )
( T21 /FPGA_Spartan6/M1_UDQS )
( R21 +2.5V )
( P21 /FPGA_Spartan6/M1_DQ8 )
( M21 /FPGA_Spartan6/M1_DQ2 )
( L21 +2.5V )
( K21 /DDR_Banks/M1_DQ6 )
( M19 ? )
( L19 /DDR_Banks/M1_LDM )
( K19 /DDR_Banks/M1_A6 )
( J19 /FPGA_Spartan6/M1_CLK# )
( H19 /FPGA_Spartan6/M1_WE# )
( G19 /DDR_Banks/M1_A10 )
( F19 /DDR_Banks/M1_A11 )
( E19 +2.5V )
( D19 ? )
( U18 +2.5V )
( P18 ? )
( N18 +2.5V )
( M18 ? )
( K18 ? )
( J18 +2.5V )
( H18 ? )
( F18 ? )
( P17 ? )
( M17 ? )
( L17 ? )
( K17 /FPGA_Spartan6/M1_BA1 )
( J17 /DDR_Banks/M1_BA0 )
( H17 ? )
( G17 ? )
( F17 ? )
( N16 ? )
( M16 ? )
( L16 +2.5V )
( K16 ? )
( J16 ? )
( J14 +1.2V )
( H14 ? )
( F14 ? )
( E14 ? )
( P13 +1.2V )
( N13 GND )
( M13 +1.2V )
( L13 GND )
( K13 +1.2V )
( J13 GND )
( H13 ? )
( G13 ? )
( F13 ? )
( D13 ? )
( B13 GND )
( Y22 ? )
( A22 GND )
( R12 +2.5V )
( P12 GND )
( N12 +1.2V )
( M12 GND )
( L12 +1.2V )
( K12 ? )
( J12 +1.2V )
( H12 ? )
( G12 +2.5V )
( F12 ? )
( E12 ? )
( D12 ? )
( AB1 GND )
( A19 ? )
( R18 GND )
( L18 GND )
( G18 GND )
( E18 ? )
( D18 GND )
( C18 ? )
( R17 ? )
( N17 GND )
( B17 GND )
( W16 GND )
( P16 ? )
( D16 +2.5V )
( AA5 GND )
( P15 ? )
( N15 ? )
( M15 +2.5V )
( K15 +2.5V )
( J15 GND )
( H15 +2.5V )
( G15 ? )
( F15 ? )
( E15 GND )
( V14 GND )
( R14 +1.2V )
( P14 GND )
( N14 +1.2V )
( M14 GND )
( L14 +1.2V )
( K14 GND )
( L9 GND )
( K9 +1.2V )
( J9 GND )
( H9 +2.5V )
( G9 ? )
( F9 ? )
( B9 GND )
( N8 +2.5V )
( L8 +2.5V )
( J8 +1.2V )
( G8 ? )
( F8 ? )
( E8 ? )
( W7 GND )
( U7 GND )
( H7 GND )
( E7 GND )
( V6 +2.5V )
( R6 +2.5V )
( R5 GND )
( L5 GND )
( G5 GND )
( B5 GND )
( V4 GND )
( D4 GND )
( U2 GND )
( N2 GND )
( J2 GND )
( E2 GND )
( A1 GND )
( AA1 ? )
( U21 GND )
( N21 GND )
( J21 GND )
( E21 GND )
( U11 +2.5V )
( P11 +1.2V )
( N11 GND )
( M11 +1.2V )
( L11 GND )
( K11 +1.2V )
( J11 GND )
( H11 ? )
( G11 ? )
( F11 +2.5V )
( E11 ? )
( V10 GND )
( R10 +2.5V )
( P10 GND )
( N10 +1.2V )
( M10 GND )
( L10 +1.2V )
( K10 GND )
( J10 +1.2V )
( H10 ? )
( F10 ? )
( E10 ? )
( P9 +1.2V )
( N9 GND )
( M9 +1.2V )
( V19 ? )
( AB8 ? )
( AA8 ? )
( Y18 ? )
( W18 ? )
( V18 ? )
( T18 ? )
( AB7 ? )
( AA7 N-000101 )
( Y17 ? )
( W17 ? )
( V17 ? )
( U17 ? )
( T17 ? )
( AB6 ? )
( AA6 ? )
( Y16 ? )
( V16 N-000101 )
( U16 ? )
( T16 ? )
( R16 ? )
( AB5 ? )
( Y15 ? )
( W15 ? )
( V15 ? )
( U15 ? )
( T15 ? )
( R15 ? )
( AB4 ? )
( AA4 ? )
( F1 ? )
( E1 /FPGA_Spartan6/M0_A9 )
( D1 /FPGA_Spartan6/M0_A12 )
( C1 /FPGA_Spartan6/M0_A11 )
( B1 ? )
( AB19 ? )
( AA19 N-000101 )
( AB18 ? )
( AA18 ? )
( AB17 ? )
( AB16 ? )
( AA16 ? )
( AB15 ? )
( AA15 N-000101 )
( AB14 ? )
( AA14 ? )
( AB13 ? )
( AA22 ? )
( AB12 ? )
( AA12 ? )
( AB21 ? )
( AA21 ? )
( AB11 ? )
( AA11 N-000101 )
( AB20 ? )
( AA20 ? )
( AB10 ? )
( AA10 ? )
( AB9 ? )
( Y19 ? )
( V9 ? )
( U9 ? )
( T9 N-000101 )
( R9 ? )
( Y8 ? )
( W8 ? )
( V8 N-000101 )
( U8 ? )
( T8 ? )
( R8 ? )
( Y7 ? )
( V7 ? )
( T7 ? )
( R7 ? )
( Y6 ? )
( W6 ? )
( U6 ? )
( T6 ? )
( Y5 ? )
( W5 N-000101 )
( V5 ? )
( T5 ? )
( Y4 ? )
( W4 ? )
( Y3 ? )
( AA17 GND )
( AA13 GND )
( AB22 GND )
( AA9 GND )
( W19 GND )
( Y14 ? )
( W14 ? )
( U14 ? )
( T14 ? )
( AB3 ? )
( AA3 N-000101 )
( Y13 ? )
( W13 ? )
( V13 ? )
( U13 ? )
( T13 N-000101 )
( R13 ? )
( AB2 ? )
( AA2 ? )
( Y12 ? )
( W12 ? )
( V12 N-000101 )
( U12 ? )
( T12 ? )
( Y11 ? )
( W11 ? )
( V11 ? )
( T11 ? )
( R11 ? )
( Y10 ? )
( W10 ? )
( U10 ? )
( T10 ? )
( Y9 ? )
( W9 ? )
)
( /4C4320F3/4C5D8114 $noname C9 C {Lib=C}
( 1 /Ethernet_Phy/ETH_PLL1.8V )
( 2 N-000347 )
)
( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 /Ethernet_Phy/ETH_PLL1.8V )
)
( /4C4320F3/4C5D8104 $noname C6 C {Lib=C}
( 1 /Ethernet_Phy/ETH_A1.8V )
( 2 N-000347 )
)
( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR}
( 1 N-000338 )
( 2 /Ethernet_Phy/ETH_A1.8V )
)
( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C}
( 1 N-000338 )
( 2 N-000347 )
)
( /4C4320F3/4C5D80ED $noname C2 C {Lib=C}
( 1 /Ethernet_Phy/ETH_1.8V )
( 2 GND )
)
( /4C4320F3/4C5D7FB7 $noname L2 FB {Lib=INDUCTOR}
( 1 3.3V )
( 2 /Ethernet_Phy/ETH_A3.3V )
)
( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C}
( 1 /Ethernet_Phy/ETH_A3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C}
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C}
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C}
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R}
( 1 /FPGA_Spartan6/ETH_MDIO )
( 2 3.3V )
)
( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R}
( 1 N-000344 )
( 2 GND )
)
( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C}
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C}
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C}
( 1 N-000336 )
( 2 GND )
)
( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R}
( 1 N-000336 )
( 2 GND )
)
( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001}
( 1 /FPGA_Spartan6/ETH_MDIO )
( 2 /Ethernet_Phy/ETH_MDC )
( 3 /FPGA_Spartan6/ETH_RXD3 )
( 4 /FPGA_Spartan6/ETH_RXD2 )
( 5 /Ethernet_Phy/ETH_RXD1 )
( 6 /Ethernet_Phy/ETH_RXD0 )
( 7 3.3V )
( 8 GND )
( 9 /Ethernet_Phy/ETH_RXDV )
( 10 /Ethernet_Phy/ETH_RXC )
( 11 /Ethernet_Phy/ETH_RXER )
( 12 GND )
( 13 /Ethernet_Phy/ETH_1.8V )
( 14 /Ethernet_Phy/ETH_TXER )
( 15 /Ethernet_Phy/ETH_TXC )
( 16 /Ethernet_Phy/ETH_TXEN )
( 17 /FPGA_Spartan6/ETH_TXD0 )
( 18 /Ethernet_Phy/ETH_TXD1 )
( 19 /Ethernet_Phy/ETH_TXD2 )
( 20 /FPGA_Spartan6/ETH_TXD3 )
( 21 /Ethernet_Phy/ETH_COL )
( 22 /Ethernet_Phy/ETH_CRS )
( 23 GND )
( 24 3.3V )
( 25 /Ethernet_Phy/ETH_INT )
( 26 /Ethernet_Phy/ETH_LED0 )
( 27 /Ethernet_Phy/ETH_LED1 )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 /Ethernet_Phy/ETH_A1.8V )
( 32 N-000345 )
( 33 N-000335 )
( 34 ? )
( 35 GND )
( 36 GND )
( 37 N-000344 )
( 38 /Ethernet_Phy/ETH_A3.3V )
( 39 GND )
( 40 N-000346 )
( 41 N-000334 )
( 42 ? )
( 43 ? )
( 44 GND )
( 45 ? )
( 46 /FPGA_Spartan6/ETH_CLK )
( 47 /Ethernet_Phy/ETH_PLL1.8V )
( 48 /FPGA_Spartan6/ETH_RESET_N )
)
( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R}
( 1 3.3V )
( 2 N-000334 )
)
( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R}
( 1 3.3V )
( 2 N-000346 )
)
( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R}
( 1 3.3V )
( 2 N-000345 )
)
( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R}
( 1 3.3V )
( 2 N-000335 )
)
( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R}
( 1 N-000350 )
( 2 /Ethernet_Phy/ETH_LED1 )
)
( /4C4320F3/4C5D719D $noname R7 220 {Lib=R}
( 1 N-000337 )
( 2 /Ethernet_Phy/ETH_LED0 )
)
( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025}
( 1 N-000334 )
( 2 N-000346 )
( 3 3.3V )
( 4 GND )
( 5 GND )
( 6 3.3V )
( 7 N-000335 )
( 8 N-000345 )
( 9 3.3V )
( 10 N-000337 )
( 11 3.3V )
( 12 N-000350 )
( 13 N-000336 )
( 14 N-000336 )
)
( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD}
( CASE GND )
( COM GND )
( CD ? )
( 1 /Non_volatile_memories/SD_DAT2 )
( 2 /FPGA_Spartan6/SD_DAT3 )
( 3 /Non_volatile_memories/SD_CMD )
( 4 ? )
( 5 /Non_volatile_memories/SD_CLK )
( 6 GND )
( 7 /Non_volatile_memories/SD_DAT0 )
( 8 /Non_volatile_memories/SD_DAT1 )
)
( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M}
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 /Non_volatile_memories/FRB_N )
( 7 /Non_volatile_memories/FRB_N )
( 8 ? )
( 9 ? )
( 10 ? )
( 11 ? )
( 12 3.3V )
( 13 GND )
( 14 ? )
( 15 ? )
( 16 ? )
( 17 ? )
( 18 ? )
( 19 3.3V )
( 20 ? )
( 21 ? )
( 22 ? )
( 23 ? )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 ? )
( 32 ? )
( 33 ? )
( 34 ? )
( 35 ? )
( 36 GND )
( 37 3.3V )
( 38 ? )
( 39 ? )
( 40 ? )
( 41 ? )
( 42 ? )
( 43 ? )
( 44 ? )
( 45 ? )
( 46 ? )
( 47 ? )
( 48 ? )
)
( /4C421DD3/4C61D1D4 1206 C34 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61D151 1206 C33 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP}
( 1 +2.5V )
( 2 GND )
)
( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R}
( 1 +2.5V )
( 2 N-000044 )
)
( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R}
( 1 N-000044 )
( 2 N-000043 )
)
( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R}
( 1 N-000045 )
( 2 N-000047 )
)
( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R}
( 1 +2.5V )
( 2 N-000045 )
)
( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP}
( 1 +2.5V )
( 2 N-000044 )
)
( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP}
( 1 N-000044 )
( 2 N-000043 )
)
( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP}
( 1 N-000045 )
( 2 N-000047 )
)
( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP}
( 1 +2.5V )
( 2 N-000045 )
)
( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /DDR_Banks/M1_DQ0 )
( 3 +2.5V )
( 4 /FPGA_Spartan6/M1_DQ1 )
( 5 /FPGA_Spartan6/M1_DQ2 )
( 6 GND )
( 7 /DDR_Banks/M1_DQ3 )
( 8 /FPGA_Spartan6/M1_DQ4 )
( 9 +2.5V )
( 10 /DDR_Banks/M1_DQ5 )
( 11 /DDR_Banks/M1_DQ6 )
( 12 GND )
( 13 /FPGA_Spartan6/M1_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /FPGA_Spartan6/M1_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /DDR_Banks/M1_LDM )
( 21 /FPGA_Spartan6/M1_WE# )
( 22 /DDR_Banks/M1_CAS# )
( 23 /DDR_Banks/M1_RAS# )
( 24 GND )
( 25 ? )
( 26 /DDR_Banks/M1_BA0 )
( 27 /FPGA_Spartan6/M1_BA1 )
( 28 /DDR_Banks/M1_A10 )
( 29 /FPGA_Spartan6/M1_A0 )
( 30 /FPGA_Spartan6/M1_A1 )
( 31 /FPGA_Spartan6/M1_A2 )
( 32 /FPGA_Spartan6/M1_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /DDR_Banks/M1_A4 )
( 36 /DDR_Banks/M1_A5 )
( 37 /DDR_Banks/M1_A6 )
( 38 /FPGA_Spartan6/M1_A7 )
( 39 /FPGA_Spartan6/M1_A8 )
( 40 /DDR_Banks/M1_A9 )
( 41 /DDR_Banks/M1_A11 )
( 42 /FPGA_Spartan6/M1_A12 )
( 43 ? )
( 44 /FPGA_Spartan6/M1_CLK# )
( 45 /DDR_Banks/M1_CKE )
( 46 /FPGA_Spartan6/M1_CLK )
( 47 /FPGA_Spartan6/M1_UDM )
( 48 GND )
( 49 N-000044 )
( 50 ? )
( 51 /FPGA_Spartan6/M1_UDQS )
( 52 GND )
( 53 ? )
( 54 /FPGA_Spartan6/M1_DQ8 )
( 55 +2.5V )
( 56 /FPGA_Spartan6/M1_DQ9 )
( 57 /FPGA_Spartan6/M1_DQ10 )
( 58 GND )
( 59 /FPGA_Spartan6/M1_DQ11 )
( 60 /FPGA_Spartan6/M1_DQ12 )
( 61 +2.5V )
( 62 /DDR_Banks/M1_DQ13 )
( 63 /FPGA_Spartan6/M1_DQ14 )
( 64 GND )
( 65 /FPGA_Spartan6/M1_DQ15 )
( 66 GND )
)
( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG}
( 1 +2.5V )
( 2 /FPGA_Spartan6/M0_DQ0 )
( 3 +2.5V )
( 4 /FPGA_Spartan6/M0_DQ1 )
( 5 /FPGA_Spartan6/M0_DQ2 )
( 6 GND )
( 7 /FPGA_Spartan6/M0_DQ3 )
( 8 /FPGA_Spartan6/M0_DQ4 )
( 9 +2.5V )
( 10 /DDR_Banks/M0_DQ5 )
( 11 /DDR_Banks/M0_DQ6 )
( 12 GND )
( 13 /FPGA_Spartan6/M0_DQ7 )
( 14 ? )
( 15 +2.5V )
( 16 /DDR_Banks/M0_LDQS )
( 17 ? )
( 18 +2.5V )
( 19 ? )
( 20 /DDR_Banks/M0_LDM )
( 21 /FPGA_Spartan6/M0_WE# )
( 22 /FPGA_Spartan6/M0_CAS# )
( 23 /FPGA_Spartan6/M0_RAS# )
( 24 GND )
( 25 ? )
( 26 /DDR_Banks/M0_BA0 )
( 27 /FPGA_Spartan6/M0_BA1 )
( 28 /DDR_Banks/M0_A10 )
( 29 /FPGA_Spartan6/M0_A0 )
( 30 /FPGA_Spartan6/M0_A1 )
( 31 /FPGA_Spartan6/M0_A2 )
( 32 /FPGA_Spartan6/M0_A3 )
( 33 +2.5V )
( 34 GND )
( 35 /FPGA_Spartan6/M0_A4 )
( 36 /DDR_Banks/M0_A5 )
( 37 /FPGA_Spartan6/M0_A6 )
( 38 /DDR_Banks/M0_A7 )
( 39 /FPGA_Spartan6/M0_A8 )
( 40 /FPGA_Spartan6/M0_A9 )
( 41 /FPGA_Spartan6/M0_A11 )
( 42 /FPGA_Spartan6/M0_A12 )
( 43 ? )
( 44 /FPGA_Spartan6/M0_CLK# )
( 45 /FPGA_Spartan6/M0_CKE )
( 46 /DDR_Banks/M0_CLK )
( 47 /DDR_Banks/M0_UDM )
( 48 GND )
( 49 N-000045 )
( 50 ? )
( 51 /DDR_Banks/M0_UDQS )
( 52 GND )
( 53 ? )
( 54 /FPGA_Spartan6/M0_DQ8 )
( 55 +2.5V )
( 56 /DDR_Banks/M0_DQ9 )
( 57 /DDR_Banks/M0_DQ10 )
( 58 GND )
( 59 /FPGA_Spartan6/M0_DQ11 )
( 60 /FPGA_Spartan6/M0_DQ12 )
( 61 +2.5V )
( 62 /DDR_Banks/M0_DQ13 )
( 63 /FPGA_Spartan6/M0_DQ14 )
( 64 GND )
( 65 /FPGA_Spartan6/M0_DQ15 )
( 66 GND )
)
)
*
{ Allowed footprints by component:
$component R10
R?
SM0603
SM0805
R?-*
$endlist
$component C16
SM*
C?
C1-1
$endlist
$component C15
SM*
C?
C1-1
$endlist
$component C14
SM*
C?
C1-1
$endlist
$component C13
SM*
C?
C1-1
$endlist
$component C9
SM*
C?
C1-1
$endlist
$component C6
SM*
C?
C1-1
$endlist
$component C4
SM*
C?
C1-1
$endlist
$component C2
SM*
C?
C1-1
$endlist
$component C8
SM*
C?
C1-1
$endlist
$component C7
SM*
C?
C1-1
$endlist
$component C5
SM*
C?
C1-1
$endlist
$component C3
SM*
C?
C1-1
$endlist
$component C1
SM*
C?
C1-1
$endlist
$component R1
R?
SM0603
SM0805
R?-*
$endlist
$component R2
R?
SM0603
SM0805
R?-*
$endlist
$component C11
SM*
C?
C1-1
$endlist
$component C10
SM*
C?
C1-1
$endlist
$component C12
SM*
C?
C1-1
$endlist
$component R9
R?
SM0603
SM0805
R?-*
$endlist
$component R3
R?
SM0603
SM0805
R?-*
$endlist
$component R4
R?
SM0603
SM0805
R?-*
$endlist
$component R6
R?
SM0603
SM0805
R?-*
$endlist
$component R5
R?
SM0603
SM0805
R?-*
$endlist
$component R8
R?
SM0603
SM0805
R?-*
$endlist
$component R7
R?
SM0603
SM0805
R?-*
$endlist
$component C34
SM*
C?
C1-1
$endlist
$component C33
SM*
C?
C1-1
$endlist
$component C28
SM*
C?
C1-1
$endlist
$component C29
SM*
C?
C1-1
$endlist
$component C31
SM*
C?
C1-1
$endlist
$component C30
SM*
C?
C1-1
$endlist
$component C32
SM*
C?
C1-1
$endlist
$component C27
SM*
C?
C1-1
$endlist
$component C21
SM*
C?
C1-1
$endlist
$component C26
SM*
C?
C1-1
$endlist
$component C24
SM*
C?
C1-1
$endlist
$component C25
SM*
C?
C1-1
$endlist
$component C23
SM*
C?
C1-1
$endlist
$component C22
SM*
C?
C1-1
$endlist
$component R13
R?
SM0603
SM0805
R?-*
$endlist
$component R14
R?
SM0603
SM0805
R?-*
$endlist
$component R12
R?
SM0603
SM0805
R?-*
$endlist
$component R11
R?
SM0603
SM0805
R?-*
$endlist
$component C19
SM*
C?
C1-1
$endlist
$component C20
SM*
C?
C1-1
$endlist
$component C18
SM*
C?
C1-1
$endlist
$component C17
SM*
C?
C1-1
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 1 "/FPGA Spartan6/ETH_CLK" "ETH_CLK"
U4 46
U1 C10
Net 2 "/FPGA Spartan6/M0_CAS#" "M0_CAS#"
U1 K4
U2 22
Net 3 "/FPGA Spartan6/M1_WE#" "M1_WE#"
U1 H19
U3 21
Net 4 "/DDR Banks/M1_RAS#" "M1_RAS#"
U1 H21
U3 23
Net 5 "/FPGA Spartan6/M0_RAS#" "M0_RAS#"
U1 K5
U2 23
Net 6 "/FPGA Spartan6/M0_WE#" "M0_WE#"
U1 F2
U2 21
Net 8 "/Non volatile memories/SD_CMD" "SD_CMD"
J1 3
U1 C17
Net 9 "/Non volatile memories/SD_CLK" "SD_CLK"
U1 A16
J1 5
Net 10 "/Ethernet Phy/ETH_INT" "ETH_INT"
U1 A4
U4 25
Net 11 "/Ethernet Phy/ETH_TXER" "ETH_TXER"
U1 A8
U4 14
Net 12 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN"
U4 16
U1 D9
Net 13 "/Ethernet Phy/ETH_TXC" "ETH_TXC"
U4 15
U1 D8
Net 14 "/Ethernet Phy/ETH_RXER" "ETH_RXER"
U1 B8
U4 11
Net 15 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV"
U4 9
U1 A7
Net 16 "/Ethernet Phy/ETH_MDC" "ETH_MDC"
U1 C5
U4 2
Net 17 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO"
U4 1
U1 A5
R1 1
Net 18 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N"
U4 48
U1 D6
Net 19 "/Ethernet Phy/ETH_RXC" "ETH_RXC"
U1 D10
U4 10
Net 20 "/Ethernet Phy/ETH_COL" "ETH_COL"
U4 21
U1 A10
Net 21 "/Ethernet Phy/ETH_CRS" "ETH_CRS"
U4 22
U1 B10
Net 22 "/FPGA Spartan6/M1_UDM" "M1_UDM"
U3 47
U1 M20
Net 23 "/FPGA Spartan6/M1_LDQS" "M1_LDQS"
U1 L20
U3 16
Net 24 "/DDR Banks/M1_LDM" "M1_LDM"
U1 L19
U3 20
Net 25 "/FPGA Spartan6/M1_UDQS" "M1_UDQS"
U1 T21
U3 51
Net 26 "/DDR Banks/M0_UDQS" "M0_UDQS"
U1 T2
U2 51
Net 27 "/DDR Banks/M0_LDM" "M0_LDM"
U1 L4
U2 20
Net 28 "/DDR Banks/M1_CAS#" "M1_CAS#"
U3 22
U1 H22
Net 29 "/DDR Banks/M1_CKE" "M1_CKE"
U3 45
U1 D21
Net 30 "GND" "GND"
U2 66
U1 B5
U3 66
U1 M12
U3 48
U1 J15
U3 58
U3 52
U2 34
U2 64
U2 24
U2 58
U1 AB1
U2 48
U3 12
U2 6
U3 6
U1 J13
U1 A22
U4 39
U1 P14
U1 V14
U1 E15
U1 H7
U4 36
U1 B13
U1 G5
U3 24
U3 34
U3 64
U1 L5
U1 P12
U4 35
U1 R5
U1 E7
U1 AA17
U1 AA5
U1 W16
U1 B17
U1 N17
U1 D18
U1 G18
U1 L18
U1 R18
U1 W19
U1 AA9
U1 AB22
U1 AA13
J1 CASE
U2 52
U2 12
U1 A1
U1 E2
U1 J2
U1 N2
U1 U2
U1 D4
U1 V4
J1 6
J1 COM
J1 CASE
J1 CASE
U5 36
U5 13
U1 L11
U4 44
U1 N11
C3 2
U4 23
U1 E21
U1 J21
U4 12
C1 2
U1 N21
U1 U21
U1 L13
U1 U7
U1 W7
C2 2
U1 P10
U1 V10
U1 J11
R9 2
U1 N13
C8 2
U4 8
C12 2
C7 2
C10 2
C5 2
C11 2
R2 2
C21 2
C27 2
C32 2
C30 2
C31 2
C33 2
C22 2
C23 2
C25 2
C24 2
C26 2
C28 2
C29 2
U1 N9
C34 2
U1 B9
U1 J9
U1 L9
J4 5
U6 8
U6 7
U1 K14
C13 2
C14 2
C15 2
V2 2
V1 2
C16 2
R10 2
U1 M14
J4 4
L5 2
U1 K10
U1 M10
Net 31 "/FPGA Spartan6/M0_CKE" "M0_CKE"
U2 45
U1 D2
Net 32 "/DDR Banks/M0_LDQS" "M0_LDQS"
U1 L3
U2 16
Net 33 "/DDR Banks/M0_UDM" "M0_UDM"
U2 47
U1 M3
Net 34 "/FPGA Spartan6/USBA_VP" "USBA_VP"
U1 B18
U6 4
Net 35 "/USB/USBA_RCV" "USBA_RCV"
U6 3
U1 A18
Net 36 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N"
U6 9
U1 E16
Net 37 "/USB/USBA_SPD" "USBA_SPD"
U6 2
U1 D17
Net 38 "/FPGA Spartan6/M0_CLK#" "M0_CLK#"
U1 H3
U2 44
Net 39 "/DDR Banks/M0_CLK" "M0_CLK"
U1 H4
U2 46
Net 40 "/FPGA Spartan6/M1_CLK#" "M1_CLK#"
U3 44
U1 J19
Net 41 "/FPGA Spartan6/M1_CLK" "M1_CLK"
U1 H20
U3 46
Net 42 "/FPGA Spartan6/USBA_VM" "USBA_VM"
U1 A17
U6 5
Net 43 "" ""
C20 2
R14 2
Net 44 "" ""
R13 2
R14 1
C19 2
U3 49
C20 1
Net 45 "" ""
C18 1
R12 1
C17 2
R11 2
U2 49
Net 46 "+2.5V" "+2.5V"
U1 N8
U1 G2
U1 L16
U1 R10
U1 C2
U1 F11
U1 H9
U1 L8
U3 15
U1 L2
U1 E19
U1 U18
U1 G21
U1 N18
U1 J18
C33 1
U3 3
U1 W21
U1 R2
U3 55
U1 U11
U1 D16
U1 W2
U1 R21
U1 L21
U1 G12
U3 18
U1 R12
U3 33
U2 61
C22 1
C23 1
U3 61
C25 1
U2 33
C24 1
C28 1
C26 1
U2 1
C34 1
U2 3
U2 9
U1 C21
C31 1
C30 1
C32 1
R11 1
R13 1
U1 M15
U1 K15
U3 9
U1 N5
U6 1
U1 U5
U1 V6
U2 15
C19 1
U1 F4
U1 F6
U1 J5
C29 1
U1 H15
U1 L7
U3 1
C17 1
C27 1
U2 18
C21 1
U2 55
U1 R6
Net 47 "" ""
C18 2
R12 2
Net 93 "/Non volatile memories/FRB_N" "FRB_N"
U5 7
U5 6
Net 94 "3.3V" "3.3V"
L2 1
U4 7
J4 11
C5 1
C10 1
J4 9
J4 6
R5 1
U6 12
J4 3
R3 1
R4 1
U6 14
R6 1
R1 2
U5 37
U5 19
U5 12
C11 1
C1 1
U4 24
C3 1
Net 98 "+1.2V" "+1.2V"
U1 P9
U1 R14
U1 P11
U1 N14
U1 L10
U1 N10
U1 L12
U1 J8
U1 K13
U1 K9
U1 J12
U1 M9
U1 L14
U1 J14
U1 M11
U1 P13
U1 M13
U1 N12
U1 K11
U1 J10
Net 100 "+3.3V" "+3.3V"
U1 E9
U1 G10
U1 B4
U1 B11
U1 E13
U1 G14
U1 B15
U1 B7
U1 B19
U1 E17
Net 101 "" ""
U1 V12
U1 AA7
U1 T13
U1 T9
U1 AA11
U1 W5
U1 V16
U1 V8
U1 AA3
U1 AA15
U1 AA19
Net 333 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
R7 2
U4 26
Net 334 "" ""
J4 1
U4 41
R3 2
Net 335 "" ""
U4 33
J4 7
R5 2
Net 336 "" ""
R9 1
C12 1
J4 13
J4 14
Net 337 "" ""
R7 1
J4 10
Net 338 "" ""
L1 1
C4 1
Net 339 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V"
C2 1
U4 13
Net 340 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
L3 2
C9 1
U4 47
Net 343 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
U4 31
L1 2
L3 1
C6 1
Net 344 "" ""
R2 1
U4 37
Net 345 "" ""
J4 8
U4 32
R6 2
Net 346 "" ""
U4 40
R4 2
J4 2
Net 347 "" ""
C4 2
C6 2
C9 2
Net 348 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
U4 38
L2 2
C8 1
C7 1
Net 349 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
R8 2
U4 27
Net 350 "" ""
R8 1
J4 12
Net 356 "" ""
V2 1
U6 10
J5 2
V2 1
Net 357 "" ""
F1 1
L4 1
Net 358 "" ""
J5 4
L5 1
Net 360 "" ""
J5 3
U6 11
V1 1
V1 1
Net 361 "" ""
J5 S4
J5 S3
R10 1
C16 1
J5 S2
J5 S1
Net 362 "" ""
L4 2
J5 1
Net 363 "" ""
C13 1
C14 1
C15 1
Net 371 "/FPGA Spartan6/SD_DAT3" "SD_DAT3"
J1 2
U1 A15
Net 372 "/Non volatile memories/SD_DAT2" "SD_DAT2"
U1 D15
J1 1
Net 373 "/Non volatile memories/SD_DAT1" "SD_DAT1"
J1 8
U1 C16
Net 374 "/Non volatile memories/SD_DAT0" "SD_DAT0"
U1 B16
J1 7
Net 375 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3"
U1 D7
U4 20
Net 376 "/FPGA Spartan6/M1_BA1" "M1_BA1"
U1 K17
U3 27
Net 377 "/DDR Banks/M1_BA0" "M1_BA0"
U3 26
U1 J17
Net 378 "/FPGA Spartan6/M0_BA1" "M0_BA1"
U1 G1
U2 27
Net 379 "/DDR Banks/M0_BA0" "M0_BA0"
U1 G3
U2 26
Net 389 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3"
U1 C6
U4 3
Net 390 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2"
U4 4
U1 B6
Net 391 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1"
U1 A6
U4 5
Net 392 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0"
U1 C7
U4 6
Net 393 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2"
U4 19
U1 A9
Net 394 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1"
U1 C9
U4 18
Net 395 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0"
U4 17
U1 C8
Net 396 "/DDR Banks/M1_A9" "M1_A9"
U1 C22
U3 40
Net 397 "/FPGA Spartan6/M1_A8" "M1_A8"
U3 39
U1 C20
Net 398 "/FPGA Spartan6/M1_A7" "M1_A7"
U1 E20
U3 38
Net 399 "/DDR Banks/M1_A6" "M1_A6"
U1 K19
U3 37
Net 400 "/DDR Banks/M1_A5" "M1_A5"
U1 K20
U3 36
Net 401 "/DDR Banks/M1_A4" "M1_A4"
U1 F20
U3 35
Net 402 "/FPGA Spartan6/M1_A3" "M1_A3"
U3 32
U1 G20
Net 403 "/FPGA Spartan6/M1_A2" "M1_A2"
U3 31
U1 E22
Net 404 "/FPGA Spartan6/M1_A1" "M1_A1"
U3 30
U1 F22
Net 405 "/FPGA Spartan6/M1_A0" "M1_A0"
U3 29
U1 F21
Net 406 "/FPGA Spartan6/M0_A12" "M0_A12"
U1 D1
U2 42
Net 407 "/FPGA Spartan6/M1_DQ15" "M1_DQ15"
U3 65
U1 V22
Net 408 "/FPGA Spartan6/M1_DQ14" "M1_DQ14"
U1 V21
U3 63
Net 409 "/DDR Banks/M1_DQ13" "M1_DQ13"
U3 62
U1 U22
Net 410 "/FPGA Spartan6/M1_DQ12" "M1_DQ12"
U3 60
U1 U20
Net 411 "/FPGA Spartan6/M1_DQ11" "M1_DQ11"
U3 59
U1 R22
Net 412 "/FPGA Spartan6/M1_DQ10" "M1_DQ10"
U1 R20
U3 57
Net 413 "/FPGA Spartan6/M1_DQ9" "M1_DQ9"
U3 56
U1 P22
Net 414 "/FPGA Spartan6/M1_DQ8" "M1_DQ8"
U3 54
U1 P21
Net 415 "/FPGA Spartan6/M1_DQ7" "M1_DQ7"
U1 K22
U3 13
Net 416 "/DDR Banks/M1_DQ6" "M1_DQ6"
U3 11
U1 K21
Net 417 "/DDR Banks/M1_DQ5" "M1_DQ5"
U3 10
U1 J22
Net 418 "/FPGA Spartan6/M1_DQ4" "M1_DQ4"
U3 8
U1 J20
Net 419 "/DDR Banks/M1_DQ3" "M1_DQ3"
U3 7
U1 M22
Net 420 "/FPGA Spartan6/M1_DQ2" "M1_DQ2"
U3 5
U1 M21
Net 421 "/FPGA Spartan6/M1_DQ1" "M1_DQ1"
U1 N22
U3 4
Net 422 "/DDR Banks/M1_DQ0" "M1_DQ0"
U3 2
U1 N20
Net 423 "/FPGA Spartan6/M1_A12" "M1_A12"
U3 42
U1 D22
Net 424 "/DDR Banks/M1_A11" "M1_A11"
U1 F19
U3 41
Net 425 "/DDR Banks/M1_A10" "M1_A10"
U3 28
U1 G19
Net 426 "/DDR Banks/M0_DQ10" "M0_DQ10"
U2 57
U1 R3
Net 427 "/DDR Banks/M0_DQ9" "M0_DQ9"
U2 56
U1 P1
Net 428 "/FPGA Spartan6/M0_DQ8" "M0_DQ8"
U2 54
U1 P2
Net 429 "/FPGA Spartan6/M0_DQ7" "M0_DQ7"
U1 K1
U2 13
Net 430 "/DDR Banks/M0_DQ6" "M0_DQ6"
U2 11
U1 K2
Net 431 "/DDR Banks/M0_DQ5" "M0_DQ5"
U1 J1
U2 10
Net 432 "/FPGA Spartan6/M0_DQ4" "M0_DQ4"
U2 8
U1 J3
Net 433 "/FPGA Spartan6/M0_DQ3" "M0_DQ3"
U2 7
U1 M1
Net 434 "/FPGA Spartan6/M0_DQ2" "M0_DQ2"
U2 5
U1 M2
Net 435 "/FPGA Spartan6/M0_DQ1" "M0_DQ1"
U2 4
U1 N1
Net 436 "/FPGA Spartan6/M0_DQ0" "M0_DQ0"
U1 N3
U2 2
Net 437 "/FPGA Spartan6/M0_A11" "M0_A11"
U1 C1
U2 41
Net 438 "/DDR Banks/M0_A10" "M0_A10"
U2 28
U1 G4
Net 439 "/FPGA Spartan6/M0_A9" "M0_A9"
U2 40
U1 E1
Net 440 "/FPGA Spartan6/M0_A8" "M0_A8"
U2 39
U1 E3
Net 441 "/DDR Banks/M0_A7" "M0_A7"
U1 H6
U2 38
Net 442 "/FPGA Spartan6/M0_A6" "M0_A6"
U1 J4
U2 37
Net 443 "/DDR Banks/M0_A5" "M0_A5"
U1 K3
U2 36
Net 444 "/FPGA Spartan6/M0_A4" "M0_A4"
U1 F3
U2 35
Net 445 "/FPGA Spartan6/M0_A3" "M0_A3"
U1 K6
U2 32
Net 446 "/FPGA Spartan6/M0_A2" "M0_A2"
U1 H5
U2 31
Net 447 "/FPGA Spartan6/M0_A1" "M0_A1"
U2 30
U1 H1
Net 448 "/FPGA Spartan6/M0_A0" "M0_A0"
U1 H2
U2 29
Net 449 "/FPGA Spartan6/M0_DQ15" "M0_DQ15"
U2 65
U1 V1
Net 450 "/FPGA Spartan6/M0_DQ14" "M0_DQ14"
U1 V2
U2 63
Net 451 "/DDR Banks/M0_DQ13" "M0_DQ13"
U1 U1
U2 62
Net 452 "/FPGA Spartan6/M0_DQ12" "M0_DQ12"
U1 U3
U2 60
Net 453 "/FPGA Spartan6/M0_DQ11" "M0_DQ11"
U1 R1
U2 59
}
#End
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