Sorta does something
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# Generated from CLion C/C++ Code Style settings
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BasedOnStyle: LLVM
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AccessModifierOffset: -2
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AccessModifierOffset: 0
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AlignAfterOpenBracket: Align
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AlignConsecutiveAssignments: None
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AlignOperands: Align
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@ -38,7 +38,7 @@ CompactNamespaces: false
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ContinuationIndentWidth: 8
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IndentCaseLabels: true
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IndentPPDirectives: None
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IndentWidth: 2
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IndentWidth: 4
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KeepEmptyLinesAtTheStartOfBlocks: true
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MaxEmptyLinesToKeep: 2
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NamespaceIndentation: All
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@ -63,4 +63,4 @@ SpacesInContainerLiterals: false
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SpacesInParentheses: false
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SpacesInSquareBrackets: false
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TabWidth: 4
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UseTab: ForContinuationAndIndentation
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UseTab: Always
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@ -1,424 +1,424 @@
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/*********************************************************************
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* SEGGER Microcontroller GmbH *
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* The Embedded Experts *
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**********************************************************************
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* *
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* (c) 1995 - 2020 SEGGER Microcontroller GmbH *
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* *
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* www.segger.com Support: support@segger.com *
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* *
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**********************************************************************
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* *
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* SEGGER RTT * Real Time Transfer for embedded targets *
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* *
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**********************************************************************
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* *
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* All rights reserved. *
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* *
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* SEGGER strongly recommends to not make any changes *
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* to or modify the source code of this software in order to stay *
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* compatible with the RTT protocol and J-Link. *
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* *
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* Redistribution and use in source and binary forms, with or *
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* without modification, are permitted provided that the following *
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* condition is met: *
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* *
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* o Redistributions of source code must retain the above copyright *
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* notice, this condition and the following disclaimer. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
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* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
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* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
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* DAMAGE. *
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* *
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**********************************************************************
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---------------------------END-OF-HEADER------------------------------
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File : SEGGER_RTT_Conf.h
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Purpose : Implementation of SEGGER real-time transfer (RTT) which
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allows real-time communication on targets which support
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debugger memory accesses while the CPU is running.
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Revision: $Rev: 21386 $
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*/
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#ifndef SEGGER_RTT_CONF_H
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#define SEGGER_RTT_CONF_H
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#ifdef __IAR_SYSTEMS_ICC__
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#include <intrinsics.h>
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#endif
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/*********************************************************************
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*
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* Defines, configurable
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*
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**********************************************************************
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*/
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//
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// Take in and set to correct values for Cortex-A systems with CPU cache
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//
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//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system
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//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached
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//
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// Most common case:
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// Up-channel 0: RTT
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// Up-channel 1: SystemView
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//
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#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS
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#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3)
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#endif
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//
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// Most common case:
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// Down-channel 0: RTT
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// Down-channel 1: SystemView
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//
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#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
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#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3)
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#endif
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#ifndef BUFFER_SIZE_UP
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#define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k)
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#endif
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#ifndef BUFFER_SIZE_DOWN
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#define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
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#endif
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#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE
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#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64)
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#endif
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#ifndef SEGGER_RTT_MODE_DEFAULT
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#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0)
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#endif
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/*********************************************************************
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*
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* RTT memcpy configuration
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*
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* memcpy() is good for large amounts of data,
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* but the overhead is big for small amounts, which are usually stored via RTT.
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* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead.
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*
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* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions.
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* This is may be required with memory access restrictions,
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* such as on Cortex-A devices with MMU.
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*/
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#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP
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#define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop
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#endif
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//
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// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets
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//
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//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))
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// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes))
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//#endif
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//
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// Target is not allowed to perform other RTT operations while string still has not been stored completely.
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// Otherwise we would probably end up with a mixed string in the buffer.
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// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
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//
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// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4.
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// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches.
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// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly.
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// (Higher priority = lower priority number)
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// Default value for embOS: 128u
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// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC
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// or define SEGGER_RTT_LOCK() to completely disable interrupts.
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//
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#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
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#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20)
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#endif
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/*********************************************************************
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*
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* RTT lock configuration for SEGGER Embedded Studio,
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* Rowley CrossStudio and GCC
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*/
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#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32))
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#if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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__asm volatile ("mrs %0, primask \n\t" \
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"movs r1, #1 \n\t" \
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"msr primask, r1 \n\t" \
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: "=r" (_SEGGER_RTT__LockState) \
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: \
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: "r1", "cc" \
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);
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#define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \
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: \
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: "r" (_SEGGER_RTT__LockState) \
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: \
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); \
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}
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#elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__))
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#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
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#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
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#endif
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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__asm volatile ("mrs %0, basepri \n\t" \
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"mov r1, %1 \n\t" \
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"msr basepri, r1 \n\t" \
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: "=r" (_SEGGER_RTT__LockState) \
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: "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \
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: "r1", "cc" \
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);
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#define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \
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: \
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: "r" (_SEGGER_RTT__LockState) \
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: \
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); \
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}
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#elif defined(__ARM_ARCH_7A__)
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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__asm volatile ("mrs r1, CPSR \n\t" \
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"mov %0, r1 \n\t" \
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"orr r1, r1, #0xC0 \n\t" \
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"msr CPSR_c, r1 \n\t" \
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: "=r" (_SEGGER_RTT__LockState) \
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: \
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: "r1", "cc" \
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);
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#define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
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"mrs r1, CPSR \n\t" \
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"bic r1, r1, #0xC0 \n\t" \
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"and r0, r0, #0xC0 \n\t" \
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"orr r1, r1, r0 \n\t" \
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"msr CPSR_c, r1 \n\t" \
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: \
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: "r" (_SEGGER_RTT__LockState) \
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: "r0", "r1", "cc" \
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); \
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}
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#elif defined(__riscv) || defined(__riscv_xlen)
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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__asm volatile ("csrr %0, mstatus \n\t" \
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"csrci mstatus, 8 \n\t" \
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"andi %0, %0, 8 \n\t" \
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: "=r" (_SEGGER_RTT__LockState) \
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: \
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: \
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);
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#define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \
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"or %0, %0, a1 \n\t" \
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"csrs mstatus, %0 \n\t" \
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: \
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: "r" (_SEGGER_RTT__LockState) \
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: "a1" \
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); \
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}
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#else
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#define SEGGER_RTT_LOCK()
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#define SEGGER_RTT_UNLOCK()
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#endif
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#endif
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/*********************************************************************
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*
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* RTT lock configuration for IAR EWARM
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*/
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#ifdef __ICCARM__
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#if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \
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(defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__))
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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_SEGGER_RTT__LockState = __get_PRIMASK(); \
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__set_PRIMASK(1);
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#define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
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}
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#elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \
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(defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \
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(defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \
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(defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__))
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#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
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#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
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#endif
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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_SEGGER_RTT__LockState = __get_BASEPRI(); \
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__set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
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#define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \
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}
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#elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \
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(defined (__ARM7R__) && (__CORE__ == __ARM7R__))
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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__asm volatile ("mrs r1, CPSR \n\t" \
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"mov %0, r1 \n\t" \
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"orr r1, r1, #0xC0 \n\t" \
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"msr CPSR_c, r1 \n\t" \
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: "=r" (_SEGGER_RTT__LockState) \
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: \
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: "r1", "cc" \
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);
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#define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
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"mrs r1, CPSR \n\t" \
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"bic r1, r1, #0xC0 \n\t" \
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"and r0, r0, #0xC0 \n\t" \
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"orr r1, r1, r0 \n\t" \
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"msr CPSR_c, r1 \n\t" \
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: \
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: "r" (_SEGGER_RTT__LockState) \
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: "r0", "r1", "cc" \
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); \
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}
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#endif
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#endif
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/*********************************************************************
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*
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* RTT lock configuration for IAR RX
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*/
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#ifdef __ICCRX__
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#define SEGGER_RTT_LOCK() { \
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unsigned long _SEGGER_RTT__LockState; \
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_SEGGER_RTT__LockState = __get_interrupt_state(); \
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__disable_interrupt();
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#define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
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}
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#endif
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/*********************************************************************
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*
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* RTT lock configuration for IAR RL78
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*/
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#ifdef __ICCRL78__
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#define SEGGER_RTT_LOCK() { \
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__istate_t _SEGGER_RTT__LockState; \
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_SEGGER_RTT__LockState = __get_interrupt_state(); \
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__disable_interrupt();
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#define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
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}
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#endif
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/*********************************************************************
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*
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* RTT lock configuration for KEIL ARM
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*/
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#ifdef __CC_ARM
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#if (defined __TARGET_ARCH_6S_M)
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \
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_SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \
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_SEGGER_RTT__PRIMASK = 1u; \
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__schedule_barrier();
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#define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \
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__schedule_barrier(); \
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}
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#elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
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#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
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#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
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#endif
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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register unsigned char BASEPRI __asm( "basepri"); \
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_SEGGER_RTT__LockState = BASEPRI; \
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BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \
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__schedule_barrier();
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#define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \
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__schedule_barrier(); \
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}
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#endif
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#endif
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/*********************************************************************
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*
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* RTT lock configuration for TI ARM
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*/
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#ifdef __TI_ARM__
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#if defined (__TI_ARM_V6M0__)
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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_SEGGER_RTT__LockState = __get_PRIMASK(); \
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__set_PRIMASK(1);
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#define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
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}
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#elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__))
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#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
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#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
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#endif
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#define SEGGER_RTT_LOCK() { \
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unsigned int _SEGGER_RTT__LockState; \
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_SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
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#define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \
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}
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#endif
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#endif
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/*********************************************************************
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*
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* RTT lock configuration for CCRX
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*/
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#ifdef __RX
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#include <machine.h>
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#define SEGGER_RTT_LOCK() { \
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unsigned long _SEGGER_RTT__LockState; \
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_SEGGER_RTT__LockState = get_psw() & 0x010000; \
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clrpsw_i();
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|
||||
#define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration for embOS Simulation on Windows
|
||||
* (Can also be used for generic RTT locking with embOS)
|
||||
*/
|
||||
#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS)
|
||||
|
||||
void OS_SIM_EnterCriticalSection(void);
|
||||
void OS_SIM_LeaveCriticalSection(void);
|
||||
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
OS_SIM_EnterCriticalSection();
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration fallback
|
||||
*/
|
||||
#ifndef SEGGER_RTT_LOCK
|
||||
#define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts)
|
||||
#endif
|
||||
|
||||
#ifndef SEGGER_RTT_UNLOCK
|
||||
#define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/*************************** End of file ****************************/
|
||||
/*********************************************************************
|
||||
* SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
**********************************************************************
|
||||
* *
|
||||
* (c) 1995 - 2020 SEGGER Microcontroller GmbH *
|
||||
* *
|
||||
* www.segger.com Support: support@segger.com *
|
||||
* *
|
||||
**********************************************************************
|
||||
* *
|
||||
* SEGGER RTT * Real Time Transfer for embedded targets *
|
||||
* *
|
||||
**********************************************************************
|
||||
* *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* SEGGER strongly recommends to not make any changes *
|
||||
* to or modify the source code of this software in order to stay *
|
||||
* compatible with the RTT protocol and J-Link. *
|
||||
* *
|
||||
* Redistribution and use in source and binary forms, with or *
|
||||
* without modification, are permitted provided that the following *
|
||||
* condition is met: *
|
||||
* *
|
||||
* o Redistributions of source code must retain the above copyright *
|
||||
* notice, this condition and the following disclaimer. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
|
||||
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
|
||||
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
|
||||
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
|
||||
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
|
||||
* DAMAGE. *
|
||||
* *
|
||||
**********************************************************************
|
||||
---------------------------END-OF-HEADER------------------------------
|
||||
File : SEGGER_RTT_Conf.h
|
||||
Purpose : Implementation of SEGGER real-time transfer (RTT) which
|
||||
allows real-time communication on targets which support
|
||||
debugger memory accesses while the CPU is running.
|
||||
Revision: $Rev: 21386 $
|
||||
|
||||
*/
|
||||
|
||||
#ifndef SEGGER_RTT_CONF_H
|
||||
#define SEGGER_RTT_CONF_H
|
||||
|
||||
#ifdef __IAR_SYSTEMS_ICC__
|
||||
#include <intrinsics.h>
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Defines, configurable
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
//
|
||||
// Take in and set to correct values for Cortex-A systems with CPU cache
|
||||
//
|
||||
//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system
|
||||
//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached
|
||||
//
|
||||
// Most common case:
|
||||
// Up-channel 0: RTT
|
||||
// Up-channel 1: SystemView
|
||||
//
|
||||
#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS
|
||||
#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (1) // Max. number of up-buffers (T->H) available on this target (Default: 3)
|
||||
#endif
|
||||
//
|
||||
// Most common case:
|
||||
// Down-channel 0: RTT
|
||||
// Down-channel 1: SystemView
|
||||
//
|
||||
#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
|
||||
#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (1) // Max. number of down-buffers (H->T) available on this target (Default: 3)
|
||||
#endif
|
||||
|
||||
#ifndef BUFFER_SIZE_UP
|
||||
#define BUFFER_SIZE_UP (128) // Size of the buffer for terminal output of target, up to host (Default: 1k)
|
||||
#endif
|
||||
|
||||
#ifndef BUFFER_SIZE_DOWN
|
||||
#define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
|
||||
#endif
|
||||
|
||||
#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE
|
||||
#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64)
|
||||
#endif
|
||||
|
||||
#ifndef SEGGER_RTT_MODE_DEFAULT
|
||||
#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0)
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT memcpy configuration
|
||||
*
|
||||
* memcpy() is good for large amounts of data,
|
||||
* but the overhead is big for small amounts, which are usually stored via RTT.
|
||||
* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead.
|
||||
*
|
||||
* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions.
|
||||
* This is may be required with memory access restrictions,
|
||||
* such as on Cortex-A devices with MMU.
|
||||
*/
|
||||
#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP
|
||||
#define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop
|
||||
#endif
|
||||
//
|
||||
// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets
|
||||
//
|
||||
//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))
|
||||
// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes))
|
||||
//#endif
|
||||
|
||||
//
|
||||
// Target is not allowed to perform other RTT operations while string still has not been stored completely.
|
||||
// Otherwise we would probably end up with a mixed string in the buffer.
|
||||
// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
|
||||
//
|
||||
// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4.
|
||||
// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches.
|
||||
// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly.
|
||||
// (Higher priority = lower priority number)
|
||||
// Default value for embOS: 128u
|
||||
// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC
|
||||
// or define SEGGER_RTT_LOCK() to completely disable interrupts.
|
||||
//
|
||||
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
|
||||
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20)
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration for SEGGER Embedded Studio,
|
||||
* Rowley CrossStudio and GCC
|
||||
*/
|
||||
#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32))
|
||||
#if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
__asm volatile ("mrs %0, primask \n\t" \
|
||||
"movs r1, #1 \n\t" \
|
||||
"msr primask, r1 \n\t" \
|
||||
: "=r" (_SEGGER_RTT__LockState) \
|
||||
: \
|
||||
: "r1", "cc" \
|
||||
);
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \
|
||||
: \
|
||||
: "r" (_SEGGER_RTT__LockState) \
|
||||
: \
|
||||
); \
|
||||
}
|
||||
#elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__))
|
||||
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
|
||||
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
|
||||
#endif
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
__asm volatile ("mrs %0, basepri \n\t" \
|
||||
"mov r1, %1 \n\t" \
|
||||
"msr basepri, r1 \n\t" \
|
||||
: "=r" (_SEGGER_RTT__LockState) \
|
||||
: "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \
|
||||
: "r1", "cc" \
|
||||
);
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \
|
||||
: \
|
||||
: "r" (_SEGGER_RTT__LockState) \
|
||||
: \
|
||||
); \
|
||||
}
|
||||
|
||||
#elif defined(__ARM_ARCH_7A__)
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
__asm volatile ("mrs r1, CPSR \n\t" \
|
||||
"mov %0, r1 \n\t" \
|
||||
"orr r1, r1, #0xC0 \n\t" \
|
||||
"msr CPSR_c, r1 \n\t" \
|
||||
: "=r" (_SEGGER_RTT__LockState) \
|
||||
: \
|
||||
: "r1", "cc" \
|
||||
);
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
|
||||
"mrs r1, CPSR \n\t" \
|
||||
"bic r1, r1, #0xC0 \n\t" \
|
||||
"and r0, r0, #0xC0 \n\t" \
|
||||
"orr r1, r1, r0 \n\t" \
|
||||
"msr CPSR_c, r1 \n\t" \
|
||||
: \
|
||||
: "r" (_SEGGER_RTT__LockState) \
|
||||
: "r0", "r1", "cc" \
|
||||
); \
|
||||
}
|
||||
#elif defined(__riscv) || defined(__riscv_xlen)
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
__asm volatile ("csrr %0, mstatus \n\t" \
|
||||
"csrci mstatus, 8 \n\t" \
|
||||
"andi %0, %0, 8 \n\t" \
|
||||
: "=r" (_SEGGER_RTT__LockState) \
|
||||
: \
|
||||
: \
|
||||
);
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \
|
||||
"or %0, %0, a1 \n\t" \
|
||||
"csrs mstatus, %0 \n\t" \
|
||||
: \
|
||||
: "r" (_SEGGER_RTT__LockState) \
|
||||
: "a1" \
|
||||
); \
|
||||
}
|
||||
#else
|
||||
#define SEGGER_RTT_LOCK()
|
||||
#define SEGGER_RTT_UNLOCK()
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration for IAR EWARM
|
||||
*/
|
||||
#ifdef __ICCARM__
|
||||
#if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \
|
||||
(defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__))
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
_SEGGER_RTT__LockState = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1);
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
|
||||
}
|
||||
#elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \
|
||||
(defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \
|
||||
(defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \
|
||||
(defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__))
|
||||
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
|
||||
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
|
||||
#endif
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
_SEGGER_RTT__LockState = __get_BASEPRI(); \
|
||||
__set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \
|
||||
}
|
||||
#elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \
|
||||
(defined (__ARM7R__) && (__CORE__ == __ARM7R__))
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
__asm volatile ("mrs r1, CPSR \n\t" \
|
||||
"mov %0, r1 \n\t" \
|
||||
"orr r1, r1, #0xC0 \n\t" \
|
||||
"msr CPSR_c, r1 \n\t" \
|
||||
: "=r" (_SEGGER_RTT__LockState) \
|
||||
: \
|
||||
: "r1", "cc" \
|
||||
);
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
|
||||
"mrs r1, CPSR \n\t" \
|
||||
"bic r1, r1, #0xC0 \n\t" \
|
||||
"and r0, r0, #0xC0 \n\t" \
|
||||
"orr r1, r1, r0 \n\t" \
|
||||
"msr CPSR_c, r1 \n\t" \
|
||||
: \
|
||||
: "r" (_SEGGER_RTT__LockState) \
|
||||
: "r0", "r1", "cc" \
|
||||
); \
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration for IAR RX
|
||||
*/
|
||||
#ifdef __ICCRX__
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned long _SEGGER_RTT__LockState; \
|
||||
_SEGGER_RTT__LockState = __get_interrupt_state(); \
|
||||
__disable_interrupt();
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration for IAR RL78
|
||||
*/
|
||||
#ifdef __ICCRL78__
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
__istate_t _SEGGER_RTT__LockState; \
|
||||
_SEGGER_RTT__LockState = __get_interrupt_state(); \
|
||||
__disable_interrupt();
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration for KEIL ARM
|
||||
*/
|
||||
#ifdef __CC_ARM
|
||||
#if (defined __TARGET_ARCH_6S_M)
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \
|
||||
_SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \
|
||||
_SEGGER_RTT__PRIMASK = 1u; \
|
||||
__schedule_barrier();
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \
|
||||
__schedule_barrier(); \
|
||||
}
|
||||
#elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
|
||||
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
|
||||
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
|
||||
#endif
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
register unsigned char BASEPRI __asm( "basepri"); \
|
||||
_SEGGER_RTT__LockState = BASEPRI; \
|
||||
BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \
|
||||
__schedule_barrier();
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \
|
||||
__schedule_barrier(); \
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration for TI ARM
|
||||
*/
|
||||
#ifdef __TI_ARM__
|
||||
#if defined (__TI_ARM_V6M0__)
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
_SEGGER_RTT__LockState = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1);
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
|
||||
}
|
||||
#elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__))
|
||||
#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
|
||||
#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
|
||||
#endif
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned int _SEGGER_RTT__LockState; \
|
||||
_SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration for CCRX
|
||||
*/
|
||||
#ifdef __RX
|
||||
#include <machine.h>
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
unsigned long _SEGGER_RTT__LockState; \
|
||||
_SEGGER_RTT__LockState = get_psw() & 0x010000; \
|
||||
clrpsw_i();
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration for embOS Simulation on Windows
|
||||
* (Can also be used for generic RTT locking with embOS)
|
||||
*/
|
||||
#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS)
|
||||
|
||||
void OS_SIM_EnterCriticalSection(void);
|
||||
void OS_SIM_LeaveCriticalSection(void);
|
||||
|
||||
#define SEGGER_RTT_LOCK() { \
|
||||
OS_SIM_EnterCriticalSection();
|
||||
|
||||
#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \
|
||||
}
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* RTT lock configuration fallback
|
||||
*/
|
||||
#ifndef SEGGER_RTT_LOCK
|
||||
#define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts)
|
||||
#endif
|
||||
|
||||
#ifndef SEGGER_RTT_UNLOCK
|
||||
#define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/*************************** End of file ****************************/
|
||||
|
||||
168
main.c
168
main.c
@ -17,6 +17,8 @@
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include <libopencm3/cm3/nvic.h>
|
||||
#include <libopencm3/stm32/rcc.h>
|
||||
#include <libopencm3/stm32/gpio.h>
|
||||
@ -24,6 +26,23 @@
|
||||
|
||||
#include <SEGGER_RTT.h>
|
||||
|
||||
#define DHT_PORT GPIOB
|
||||
#define DHT_PIN GPIO0
|
||||
|
||||
enum DHT11_STATE {
|
||||
DHT11_STOP, // Stop statemachine
|
||||
DHT11_BEGIN_START, // We drive DATA Low for min 18ms
|
||||
DHT11_END_START, // We drive DATA High and set it to input
|
||||
DHT11_RESPONSE, // Wait for DHT to drive DATA Low
|
||||
DHT11_DATA,
|
||||
DHT11_END
|
||||
};
|
||||
|
||||
int g_dht11_state = DHT11_STOP;
|
||||
|
||||
int g_dht_i = 0;
|
||||
uint16_t g_dht_vals[100] = {0};
|
||||
|
||||
static void delay(int count)
|
||||
{
|
||||
for (int i=0; i < count; i++) {
|
||||
@ -44,7 +63,7 @@ static void gpio_setup(void)
|
||||
// GPIOA_CRH = (GPIO_CNF_OUTPUT_PUSHPULL << (((5 - 8) * 4) + 2));
|
||||
// GPIOA_CRH |= (GPIO_MODE_OUTPUT_2_MHZ << ((5 - 8) * 4));
|
||||
/* Using API functions: */
|
||||
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO0);
|
||||
gpio_set_mode(DHT_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, DHT_PIN);
|
||||
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1);
|
||||
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO2);
|
||||
}
|
||||
@ -52,109 +71,148 @@ static void gpio_setup(void)
|
||||
static void tim_setup(void)
|
||||
{
|
||||
nvic_enable_irq(NVIC_TIM3_IRQ);
|
||||
nvic_set_priority(NVIC_TIM3_IRQ, 1); // interupts will not work without it???
|
||||
nvic_set_priority(NVIC_TIM3_IRQ, 1); // interrupts will not work without it???
|
||||
|
||||
rcc_periph_clock_enable(RCC_TIM3);
|
||||
rcc_periph_reset_pulse(RST_TIM3);
|
||||
|
||||
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
|
||||
timer_set_prescaler(TIM3, 1152); // set timer tickrate to 500khz
|
||||
//timer_set_oc_value(TIM3, TIM_OC1, 0x1000);
|
||||
timer_set_prescaler(TIM3, (rcc_apb1_frequency*2) / 1000000 - 1); // set timer tickrate to 1mhz
|
||||
timer_set_period(TIM3, 0xffff);
|
||||
timer_one_shot_mode(TIM3);
|
||||
//timer_one_shot_mode(TIM3);
|
||||
|
||||
timer_ic_set_input(TIM3, TIM_IC3, TIM_IC_IN_TI3);
|
||||
//timer_ic_set_filter(TIM3, TIM_IC3, 0b1111); // does not do anything ????
|
||||
//timer_ic_set_polarity(TIM3, TIM_IC3, TIM_IC_FALLING); // TIM_IC_RISING
|
||||
//timer_ic_enable(TIM3, TIM_IC3);
|
||||
|
||||
timer_enable_counter(TIM3);
|
||||
timer_enable_irq(TIM3, TIM_DIER_UIE);
|
||||
timer_enable_irq(TIM3, TIM_DIER_CC1IE); // end start condition
|
||||
timer_enable_irq(TIM3, TIM_DIER_CC3IE);
|
||||
timer_enable_irq(TIM3, TIM_DIER_CC1IE); // triggered when DHT11_END_START
|
||||
timer_enable_irq(TIM3, TIM_DIER_CC3IE); // triggered when DHT drives DATA pin
|
||||
|
||||
// start condition
|
||||
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO0);
|
||||
gpio_clear(GPIOB, GPIO0);
|
||||
}
|
||||
|
||||
enum DHT11_STATE {
|
||||
DHT11_START,
|
||||
DHT11_RESPONSE,
|
||||
DHT11_BIT0,
|
||||
DHT11_BIT1,
|
||||
DHT11_END
|
||||
};
|
||||
|
||||
int dht11_state = DHT11_START;
|
||||
|
||||
void tim3_isr(void)
|
||||
{
|
||||
// Timer overflow that should only happen if DHT11 does not answer
|
||||
if (timer_get_flag(TIM3, TIM_SR_UIF)) {
|
||||
|
||||
if (timer_get_flag(TIM3, TIM_SR_UIF)) // timer reached end
|
||||
{
|
||||
timer_clear_flag(TIM3, TIM_SR_UIF);
|
||||
//gpio_toggle(GPIOB, GPIO1);
|
||||
gpio_toggle(GPIOB, GPIO2);
|
||||
//gpio_toggle(GPIOB, GPIO2);
|
||||
if (g_dht11_state == DHT11_RESPONSE) {
|
||||
puts("no response");
|
||||
} else if (g_dht11_state == DHT11_DATA) {
|
||||
puts("got data");
|
||||
} else {
|
||||
puts("overflow");
|
||||
}
|
||||
g_dht11_state = DHT11_STOP;
|
||||
timer_disable_counter(TIM3);
|
||||
|
||||
//timer_set_counter(TIM3, 0);
|
||||
//timer_clear_flag(TIM3, TIM_SR_UIF);
|
||||
//timer_set_oc_value(TIM3, TIM_OC1, 1000);
|
||||
} else if (timer_get_flag(TIM3, TIM_SR_CC1IF))
|
||||
{
|
||||
timer_clear_flag(TIM3, TIM_SR_CC3IF);
|
||||
if (dht11_state == DHT11_START){
|
||||
gpio_set(GPIOB, GPIO0);
|
||||
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO0);
|
||||
}
|
||||
|
||||
// handle DHT11_END_START
|
||||
else if (timer_get_flag(TIM3, TIM_SR_CC1IF)) {
|
||||
timer_clear_flag(TIM3, TIM_SR_CC1IF);
|
||||
//gpio_toggle(GPIOB, GPIO2);
|
||||
if (g_dht11_state == DHT11_BEGIN_START) {
|
||||
g_dht11_state = DHT11_END_START;
|
||||
|
||||
// And make the GPIO input so that we can wait for response
|
||||
gpio_set(DHT_PORT, DHT_PIN);
|
||||
gpio_set_mode(DHT_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, DHT_PIN);
|
||||
|
||||
// setup timer to wait for start response from dht11
|
||||
timer_ic_set_polarity(TIM3, TIM_IC3, TIM_IC_FALLING); // TIM_IC_RISING
|
||||
//timer_ic_set_polarity(TIM3, TIM_IC3, TIM_IC_FALLING);// TIM_IC_RISING
|
||||
timer_ic_set_polarity(TIM3, TIM_IC3, TIM_IC_RISING);// TIM_IC_RISING
|
||||
timer_ic_enable(TIM3, TIM_IC3);
|
||||
|
||||
dht11_state = DHT11_START;
|
||||
}
|
||||
|
||||
} else if (timer_get_flag(TIM3, TIM_SR_CC3IF)) // PB0 changed value
|
||||
{
|
||||
timer_clear_flag(TIM3, TIM_SR_CC3IF);
|
||||
|
||||
|
||||
|
||||
if (timer_get_flag(TIM3, TIM_SR_CC3OF))
|
||||
{
|
||||
timer_clear_flag(TIM3, TIM_SR_CC3OF);
|
||||
timer_clear_flag(TIM3, TIM_SR_CC3IF);
|
||||
//puts("waiting for response");
|
||||
}
|
||||
gpio_toggle(GPIOB, GPIO2);
|
||||
}
|
||||
|
||||
else if (timer_get_flag(TIM3, TIM_SR_CC3IF)) // PB0 changed value
|
||||
{
|
||||
if (g_dht11_state == DHT11_END_START) {
|
||||
g_dht11_state = DHT11_RESPONSE;
|
||||
gpio_toggle(GPIOB, GPIO2);
|
||||
//timer_ic_disable(TIM3, TIM_IC3);
|
||||
//timer_clear_flag(TIM3, TIM_SR_CC3IF);
|
||||
//timer_ic_set_polarity(TIM3, TIM_IC3, TIM_IC_FALLING);// TIM_IC_RISING
|
||||
g_dht_vals[g_dht_i++] = TIM_CCR3(TIM3); // store captured high time value
|
||||
//timer_ic_enable(TIM3, TIM_IC3);
|
||||
gpio_toggle(GPIOB, GPIO2);
|
||||
} else {
|
||||
gpio_toggle(GPIOB, GPIO2);
|
||||
g_dht11_state = DHT11_DATA;
|
||||
g_dht_vals[g_dht_i] = TIM_CCR3(TIM3) - g_dht_vals[g_dht_i-1]; // store length from last sample
|
||||
g_dht_i++;
|
||||
gpio_toggle(GPIOB, GPIO2);
|
||||
}
|
||||
|
||||
// if (timer_get_flag(TIM3, TIM_SR_CC3OF))
|
||||
// {
|
||||
// timer_clear_flag(TIM3, TIM_SR_CC3OF);
|
||||
// puts("we are too slow to read and clear timer input capture flags");
|
||||
// }
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void dht_start(void)
|
||||
{
|
||||
timer_disable_counter(TIM3);
|
||||
g_dht11_state = DHT11_BEGIN_START;
|
||||
g_dht_i = 0;
|
||||
|
||||
// Setup DHT11_END_START trigger on output compare 1
|
||||
timer_set_counter(TIM3, 0);
|
||||
timer_set_oc_value(TIM3, TIM_OC1, 1000*20); // 20ms
|
||||
timer_clear_flag(TIM3, TIM_SR_CC1IF);
|
||||
|
||||
// Do DHT11_BEGIN_START aka drive DATA Low
|
||||
gpio_set_mode(DHT_PORT, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, DHT_PIN);
|
||||
gpio_clear(DHT_PORT, DHT_PIN);
|
||||
|
||||
// And start counting
|
||||
timer_enable_counter(TIM3);
|
||||
|
||||
//gpio_toggle(GPIOB, GPIO2);
|
||||
|
||||
}
|
||||
|
||||
static void dht_start_signal(void)
|
||||
{
|
||||
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO0);
|
||||
gpio_clear(GPIOB, GPIO0);
|
||||
delay(205000);
|
||||
gpio_set_mode(DHT_PORT, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, DHT_PIN);
|
||||
gpio_clear(DHT_PORT, DHT_PIN);
|
||||
delay(100000);
|
||||
//delay(30000);
|
||||
gpio_set(GPIOB, GPIO0);
|
||||
gpio_set(DHT_PORT, DHT_PIN);
|
||||
delay(100);
|
||||
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO0);
|
||||
gpio_set_mode(DHT_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, DHT_PIN);
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
int i = 0;
|
||||
SEGGER_RTT_printf(0, "Start\n");
|
||||
puts("Start");
|
||||
rcc_clock_setup_pll(&rcc_hse_configs[RCC_CLOCK_HSE8_72MHZ]);
|
||||
gpio_setup();
|
||||
//tim_setup();
|
||||
tim_setup();
|
||||
|
||||
/* Blink the LED (PA5) on the board. */
|
||||
while (1) {
|
||||
/* Using API function gpio_toggle(): */
|
||||
gpio_toggle(GPIOB, GPIO1); /* LED on/off */
|
||||
delay(4000000);
|
||||
//dht_start_signal();
|
||||
delay(10000000);
|
||||
dht_start();
|
||||
|
||||
i++;
|
||||
SEGGER_RTT_printf(0, "hello: %d\n", i);
|
||||
SEGGER_RTT_printf(0, "Poll: %d\n", i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -22,6 +22,7 @@ source [find target/stm32f1x.cfg]
|
||||
|
||||
reset_config srst_only
|
||||
|
||||
# Search for RTT string from start of RAM
|
||||
rtt setup 0x20000000 8192 "SEGGER RTT"
|
||||
rtt server start 9090 0
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user