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calmsacibis995
2022-09-29 17:59:04 +03:00
parent 72fa9da3d7
commit 8fc8fa8089
33399 changed files with 11964078 additions and 0 deletions
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stand/arcs/include/sys/adp78.h
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/*
* Header file for Adaptec 7800 family of SCSI controllers
*
* $Id: adp78.h,v 1.3 1997/07/24 00:39:26 philw Exp $
*/
/****************************************************************
%%% Scatter Gather Element Definition %%%
*****************************************************************/
/*
* The scatter gather element list must be in contiguous memory.
* There is no limit on how many elements there are.
* The data_len field of the last element must have SG_LAST_ELEMENT.
*/
#define NUMSG_SMALL 16 /* typical number of s/g needed */
#define NUMSG_BIG 512
#define SG_LAST_ELEMENT 0x80000000
typedef struct sg_element {
void *data_ptr; /* 32 bit data pointer */
unsigned int data_len; /* 32 bit data length */
} SG_ELEMENT;
/****************************************************************
*
* Adaptec 7880 Host adapter interface record.
* Holds lists of active scsi requests/scb's, waiting scsi requests, and
* free scb's as well as state information.
*
****************************************************************/
typedef struct adp78_adap {
u_char ad_ctlrid; /* adapter/controller number */
u_char ad_scsiid; /* scsi id of this controller */
u_char ad_rev; /* rev of this controller */
u_char ad_pcibusnum; /* 0 for main bus */
u_char ad_pcidevnum; /* PCI device number */
u_int ad_flags;
SG_ELEMENT *ad_sg; /* s/g list, only 1 per adapter */
char *ad_ebuf; /* for swizzled cdb */
struct cfp *ad_himcfg; /* HIM configuration structure */
char *ad_baseaddr; /* Memory mapped address */
volatile char *ad_cfgaddr; /* config. address/token */
int ad_timeoutval; /* timeout value for current command */
scsisubchan_t *ad_currcmd; /* ptr to current cmd */
scsisubchan_t *ad_subchan[SC_MAXTARG][SC_MAXLUN];
sp_struct *ad_scb[SC_MAXTARG][SC_MAXLUN];
char *ad_inq[SC_MAXTARG][SC_MAXLUN];
u_char ad_syncflags[SC_MAXTARG];
} adp78_adap_t;
#define ADP78_NUMADAPTERS SC_MAXADAP /* only adaptecs recognized in standalone */
/*
* Flags for ad_flags
*/
#define ADF_OPTIONAL_PCI 1 /* controller is on external PCI card */
/*
* Flags for ad_syncflags
*/
#define AD_CANTSYNC 1
#define AD_SYNC_ON 2
/*
* Bit fields for dealing with adp_scsi_opt.
* Bits 7-4 and bit 0 from adp_device_options go directly into Cf_ScsiOptions
* in the config structure of for the HIM. I use bits 1 and 2 to make
* configuration in master.d/adp78 a bit easier.
*/
#define HIM_OPTIONS 0xf1
#define ADP_ALLOW_DISCONNECT 0x02
/*
* Defines for standalone.
* Number of us to wait between polls of the intstat register
*/
#define POLL_WAIT 1000
#define US_IN_SEC 1000000
#define ADP_MIN_TIMEOUT 1
stand/arcs/include/sys/apf_diag.h
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/**************************************************************************
* *
* Copyright (C) 1993 Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/*
* apf_diag.h - Adobe Pixel Formatter defines for diags
*/
#define GIO_SLOT_0_ADDRESS 0x1f400000
#define GIO_SLOT_1_ADDRESS 0x1f600000
#define PF_INTERRUPT_REG_OFFSET 0x1fe00 /* write to set */
#define PF_CAUSE_REG_OFFSET 0x1fe04 /* write to clear */
#define PF_INTERRUPT_MASK 0x80008000
#define PRODUCT_ID_MASK 0xff /* mask rest of GIO id */
#define PF_PRODUCT_ID 0x06
/*
revisions:
0 - all pre-released versions of the PF board and ROMs (old sload, 32k RAM)
1 - PF3 with new ROM (new sload, 32k RAM)
2 - PF4 with new ROM (new sload, 32k RAM + 32k unshared RAM)
*/
#define GET_PRODUCT_REVISION(x) ( ((x) >> 8) & 0xff)
stand/arcs/include/sys/buf.h
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/**************************************************************************
* *
* Copyright (C) 1989, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/* Copyright (c) 1984 AT&T */
/* All Rights Reserved */
/* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF AT&T */
/* The copyright notice above does not evidence any */
/* actual or intended publication of such source code. */
#ifndef __SYS_BUF_H__
#define __SYS_BUF_H__
#ident "$Revision: 3.29 $"
#include "sys/sema.h"
struct bdevsw;
/*
* Structure used to get to the device driver, which can either be
* via a spec vnode, or the bdevsw entry. We cache the bdevsw entry
* in order to avoid using the hardware graph to find it in the
* get_bdevsw macro. The spec vp is used in the cellular case where
* we have to use VOP_STRATEGY in place of bdstrat.
*/
typedef struct buftarg {
struct vnode *specvp;
struct bdevsw *bdevsw;
dev_t dev;
} buftarg_t;
/*
* Each buffer in the pool is usually doubly linked into 2 lists:
* the device with which it is currently associated (always)
* and also on a list of blocks available for allocation
* for other use (usually).
* The latter list is kept in last-used order, and the two
* lists are doubly linked to make it easy to remove
* a buffer from one list when it was found by
* looking through the other.
* A buffer is on the available list, and is liable
* to be reassigned to another disk block, if and only
* if it is not marked BUSY. When a buffer is busy, the
* available-list pointers can be used for other purposes.
* Most drivers use the forward ptr as a link in their I/O active queue.
* A buffer header contains all the information required to perform I/O.
* Most of the routines which manipulate these things are in fs_bio.c.
*/
typedef struct buf
{
sema_t b_lock; /* lock for buffer usage */
int b_flags; /* see defines below */
struct buf *b_forw; /* headed by d_tab of conf.c */
struct buf *b_back; /* " */
struct buf *av_forw; /* position on free list, */
struct buf *av_back; /* if not BUSY*/
dev_t b_dev; /* major+minor device name */
char b_error; /* returned after I/O */
ushort b_length; /* length of buffer memory in BBs*/
unsigned b_bcount; /* transfer count */
union {
caddr_t b_addr; /* low order core address */
int *b_words; /* words for clearing */
struct pfdat *b_pfdat; /* pointer into b_pages list */
daddr_t *b_daddr; /* disk blocks */
} b_un;
daddr_t b_blkno; /* block # on device */
unsigned b_resid; /* words not transferred after error */
time_t b_start; /* request start time */
struct proc *b_proc; /* process doing physical or swap I/O */
struct pfdat *b_pages; /* page list for PAGEIO */
unsigned b_remain; /* virt b_bcount for PAGEIO use only */
unsigned b_sort; /* key with which to sort on queue */
void (*b_relse)(); /* 'special action' release function */
sema_t b_iodone; /* lock indicating I/O done */
void (*b_iodonefunc)(); /* 'special action' iodone function */
} buf_t;
typedef int opaque_t;
#define paddr(X) (paddr_t)(X->b_un.b_addr)
#define b_dmaaddr b_un.b_addr
#define b_page b_un.b_pfdat
extern struct buf* buf; /* The buffer pool itself */
extern struct buf bfreelist; /* head of available list */
extern int bfslpcnt; /* # procs waiting for free buffers */
extern sema_t bfreeslp; /* sleep semaphore for free list */
extern lock_t bfreelock; /* lock on buffer free list */
struct pfree {
int b_flags;
struct buf *av_forw;
struct buf *av_back;
};
/*
* These flags are kept in b_flags.
*/
#define B_WRITE 0x000000 /* non-read pseudo-flag */
#define B_READ 0x000001 /* read when I/O occurs */
#define B_DONE 0x000002 /* transaction finished */
#define B_ERROR 0x000004 /* transaction aborted */
#define B_BUSY 0x000008 /* not on av_forw/back list */
#define B_PHYS 0x000010 /* Physical IO */
#define B_MAP 0x000020 /* mappable data */
#define B_WANTED 0x000040 /* issue wakeup when BUSY goes off */
#define B_AGE 0x000080 /* delayed write for correct aging */
#define B_ASYNC 0x000100 /* don't wait for I/O completion */
#define B_DELWRI 0x000200 /* delayed write - wait until buffer needed */
#define B_OPEN 0x000400 /* open routine called */
#define B_STALE 0x000800
#define B_VERIFY 0x001000
#define B_FORMAT 0x002000
#define B_PAGEIO 0x004000 /* use b_pages for I/O */
#define B_MAPPED 0x008000 /* buffer has been mapped to kernel va */
#define B_SWAP 0x010000 /* block is on swap, paddr is physical addr */
#define B_BDFLUSH 0x020000 /* block being written by bdflush() */
#define B_FRAG 0x040000 /* fragmented buffer */
#define B_BMAP 0x080000 /* FS_BMAP flag -- just want block mappings */
#define B_PDELWRI 0x100000 /* pseudo-flag for prelse */
#define B_UNCACHED 0x200000 /* uncached mapping requested for memcopy */
#define B_LAST 0x400000 /* must put this buffer at the end of driver's
queue */
#define B_BFLUSH 0x800000 /* delayed write buffer is being pushed out */
#define BP_ISMAPPED(bp) ((bp->b_flags & (B_PAGEIO|B_MAPPED)) != B_PAGEIO)
/*
* Fast access to buffers in cache by hashing.
*/
#define bhash(d,b) ((struct buf *)&hbuf[((int)(d)+(int)(b))&v.v_hmask])
struct hbuf
{
sema_t b_lock; /* lock for hash queue */
int b_flags;
struct buf *b_forw;
struct buf *b_back;
};
extern struct hbuf *hbuf;
/*
* Pick up the device's error number and pass it to the user;
* if there is an error but the number is 0 set a generalized code
*/
#define geterror(bp) \
{\
\
if (bp->b_flags&B_ERROR)\
if ((u.u_error = bp->b_error)==0)\
u.u_error = EIO;\
}
#ifdef _KERNEL
#define BIO_MAXBSIZE_LOG2 (BPCSHIFT+8)
/* Limit for maximum offsets, in chars and BBs that can be reached via lseek */
#define BIO_MAXBSIZE (1<<BIO_MAXBSIZE_LOG2)
#define BIO_MAXBBS (1<<(BIO_MAXBSIZE_LOG2-BBSHIFT))
/*
* Hashing parameters. Each disk block is scaled into a larger block,
* whose length is twice the maximun length of a buffer block.
* Maximum overlap of buckets is thus reduced to 2.
*/
#define BIO_BBSPERBUCKETSHIFT (5)
#define BIO_BBSPERBUCKETMINUSONE ((1 << BIO_BBSPERBUCKETSHIFT) - 1)
#define BIO_BBSPERLBMINUSONE (BTOBBT(BIO_MAXBSIZE) - 1)
struct buf *getblk(dev_t, daddr_t, int);
struct buf *geteblk(int);
struct buf *bread(dev_t, daddr_t, int);
struct buf *breada(dev_t, daddr_t, int, daddr_t, int);
char *bp_mapin(buf_t *);
void bp_mapout(buf_t *);
struct buf *getphysbuf(void);
void putphysbuf(buf_t *);
void putphysbuf(buf_t *);
struct buf *incore(dev_t, daddr_t, int, int);
void prelse(buf_t *);
paddr_t bptophys(buf_t *);
#endif /* _KERNEL */
#endif /* __SYS_BUF_H__ */
stand/arcs/include/sys/device_id.h
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#ifndef __SYS_DEVICE_ID_H__
#define __SYS_DEVICE_ID_H__
#ident $Revision: 1.2 $
/* Device Id's for use with interrupt functions. */
#define DEV_SW_UNUSED0 0
#define DEV_SW_UNUSED1 1
#define DEV_FPU 2
#define DEV_LOCAL0 3
#define DEV_LOCAL1 4
#define DEV_TIMER0 5
#define DEV_TIMER1 6
#define DEV_PARITY 7
#define DEV_GIO_0 8
#define DEV_IDE_DMA 9
#define DEV_SCSI 10
#define DEV_ETHERNET 11
#define DEV_GRAPHICS 12
#define DEV_DUART 13
#define DEV_GIO_1 14
#define DEV_VME_0 15
#define DEV_UNUSED16 16
#define DEV_GR1STAT 17
#define DEV_UNUSED18 18
#define DEV_VME_1 19
#define DEV_DSP 20
#define DEV_ACFAIL 21
#define DEV_VIDOPT 22
#define DEV_VRETRACE 23
#define DEV_PC_KBD 24
#define DEV_PC_IDE 25
#define DEV_PC_UNUSED26 26
#define DEV_PC_MOUSE 27
#define DEV_PC_FLOPPY 28
#define DEV_PC_UNUSED29 29
#define DEV_PC_UART1 30
#define DEV_PC_UART2 31
#define DEV_PC_PPORT 32
#define DEV_PC_UNUSED33 33
#define DEV_PC_AUDIO 34
/* Eisa interrupts on EISA bus 0. */
#define DEV_EISA0_IRQ0 40
#define DEV_EISA0_IRQ1 41
#define DEV_EISA0_IRQ2 42
#define DEV_EISA0_IRQ3 43
#define DEV_EISA0_IRQ4 44
#define DEV_EISA0_IRQ5 45
#define DEV_EISA0_IRQ6 46
#define DEV_EISA0_IRQ7 47
#define DEV_EISA0_IRQ8 48
#define DEV_EISA0_IRQ9 49
#define DEV_EISA0_IRQ10 50
#define DEV_EISA0_IRQ11 51
#define DEV_EISA0_IRQ12 52
#define DEV_EISA0_IRQ13 53
#define DEV_EISA0_IRQ14 54
#define DEV_EISA0_IRQ15 55
#define DEV_MAX 35 /* Number of Devices */
#define DEV_NONE -1 /* All 1's => no such device */
#endif
stand/arcs/include/sys/dksc.h
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/**************************************************************************
* *
* Copyright (C) 1986, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
#ident "$Revision: 3.42 $"
#ifndef OTYPCNT
# include <sys/open.h> /* for OTYP stuff */
#endif
/* SCSI disk minor # breakdown.
* 7 6 5 4 3 2 1 0
* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
* + + + +
* + Target ID + LUN # + Partition +
* + + + +
* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
*/
#define dev_to_softc(adap, targ, lu) (dksoftc[adap][targ][lu])
#define scsi_lu(dev) 0
/* these allow the dksc driver to work with different logical block size
devices. So all raw accesses will be OK; if/when block code is fixed,
block devices will just start working.
*/
#define dkCHKBB(bytes) ((bytes)%dk->dk_blksz)
#define dkBTOBB(bytes) ((bytes)/dk->dk_blksz) /* truncates! used where caller
should be checking for short count on return anyway. */
#define dkBBTOB(blks) ((blks)*dk->dk_blksz)
/* Only 1 LU supported per physical disk drive (LUN == 0) */
#define DK_MAXLU 1
/* partitions per drive */
#define DK_MAX_PART 16
/* values for dk_flags */
#define DK_WRTPROT 1 /* drive is write protected */
#define DK_SILENT_NOTREADY 2 /* set when doing test unit ready */
/* by powers of 2, allows tracking sizes up to 128 blocks */
#define NUM_BLK_STATS 8
struct blkstats {
uint bk_reads[NUM_BLK_STATS];
uint bk_writes[NUM_BLK_STATS];
};
/*
* Software state per disk drive.
*/
struct dksoftc {
struct volume_header dk_vh; /* Volume header info */
struct buf dk_buf; /* Local buffer */
sema_t dk_wait; /* Synchronous use waiters */
struct iobuf dk_tab; /* Strat routine queue header */
struct blkstats dk_blkstats; /* i/o stats */
scsisubchan_t *dk_subchan; /* SCSI Subchannel structure */
unsigned *dk_drivecap; /* drive size as returned by
readcapacity (2nd word is block
size at end of media) */
#define DK_DRIVECAP_SIZE 8
unsigned dk_blksz; /* logical (from drive) blocksize of device */
u_char *dk_sense_data; /* private buffer for sense data */
#define DK_SENSE_DATA_SIZE 24
ushort dk_openparts[OTYPCNT]; /* map of open partitions (counts
on DK_MAX_PART being 16 or less), one entry for
CHR, LYR, BLK, SWP, and MNT */
ushort dk_lyrcnt[DK_MAX_PART]; /* lyr open/closes are matched
pairs, so need a counter for it (ugh) */
ushort dk_flags;
lock_t dk_lock; /* Lock to protect structure fields */
u_char dk_cmd[SC_CLASS1_SZ]; /* the command packet */
u_char dk_selflags; /* flags for DIOCSELECT; see DIOCSELFLAGS */
u_char dk_retry; /* Retry count for cmds */
u_char *dk_inqtyp; /* devtype from first byte of inquiry data */
};
/*
* We only really need the first byte of inquiry data, but when we do SCSI
* inquiries on little-endian devices, the significant byte comes in as
* byte 3. This needs to be big enough to hold the significant data.
*/
#define DK_INQTYP_SIZE 4
#define dk_part(minor) (minor & (DK_MAX_PART - 1))
/*
* This structure is used by the mode select/get ioctls to determine
* where the data is to be sent to/recieved from.
*/
struct dk_ioctl_data {
caddr_t i_addr;
u_int i_len;
u_char i_page; /* Page code is used only on mode select */
};
/* Maximum amount of data allowed by an ioctl cmd */
#define MAX_IOCTL_DATA 4096
/* These are the possible page codes used by mode sense/get */
#define ERR_RECOV 0x1
#define CONN_PARMS 0x2
#define DEV_FORMAT 0x3
#define DEV_GEOMETRY 0x4
#define DEV_FDGEOMETRY 0x5 /* geometry for SMS flexible disks */
#define BLOCK_DESCRIP 0x7 /* TOSHIBA MK156FB only */
#define VERIFY_ERR 0x7 /* SCSI 2 Verify error recovery page */
#define CACHE_SCSI2 0x8 /* SCSI 2 cache control; Maxtor 8760, Hitachi 515C */
#define NOTCH_SCSI2 0xC /* SCSI 2 notch page */
#define CACHE_CONTR 0x38 /* CDC Wren IV/V/VI drives */
#define ALL 0x3f
/* These are the page control field values recognized by the mode sense cmd */
#define CURRENT 0
#define CHANGEABLE (0x1 << 6)
#define DEFAULT (0x2 << 6)
#define SAVED (0x3 << 6)
/*
* These are the pages of the drive parameter set/get commands.
* Note that all of the struct should be allocated to the full
* size of the union, since we determine their sizes at run time,
* due to the possiblity of different page sizes on different
* mfg drives. This is normally done by using ptrs to the structs,
* and setting them to point to the dk_pages member of a struct mode_sense_data.
* Any 'extra' bytes won't be changed by programs like fx, but most
* drives require that the pages being set by a mode select be
* the correct size and have valid data for bytes that aren't
* changed (usually retrieved via a mode sense into the same buffer).
*/
union dk_pages {
struct common {
u_char pg_code;
u_char pg_len;
u_char pg_maxlen[0x100-2]; /* make room for max possible page len */
} common;
struct err_recov {
u_char e_pgcode;
u_char e_pglen;
u_char e_err_bits;
u_char e_retry_count;
u_char e_rdretry;
u_char e_corrspan;
u_char e_headoffset;
u_char e_strobeoffset;
u_char e_rsv0;
u_char e_wrretry;
u_char e_rsv1;
u_char e_recovtime[2];
} err_recov;
struct connparms {
u_char c_pgcode;
u_char c_pglen;
u_char c_bfull;
u_char c_bempty;
u_char c_binacthi;
u_char c_binactlo;
u_char c_disconhi;
u_char c_disconlo;
u_char c_reserv[2];
} cparms;
struct dev_format {
u_char f_pgcode;
u_char f_pglen;
u_char f_trk_zone[2];
u_char f_altsec[2];
u_char f_alttrk_zone[2];
u_char f_alttrk_vol[2];
u_char f_sec_trac[2];
u_char f_bytes_sec[2];
u_char f_interleave[2];
u_char f_trkskew[2];
u_char f_cylskew[2];
u_char f_form_bits;
u_char f_reserved4[3];
} dev_format;
struct dev_geometry { /* page 4 for winchesters */
u_char g_pgcode;
u_char g_pglen;
u_char g_ncyl[3];
u_char g_nhead;
u_char g_wrprecomp[3];
u_char g_reducewrcur[3];
u_char g_steprate[2];
u_char g_landing[3];
u_char g_reserved1:7;
u_char g_spindlesync:1;
u_char g_rotatoff;
u_char g_reserved2;
u_char g_rotatrate[2];
u_char g_reserved3[2];
} dev_geometry;
struct dev_fdgeometry { /* page 5 for floppies */
u_char g_pgcode;
u_char g_pglen;
u_char g_trate[2];
u_char g_nhead;
u_char g_spt;
u_char g_bytes_sec[2];
u_char g_ncyl[2];
u_char g_wprcomp[2];
u_char g_wrcurr[2];
u_char g_steprate[2];
u_char g_steppulsewidth;
u_char g_headset[2];
u_char g_moton;
u_char g_motoff;
u_char g_trdy:1;
u_char g_ssn:1;
u_char g_mo:1;
u_char g_reserv0:5;
u_char g_reserv1:4;
u_char g_stpcyl:4;
u_char g_wrprecomp;
u_char g_headld;
u_char g_headunld;
u_char g_pin34:4;
u_char g_pin2:4;
u_char g_pin4:4;
u_char g_pin1:4; /* pin 1 TEAC, reserved on NCR */
u_char g_reserv2[4];
} dev_fdgeometry;
struct block_descrip { /* Toshiba 156 FB only */
u_char b_pgcode;
u_char b_pglen;
u_char b_reserved0;
u_char b_bdlen;
u_char b_density;
u_char b_reserved1[3];
u_int b_blen; /* This is actually a 3 byte val; high
byte reserved */
} block_descrip;
struct verify_err { /* scsi 2 error recovery params */
u_char v_pgcode;
u_char v_pglen;
u_char rsv0:4,
eer:1,
per:1,
dte:1,
dcr:1;
u_char v_retry;
u_char v_corrspan;
u_char v_rsv1[5];
u_char v_recovtime[2];
} verify_err;
struct cachectrl { /* CDC Wren IV/V/VI cache control */
u_char c_pgcode;
u_char c_pglen;
u_char c_ccen:1, c_wie:1, c_ssm:1, c_ce:1, c_ctsize:4;
u_char c_prefetch;
u_char c_maxpre;
u_char c_maxpremult;
u_char c_minpre;
u_char c_minpremult;
u_char c_reserv[8];
} cachctrl;
struct notch { /* info for 'zone bit recorded' devices */
u_char n_pgcode;
u_char n_pglen;
u_char n_nd:1;
u_char n_lpn:1;
u_char n_rsv0:6;
u_char n_rsv1;
u_char n_maxnotch[2];
u_char n_actnotch[2];
u_char n_startbound[2];
u_char n_endbound[2];
u_char n_pagesnotched[2];
} notch;
struct cachescsi2 { /* scsi 2 cache ctrl page */
u_char c_pgcode;
u_char c_pglen;
u_char c_rsrv:5;
u_char c_wce:1;
u_char c_mf:1;
u_char c_rcd:1;
u_char c_rdpri:4;
u_char c_wrpri:4;
u_char c_predislen[2];
u_char c_minpre[2];
u_char c_maxpre[2];
u_char c_maxpreceil[2];
u_char c_fsw:1; /* force seq write; not yet in rev 10H */
u_char c_rsrv2:1; /* not yet in rev 10H */
u_char c_dra:1; /* disable readahead; not yet in rev 10H */
u_char c_rsrv3:5; /* not yet in rev 10H */
u_char c_numseg;
u_char c_cachsize[2]; /* cache seg size; not yet in rev 10H */
u_char c_rsv5; /* not yet in rev 10H */
u_char c_ncachsize[3]; /* non-cache seg size; not yet in rev 10H */
} cachescsi2;
};
/* Error recovery flag byte bits for e_err_bits */
#define E_DCR 0x1
#define E_DTE 0x2
#define E_PER 0x4
#define E_RC 0x10
#define E_TB 0x20
#define E_ARRE 0x40
#define E_AWRE 0x80
/* The data structure of the mode sense command */
struct mode_sense_data {
u_char sense_len;
u_char mediatype;
u_char wprot:1, reserv0:2, dpofua:1, reserv1:4;
u_char bd_len;
u_char block_descrip[8]; /* note that this field will NOT be supplied
by some drives, so that dk_pages data may actually start at this
offset; check the bd_len value! */
union dk_pages dk_pages;
};
/* The structure of the mode select command */
struct mode_select_data {
u_char reserv0;
u_char mediatype;
u_char wprot:1, reserv1:7;
u_char blk_len; /* This will normally be set to 0 */
union dk_pages dk_pages;
};
struct defect_header {
u_char reserved0;
u_char format_bits;
u_char defect_listlen[2];
};
struct defect_entry {
u_char def_cyl[3];
u_char def_head;
u_char def_sector[4]; /* bytes from index, or sector */
};
stand/arcs/include/sys/dump.h
+19
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@@ -0,0 +1,19 @@
/*
* Constants for kernel crash dumping stuff
*
* $Revision: 3.5 $
*/
#ifdef _KERNEL
#define DUMP_OPEN 1 /* initialize device */
#define DUMP_WRITE 2 /* write some data */
#define DUMP_CLOSE 3 /* close the device */
#endif
/*
* Values for led's during a crash
*/
#define LED_PATTERN_BADVA 2 /* kernel bad virtual address */
#define LED_PATTERN_FAULT 3 /* random kernel fault */
#define LED_PATTERN_BOTCH 4 /* nofault botch */
#define LED_PATTERN_PKG 5 /* bad package linkage */
stand/arcs/include/sys/errno.h
+2
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@@ -0,0 +1,2 @@
/* compatibility hook */
#include <arcs/errno.h>
stand/arcs/include/sys/fat.h
+73
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@@ -0,0 +1,73 @@
#ifndef __SYS_FAT_H__
#define __SYS_FAT_H__
#ident "$Revision: 1.2 $"
/* BIOS parameter block */
typedef struct bpb {
USHORT BytesPerSector;
UCHAR SectorsPerCluster;
USHORT ReservedSectors;
UCHAR FatCount;
USHORT RootDirEntries;
USHORT TotalSectors;
UCHAR MediaDesc;
USHORT SectorsPerFat;
USHORT SectorsPerTrack;
USHORT HeadCount;
USHORT HiddenSectors;
} BPB;
/* offsets within boot sector */
#define BYTES_PER_SECTOR 0x0b
#define SECTOR_PER_CLUSTER 0x0d
#define RESERVED_SECTOR 0x0e
#define FAT_COUNT 0x10
#define ROOTDIR_ENTRIES 0x11
#define TOTAL_SECTORS 0x13
#define MEDIA_DESC 0x15
#define SECTORS_PER_FAT 0x16
#define SECTORS_PER_TRACK 0x18
#define HEAD_COUNT 0x1a
#define HIDDEN_SECTORS 0x1c
/* size of directory entries */
#define DIRENTRYSZ 32
/* support FAT types */
#define DOS12 0x01
#define DOS16 0x04
#define DOS331 0x06
/* file attributes */
#define READONLY 0x00
#define HIDDEN 0x02
#define SYSTEM 0x04
#define VOLUMELABEL 0x08
#define DIRECTORY 0x10
#define ARCHIVE 0x20
/* directory entry offsets */
#define FILENAME 0x00
#define EXTENSION 0x08
#define ATTRIBUTE 0x0b
#define TIMESTAMP 0x16
#define DATESTAMP 0x18
#define STARTCLUSTER 0x1a
#define FILESIZE 0x1c
/* this structures stores the information for open requests */
typedef struct openinfo {
LONG Fid;
USHORT BytesPerSector;
USHORT SectorsPerCluster;
USHORT BytesPerCluster;
USHORT DataOffset;
CHAR FatType;
USHORT FatStart;
USHORT StartingCluster;
ULONG FileLength;
UCHAR Attribute;
} OPENINFO;
#endif
stand/arcs/include/sys/file.h
+62
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@@ -0,0 +1,62 @@
#ident "include/sys/file.h: $Revision: 1.4 $"
/*
* file.h - defines for file syscalls
*/
/*
* flags- also for fcntl call.
*/
#define FOPEN (-1)
#define FREAD 00001 /* descriptor read/receive'able */
#define FWRITE 00002 /* descriptor write/send'able */
#define FNDELAY 00004 /* no delay */
#define FAPPEND 00010 /* append on each write */
#define FMARK 00020 /* mark during gc() */
#define FDEFER 00040 /* defer for next gc pass */
#define FASYNC 00100 /* signal pgrp when data ready */
#define FSHLOCK 00200 /* shared lock present */
#define FEXLOCK 00400 /* exclusive lock present */
/* bits to save after open */
#define FMASK 00113
#define FCNTLCANT (FREAD|FWRITE|FMARK|FDEFER|FSHLOCK|FEXLOCK)
/* open only modes */
#define FCREAT 01000 /* create if nonexistant */
#define FTRUNC 02000 /* truncate to zero length */
#define FEXCL 04000 /* error if already created */
/*
* User definitions.
*/
/*
* Open call (standalone doesn't support all POSIX modes).
*/
#define O_RDONLY OpenReadOnly /* open for reading */
#define O_WRONLY OpenWriteOnly /* open for writing */
#define O_RDWR OpenReadWrite /* open for read & write */
/*
* Flock call.
*/
#define LOCK_SH 1 /* shared lock */
#define LOCK_EX 2 /* exclusive lock */
#define LOCK_NB 4 /* don't block when locking */
#define LOCK_UN 8 /* unlock */
/*
* Access call.
*/
#define F_OK 0 /* does file exist */
#define X_OK 1 /* is it executable by caller */
#define W_OK 2 /* writable by caller */
#define R_OK 4 /* readable by caller */
/*
* Lseek call.
*/
#define L_SET 0 /* absolute offset */
#define L_INCR 1 /* relative to current offset */
#define L_XTND 2 /* relative to end of file */
stand/arcs/include/sys/fpu.h
+77
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@@ -0,0 +1,77 @@
#ident "include/sys/fpu.h: $Revision: 1.5 $"
/*
* fpu.h -- floating point coprocessor specific defines
*/
#define FPREV_REVISION_MASK 0xff
#define FPREV_IMPLEMENTATION_MASK 0xff00
/* FPU co-processor definitions
*/
#if defined(_LANGUAGE_ASSEMBLY)
# define __C1REG__(x) $x
#else
# define __C1REG__(x) x
#endif
#define C1_F0 __C1REG__(0)
#define C1_F1 __C1REG__(1)
#define C1_STATUS __C1REG__(31)
#define RN 0
#define RZ 1
#define RP 2
#define RM 3
#define FP_COND 0x00800000
/* Exception bits */
#define FP_EXC 0x0003f000
#define FP_EXC_E 0x00020000
#define FP_EXC_V 0x00010000
#define FP_EXC_Z 0x00008000
#define FP_EXC_O 0x00004000
#define FP_EXC_U 0x00002000
#define FP_EXC_I 0x00001000
/* Enables */
#define FP_ENABLE 0x00000f80
#define FP_EN_V 0x00000800
#define FP_EN_Z 0x00000400
#define FP_EN_O 0x00000200
#define FP_EN_U 0x00000100
#define FP_EN_I 0x00000080
/* Sticky bits */
#define FP_STKY 0x0000007c
#define FP_STKY_V 0x00000040
#define FP_STKY_Z 0x00000020
#define FP_STKY_O 0x00000010
#define FP_STKY_U 0x00000008
#define FP_STKY_I 0x00000004
/* Rounding Modes */
#define FP_RMODE 0x00000003
#define FP_RN 0x00000000
#define FP_RZ 0x00000001
#define FP_RP 0x00000002
#define FP_RM 0x00000003
#define FP_RN_MASK 0x00000003
#define FP_RZ_MASK 0x00000002
#define FP_RP_MASK 0x00000001
#define FP_RM_MASK 0x00000000
#if defined(_LANGUAGE_ASSEMBLY)
#define fpc_irr $0
#define fpc_led $0
#define fpc_eir $30
#define fpc_csr $31
#endif
#define IMPLEMENTATION_NONE 0 /* software */
#define IMPLEMENTATION_R2360 0x100 /* board */
#define IMPLEMENTATION_R2010 0x200 /* chip */
stand/arcs/include/sys/gda_ip32.h
+76
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@@ -0,0 +1,76 @@
/**************************************************************************
* *
* Copyright (C) 1998, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/*
* gda.h -- Contains the data structure for the global data area,
* The GDA contains information communicated between the
* PROM, SYMMON, and the kernel.
*/
#ident "$Revision: 1.1 $"
#ifndef __SYS_GDA_IP32_H__
#define __SYS_GDA_IP32_H__
#define GDA_ADDR (K0_RAMBASE+0x400)
/**************************************/
#define GDA_MAGIC 0x58464552
#define G_MAGICOFF 0x00 /* g_magic */
#define G_PROMOPOFF 0x04 /* g_promop */
#define G_NMISRSAVE 0x04 /* g_nmi_sr_save */
#define G_NMIVECOFF 0x08 /* g_nmivec */
#define G_NMIEPCSAVE 0x0c /* g_nmi_epc_save */
#define G_MASTEROFF 0x10 /* g_masterspnum */
#define G_HKDNORMOFF 0x18 /* g_hooked_norm */
#define G_HKDUTLBOFF 0x20 /* g_hooked_utlb */
#define G_HKDXUTLBOFF 0x28 /* g_hooked_xtlb */
#define G_VDSOFF 0x30 /* g_vds */
#ifdef _LANGUAGE_C
typedef struct gda {
uint g_magic; /* GDA magic number */
uint g_promop; /* Passes requests from the kernel to prom */
uint g_nmivec; /* The address to jump to on an NMI */
uint g_nmi_epc_save; /* The saved epc at NMI */
uint g_masterspnum; /* The SPNUM (not vpid) of the master cpu */
uint g_fill0; /* 0x14 */
inst_t **g_hooked_norm;/* ptr to pda loc for norm hndlr */
uint _fill1; /* 0x1c */
inst_t **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */
uint _fill2; /* 0x24 */
inst_t **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */
uint _fill3; /* 0x2c */
ulong g_vds; /* Store the virtual dipswitches here */
} gda_t;
#define g_nmi_sr_save g_promop
#define GDA ((gda_t *)GDA_ADDR)
#endif /* __LANGUAGE_C */
/*
* The following requests can be sent to the PROM during startup.
*/
#define PROMOP_HALT 1
#define PROMOP_POWERDOWN 2
#define PROMOP_RESTART 3
#define PROMOP_REBOOT 4
#define PROMOP_IMODE 5
#endif /* __SYS_GDA_IP32_H__ */
stand/arcs/include/sys/ht_gl.h
+59
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@@ -0,0 +1,59 @@
/**************************************************************************
* *
* Copyright (C) 1988, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/**************************************************************************/
/*
** Standalone version of gl.h
*/
/**************************************************************************/
#define XMAXSCREEN 1279
#define YMAXSCREEN 1023
#define XMAXMEDIUM 1023
#define YMAXMEDIUM 767
#define BLACK 0
#define RED 1
#define GREEN 2
#define YELLOW 3
#define BLUE 4
#define MAGENTA 5
#define CYAN 6
#define WHITE 7
typedef unsigned short Colorindex;
/*
** global data for character sets
**
*/
#define Byte unsigned char
typedef struct {
unsigned short offset;
Byte w, h;
signed char xoff, yoff;
short width;
} Fontchar;
typedef struct Bitmap {
unsigned short *base;
short xsize, ysize;
short xorig, yorig;
short xmove, ymove;
short sper;
} Bitmap;
extern Fontchar hc_font[];
extern unsigned short hc_raster[];
stand/arcs/include/sys/hwgraph.h
+196
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/**************************************************************************
* *
* Copyright (C) 1992-1995 Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
#ifndef _HWGRAPH_H
#define _HWGRAPH_H
#ident "$Revision: 1.3 $"
#if _KERNEL
#include <sys/conf.h>
#include <sys/graph.h>
#include <sys/sysmacros.h>
/* Defines for dealing with fast indexed information associated with a vertex */
/* Reserve room in every vertex for 4 pieces of fast access indexed information */
#define HWGRAPH_NUM_INDEX_INFO 4
#define HWGRAPH_BDEVSW 0 /* bdevsw for this device */
#define HWGRAPH_CDEVSW 1 /* cdevsw for this device */
#define HWGRAPH_CONNECTPT 2 /* connect point (parent) */
#define HWGRAPH_FASTINFO 3 /* reserved for creator of vertex */
typedef int (*traverse_fn_t)(vertex_hdl_t, char **, vertex_hdl_t *);
/*
* Interfaces to convert between graph vertex handles and dev_t's.
* Major number 0 is reserved for use by hwgraph; this allows the
* conversion between vhdl's and dev's to be a NULL conversion.
* That simplifies things for driver writers -- they can pass dev_t's
* directly to hwgraph interfaces.
*/
#if TBD
#include <sys/major.h>
#assert(HWGRAPH_MAJOR == 0)
#endif
#define vhdl_to_dev(vhdl) ((dev_t)(vhdl))
#define dev_to_vhdl(dev) ((vertex_hdl_t)(dev))
#define dev_is_vertex(dev) (emajor((dev_t)(dev)) == 0)
#define HWGRAPH_STRING_DEV makedev(0, 0)
#define IS_HWGRAPH_STRING_DEV(x) ((dev_t)(x)==HWGRAPH_STRING_DEV)
/*
* Reserved edge_place_t values, used as the "place" parameter to edge_get_next.
* Every vertex in the hwgraph has up to 4 *implicit* edges. There is an implicit
* edge called "." that points to the current vertex. There is an implicit edge
* called ".." that points to the vertex' connect point. There are implicit edges
* called "block" and "char" that point to special files that represent block and
* character access to the special file. The "block" and "char" implicit edges
* exist if and only if the vertex has defined bdevsw and cdevsw, respectively.
*/
#define EDGE_PLACE_WANT_CURRENT GRAPH_EDGE_PLACE_NONE
#define EDGE_PLACE_WANT_CONNECTPT 1
#define EDGE_PLACE_WANT_BDEVSW 2
#define EDGE_PLACE_WANT_CDEVSW 3
#define EDGE_PLACE_WANT_REAL_EDGES 4
#define HWGRAPH_RESERVED_PLACES 4
/* Root of hwgraph */
extern vertex_hdl_t hwgraph_root;
/* Operations on the hwgraph: init, summary_get, visit */
extern void hwgraph_init(void);
extern graph_error_t hwgraph_summary_get(graph_attr_t *);
extern graph_error_t hwgraph_vertex_visit(int (*)(void *, vertex_hdl_t), void *, int *, vertex_hdl_t *);
/* Operations on VERTICES: create, destroy, combine, clone, get_next, ref, unref */
extern graph_error_t hwgraph_vertex_create(vertex_hdl_t *);
extern graph_error_t hwgraph_vertex_destroy(vertex_hdl_t);
#if NOTDEF
extern graph_error_t hwgraph_vertex_combine(vertex_hdl_t, vertex_hdl_t);
#endif /* NOTDEF */
extern graph_error_t hwgraph_vertex_clone(vertex_hdl_t, vertex_hdl_t *);
extern graph_error_t hwgraph_vertex_get_next(vertex_hdl_t *, graph_vertex_place_t *);
extern graph_error_t hwgraph_vertex_ref(vertex_hdl_t);
extern graph_error_t hwgraph_vertex_unref(vertex_hdl_t);
/* Operations on EDGES: add, remove, get_next */
extern graph_error_t hwgraph_edge_add(vertex_hdl_t, vertex_hdl_t, char *);
extern graph_error_t hwgraph_edge_remove(vertex_hdl_t, char *, vertex_hdl_t *);
extern graph_error_t hwgraph_edge_get(vertex_hdl_t, char *, vertex_hdl_t *);
extern graph_error_t hwgraph_edge_get_next(vertex_hdl_t, char *, vertex_hdl_t *, graph_edge_place_t *);
/* Special pre-defined edge labels */
#define HWGRAPH_EDGELBL_HW "hw"
#define HWGRAPH_EDGELBL_DOT "."
#define HWGRAPH_EDGELBL_DOTDOT ".."
#define HWGRAPH_EDGELBL_BLK _HWGRAPH_NAME_BLOCK
#define HWGRAPH_EDGELBL_CHAR _HWGRAPH_NAME_CHAR
/* Operations on LABELLED INFORMATION: add, remove, replace, get, get_next */
extern graph_error_t hwgraph_info_add_LBL(vertex_hdl_t, char *, arbitrary_info_t);
extern graph_error_t hwgraph_info_remove_LBL(vertex_hdl_t, char *, arbitrary_info_t *);
extern graph_error_t hwgraph_info_replace_LBL(vertex_hdl_t, char *, arbitrary_info_t, arbitrary_info_t *);
extern graph_error_t hwgraph_info_get_LBL(vertex_hdl_t, char *, arbitrary_info_t *);
extern graph_error_t hwgraph_info_get_next(vertex_hdl_t, char *, arbitrary_info_t *, graph_info_place_t *);
extern graph_error_t hwgraph_info_export_LBL(vertex_hdl_t, char *, short);
extern graph_error_t hwgraph_info_unexport_LBL(vertex_hdl_t, char *);
/*
** Operations on locator STRINGS: get_component, path_add,
** traverse, string_to_dev, add_device
*/
extern graph_error_t hwgraph_string_get_component(char *, char *, int *, int *);
extern graph_error_t hwgraph_path_add(vertex_hdl_t, vertex_hdl_t, char *, vertex_hdl_t *);
extern graph_error_t hwgraph_traverse(vertex_hdl_t, char *, vertex_hdl_t *);
extern vertex_hdl_t hwgraph_string_to_vertex(char *);
extern dev_t hwgraph_string_to_dev(char *);
extern graph_error_t hwgraph_device_add(vertex_hdl_t, char *, char *, vertex_hdl_t *);
/*
** set/get routines for indexed information and predefined labels:
** cdevsw, bdevsw, traverse routine
*/
extern int hwgraph_cdevsw_set(vertex_hdl_t, struct cdevsw *);
extern struct cdevsw * hwgraph_cdevsw_get(vertex_hdl_t);
extern int hwgraph_bdevsw_set(vertex_hdl_t, struct bdevsw *);
extern struct bdevsw * hwgraph_bdevsw_get(vertex_hdl_t);
extern graph_error_t hwgraph_traverse_set(vertex_hdl_t, traverse_fn_t);
extern traverse_fn_t hwgraph_traverse_get(vertex_hdl_t);
extern void hwgraph_fastinfo_set(vertex_hdl_t, arbitrary_info_t);
extern arbitrary_info_t hwgraph_fastinfo_get(vertex_hdl_t);
extern void device_info_set(dev_t device, void *info);
extern void *device_info_get(dev_t device);
/* Support for INVENTORY */
struct inventory_s;
struct invplace_s;
extern struct invplace_s invplace_none;
extern graph_error_t hwgraph_inventory_add(vertex_hdl_t,
int class, int type, char ctlr, char unit, int state);
extern graph_error_t hwgraph_inventory_get_next(struct invplace_s *, struct inventory_s **);
/* Support for file systems */
extern graph_error_t hwgraph_connectpt_set(vertex_hdl_t, vertex_hdl_t);
extern vertex_hdl_t hwgraph_connectpt_get(vertex_hdl_t);
/* Support for general topology manipulation */
extern graph_error_t hwgraph_vertex_name_get(vertex_hdl_t, char *, uint);
extern char *vertex_to_name(vertex_hdl_t, char *, uint);
extern void vertex_msg(vertex_hdl_t vhdl, int level, char *fmt, ...);
extern vertex_hdl_t device_master_get(vertex_hdl_t);
extern cnodeid_t master_node_get(vertex_hdl_t);
extern cpuid_t cpuvertex_to_cpuid(vertex_hdl_t);
extern cnodeid_t nodevertex_to_cnodeid(vertex_hdl_t);
/* Not for use by drivers */
struct vnode;
extern dev_t hwgraph_vnode_to_dev(struct vnode *, struct cred *);
extern int device_master_set(vertex_hdl_t vhdl, vertex_hdl_t master);
extern void mark_nodevertex_as_node(vertex_hdl_t vhdl, cnodeid_t cnodeid);
extern void mark_cpuvertex_as_cpu(vertex_hdl_t vhdl, cpuid_t cpuid);
extern void hwgfs_vertex_destroy(vertex_hdl_t vhdl);
/*
* The generic graph code defines "information descriptors" that are associated
* with each piece of labelled information. hwgraph layer chooses to use these
* info descriptors to indicate whether or not the associated labelled information
* should be exported through hwgfs attr_get calls. If the information should
* NOT be exported, the descriptor is set to PRIVATE. If the information should
* be exported, the descriptor is set to EXPORT. If the information is a pointer
* to information that should be exported, the descriptor is set to the number
* of bytes that should be exported.
*
* It is left to user-level code to interpret exported information.
*
* By default, labelled information is PRIVATE. A caller explicitly
* exports any information it wants to via hwgraph_info_export_LBL.
* If information is ever hwgraph_info_replace_LBL'ed, it must be
* re-exported.
*/
#define INFO_DESC_PRIVATE -1 /* default */
#define INFO_DESC_EXPORT 0 /* export info itself */
extern graph_error_t hwgraph_info_get_exported_LBL(vertex_hdl_t, char *,
short *, arbitrary_info_t *);
extern graph_error_t hwgraph_info_get_next_exported_LBL(vertex_hdl_t, char *,
short *, arbitrary_info_t *, graph_info_place_t *);
#endif /* _KERNEL */
#define _HWGRAPH_NAME_BLOCK "block"
#define _HWGRAPH_NAME_CHAR "char"
#endif /* _HWGRAPH_H */
stand/arcs/include/sys/mace_regs.h
+80
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/*****************************************************************************
* $Id: mace_regs.h,v 1.1 1996/01/18 17:27:16 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE Registers
*
*/
#ifdef __cplusplus
/*extern "C" {*/
#endif
#ifndef __MACE_REG_T
#define __MACE_REG_T
typedef unsigned long long reg_t;
#endif /* __MACE_REG_T */
#include "mace_regs_audio.h"
#include "mace_regs_crime.h"
#include "mace_regs_ether.h"
#include "mace_regs_iic.h"
#include "mace_regs_isa.h"
#include "mace_regs_keyboard.h"
#include "mace_regs_pci.h"
#include "mace_regs_serial.h"
#include "mace_regs_timers.h"
#include "mace_regs_video.h"
#define MACE_OFFSET 0x1f000000
#define MACE_OFFSET_CRIME 0x000000
#define MACE_OFFSET_PCI_CONTROL 0x080000
#define MACE_OFFSET_PCI_CONFIG 0x084000
#define MACE_OFFSET_VIDEO_IN1 0x100000
#define MACE_OFFSET_VIDEO_IN2 0x180000
#define MACE_OFFSET_VIDEO_OUT 0x200000
#define MACE_OFFSET_ETHER 0x280000
#define MACE_OFFSET_ETHER_FIFO 0x280100
#define MACE_OFFSET_AUDIO 0x300000
#define MACE_OFFSET_ISA_DMA 0x310000
#define MACE_OFFSET_KEYBOARD 0x320000
#define MACE_OFFSET_IIC 0x330000
#define MACE_OFFSET_TIMERS 0x340000
#define MACE_OFFSET_COMPARE1 0x350000
#define MACE_OFFSET_COMPARE2 0x360000
#define MACE_OFFSET_COMPARE3 0x370000
#define MACE_OFFSET_ISA 0x380000
#define MACE_OFFSET_PAR 0x384000
#define MACE_OFFSET_SER1 0x388000
#define MACE_OFFSET_SER2 0x38c000
#define MACE_OFFSET_PROM 0xC00000
#ifdef __cplusplus
/*}*/
#endif
/* === */
stand/arcs/include/sys/mace_regs_audio.h
+34
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/*****************************************************************************
* $Id: mace_regs_audio.h,v 1.1 1996/01/18 17:27:28 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE Audio Registers
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/* === */
stand/arcs/include/sys/mace_regs_crime.h
+34
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@@ -0,0 +1,34 @@
/*****************************************************************************
* $Id: mace_regs_crime.h,v 1.1 1996/01/18 17:27:39 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE Audio Registers
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/* === */
stand/arcs/include/sys/mace_regs_ether.h
+34
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@@ -0,0 +1,34 @@
/*****************************************************************************
* $Id: mace_regs_ether.h,v 1.1 1996/01/18 17:27:47 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE Ethernet Registers
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/* === */
stand/arcs/include/sys/mace_regs_iic.h
+136
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@@ -0,0 +1,136 @@
/*****************************************************************************
* $Id: mace_regs_iic.h,v 1.1 1996/01/18 17:27:54 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE I2C Registers
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/* === */
#ifdef __cplusplus
/*extern "C" {*/
#endif
#ifndef __MACE_REG_T
#define __MACE_REG_T
typedef unsigned long long reg_t;
#endif /* __MACE_REG_T */
/*
* Control and Status Register (CSR) Definitions
*/
/* CSR bit shift counts */
#define CSR_MASK 0xff /* mask for CSR */
#define CSR_FISC_SHIFT 0 /* force idle state control */
#define CSR_BDC_SHIFT 1 /* bus direction control */
#define CSR_LBC_SHIFT 2 /* last byte control */
#define CSR_RSVD_SHIFT 3 /* reserved */
#define CSR_TS_SHIFT 4 /* transfer status (read only) */
#define CSR_AS_SHIFT 5 /* acknowledge status (read only) */
#define CSR_RSVD1_SHIFT 6 /* reserved */
#define CSR_BES_SHIFT 7 /* bus error status (read only) */
/* CSR reset values for each bit */
#define CSR_FISC_RESET_VALUE 0 /* force idle state control */
#define CSR_BDC_RESET_VALUE 0 /* bus direction control */
#define CSR_LBC_RESET_VALUE 0 /* last byte control */
#define CSR_RSVD_RESET_VALUE 0 /* reserved */
#define CSR_TS_RESET_VALUE 0 /* transfer status */
#define CSR_AS_RESET_VALUE 0 /* acknowledge status */
#define CSR_RSVD1_RESET_VALUE 0 /* reserved */
#define CSR_BES_RESET_VALUE 0 /* bus error status */
/*
* Configuration and Reset Register (CRR) Definitions
*/
/* CRR bit shift counts */
#define CRR_MASK 0x3f /* mask for CSR */
#define CRR_RESET_SHIFT 0 /* RESET */
#define CRR_FME_SHIFT 1 /* Fast mode enable */
#define CRR_DPO_SHIFT 2 /* Data pin override */
#define CRR_CPO_SHIFT 3 /* Clock pin override */
#define CRR_DICV_SHIFT 4 /* Data input current value (read only) */
#define CRR_CICV_SHIFT 5 /* Clock input current value (read only) */
/* CRR reset values for each bit */
#define CRR_RESET_RESET_VALUE 0 /* RESET */
#define CRR_FME_RESET_VALUE 0 /* Fast mode enable */
#define CRR_DPO_RESET_VALUE 0 /* Data pin override */
#define CRR_CPO_RESET_VALUE 0 /* Clock pin override */
#define CRR_DICV_RESET_VALUE X /* Data input current value */
/* no reset value */
#define CRR_CICV_RESET_VALUE X /* Clock input current value */
/* no reset value */
typedef struct cont_stat_reg_s {
reg_t i2cpad:56; /* 63:8 */
reg_t i2c_bus_err_status:1; /* 7 */
reg_t i2c_rsvd1:1; /* 6 */
reg_t i2c_ack_status:1; /* 5 */
reg_t i2c_xfer_status:1; /* 4 */
reg_t i2c_rsvd2:1; /* 3 */
reg_t i2c_last_byte_control:1; /* 2 */
reg_t i2c_bus_dir_control:1; /* 1 */
reg_t i2c_force_idle_control:1; /* 0 */
} cont_stat_reg_s;
typedef struct config_reset_reg_s {
reg_t i2cpad1:58; /* 63:6 */
reg_t i2c_clk_input_current:1; /* 5 */
reg_t i2c_data_input_current:1; /* 4 */
reg_t i2c_clk_pin_ovrrde:1; /* 3 */
reg_t i2_data_pin_ovrrde:1; /* 2 */
reg_t i2c_fast_mode_enable:1; /* 1 */
reg_t i2c_reset:1; /* 0 */
} config_reset_reg_s;
typedef union config_reset_reg_u {
reg_t word;
config_reset_reg_s bits;
} config_reset_reg_t;
#define I2C_MACE_ADDR (void *)((unsigned long)(MACE_OFFSET) | \
(unsigned long)(MACE_OFFSET_IIC))
#define I2C_PHYS_ADDR (void *)((unsigned long)(I2C_MACE_ADDR) | \
(unsigned long)(0xA0000000))
typedef struct {
reg_t i2c_config_reset;
reg_t i2c_rsvd1;
reg_t i2c_cont_status;
reg_t i2c_data;
} MaceI2CAddr;
#ifdef __cplusplus
/*}*/
#endif
/* === */
stand/arcs/include/sys/mace_regs_isa.h
+34
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@@ -0,0 +1,34 @@
/*****************************************************************************
* $Id: mace_regs_isa.h,v 1.1 1996/01/18 17:28:06 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE Audio Registers
*
*/
#ifdef __cplusplus
/*extern "C" {*/
#endif
#ifdef __cplusplus
/*}*/
#endif
/* === */
stand/arcs/include/sys/mace_regs_keyboard.h
+34
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@@ -0,0 +1,34 @@
/*****************************************************************************
* $Id: mace_regs_keyboard.h,v 1.1 1996/01/18 17:28:15 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE Keyboard Registers
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/* === */
stand/arcs/include/sys/mace_regs_kybdms.h
+34
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@@ -0,0 +1,34 @@
/*****************************************************************************
* $Id: mace_regs_kybdms.h,v 1.1 1996/01/18 17:28:33 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE Keyboard Registers
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/* === */
stand/arcs/include/sys/mace_regs_pci.h
+34
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@@ -0,0 +1,34 @@
/*****************************************************************************
* $Id: mace_regs_pci.h,v 1.1 1996/01/18 17:28:41 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE PCI Registers
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/* === */
stand/arcs/include/sys/mace_regs_serial.h
+34
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@@ -0,0 +1,34 @@
/*****************************************************************************
* $Id: mace_regs_serial.h,v 1.1 1996/01/18 17:28:49 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE Serial Registers
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/* === */
stand/arcs/include/sys/mace_regs_timers.h
+34
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@@ -0,0 +1,34 @@
/*****************************************************************************
* $Id: mace_regs_timers.h,v 1.1 1996/01/18 17:28:59 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead MACE Timers Registers
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/* === */
stand/arcs/include/sys/mace_regs_video.h
+365
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/*****************************************************************************
* $Id: mace_regs_video.h,v 1.1 1996/01/18 17:29:10 montep Exp $
*
* Copyright 1993, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
* RESTRICTED RIGHTS LEGEND:
* Use, duplication or disclosure by the Government is subject to restrictions
* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
* rights reserved under the Copyright Laws of the United States.
*
*****************************************************************************/
/*
* Moosehead Video Registers
*
*/
#ifdef __cplusplus
/*extern "C" {*/
#endif
#ifndef __MACE_REG_T
#define __MACE_REG_T
typedef unsigned long long reg_t;
#endif /* __MACE_REG_T */
typedef struct videohwregs_s {
reg_t vhw_cfg;
} videohwregs_s;
typedef union videohwregs_u {
videohwregs_s reg;
reg_t pad[0x8000];
} vidhwregs_t;
typedef struct controlreg_s {
reg_t pad:56; /* 63:8 */
reg_t enable_fifo_ovflw:1; /* 7 */
reg_t enable_vertical_ovrflw:1; /* 6 */
reg_t enable_horizontal_ovrflw:1; /* 5 */
reg_t enable_buffer_ovrflw:1; /* 4 */
reg_t enable_lostsync:1; /* 3 */
reg_t enable_dmacomplete:1; /* 2 */
reg_t enable_verticalsync:1; /* 1 */
reg_t enable_dma:1; /* 0 */
} controlreg_s;
typedef union controlreg_u {
reg_t word;
controlreg_s bits;
} controlreg_t;
typedef struct statusreg_s {
reg_t pad1:54; /* 63:10 */
reg_t dma_complete_status:1; /* 9 */
reg_t sync_present_status:1; /* 8 */
reg_t fifo_ovrflw:1; /* 7 */
reg_t vertical_ovrflw:1; /* 6 */
reg_t horizontal_ovrflw:1; /* 5 */
reg_t buffer_ovrflw:1; /* 4 */
reg_t lost_sync:1; /* 3 */
reg_t dma_complete:1; /* 2 */
reg_t vertical_sync:1; /* 1 */
reg_t pad2:1; /* 0 */
} statusreg_s;
typedef union statusreg_u {
reg_t word;
statusreg_s bits;
} statusreg_t;
typedef struct configinreg_s {
reg_t pad1:53; /* 63:11 */
reg_t vin_source:2; /* 10:9 */
reg_t mode:2; /* 8:7 */
reg_t interleaved:1; /* 6 */
reg_t ecc:1; /* 5 */
reg_t precision:1; /* 4 */
reg_t format:3; /* 3:1 */
reg_t reset:1; /* 0 */
} configinreg_s;
typedef union configinreg_u {
reg_t word;
configinreg_s bits;
} configinreg_t;
typedef struct configoutreg_s {
reg_t pad1:35; /* 63:19 */
reg_t audio_genlock:2; /* 18:17 */
reg_t gbe_genlock:2; /* 16:15 */
reg_t out_genlock:2; /* 14:13 */
reg_t svout_source:2; /* 12:11 */
reg_t pvout_source:2; /* 10:9 */
reg_t mode:2; /* 8:7 */
reg_t interleaved:1; /* 6 */
reg_t alpha_out:1; /* 5 */
reg_t precision:1; /* 4 */
reg_t format:3; /* 3:1 */
reg_t reset:1; /* 0 */
} configoutreg_s;
/* reset field */
#define CONFIG_ENABLE 0
#define CONFIG_RESET 1
/* format */
#define CONFIG_FORMAT_RGBA8 0
#define CONFIG_FORMAT_ABGR8 1
#define CONFIG_FORMAT_RGBA5_DITHERED 2
#define CONFIG_FORMAT_RGBA5 3
#define CONFIG_FORMAT_YUV8 4
#define CONFIG_FORMAT_YUV10 5
/* precision */
#define CONFIG_PRECISION_8 0
#define CONFIG_PRECISION_10 1
/* ecc */
#define CONFIG_ECC_OFF 0
#define CONFIG_ECC_ON 1
/* alpha_out */
#define CONFIG_YUVONLY 0
#define CONFIG_YUVA 1
/* interleaved */
#define CONFIG_FIELDS 0
#define CONFIG_INTERLEAVED 1
/* mode */
#define CONFIG_LINEAR 0
#define CONFIG_TILED 2
#define CONFIG_MIPMAPPED 3
/* pvout_source, svout_source */
#define CONFIG_YUVOUT 0
#define CONFIG_ALPHAOUT 1
#define CONFIG_PRIMD1OUT 2
#define CONFIG_SECD1OUT 3
/* out_genlock, gbe_genlock, audio_genlock */
#define CONFIG_INTERNALTIMING 0
#define CONFIG_PRIMD1TIMING 2
#define CONFIG_SECD1TIMING 3
typedef union configoutreg_u {
reg_t word;
configoutreg_s bits;
} configoutreg_t;
typedef struct clipreg_s {
reg_t scaling_on:1; /* 63 */
reg_t pad:7; /* 62:56 */
reg_t scaling_ratio:8; /* 55:48 */
reg_t count:16; /* 47:32 */
reg_t end:16; /* 31:16 */
reg_t start:16; /* 15:0 */
} clipreg_s;
typedef union clipreg_u {
reg_t word;
clipreg_s bits;
} clipreg_t;
typedef struct padreg_s {
reg_t pad1:16; /* 63:48 */
reg_t count:16; /* 47:32 */
reg_t pad2:16; /* 31:16 */
reg_t start:16; /* 15:0 */
} padreg_s;
typedef union padreg_u {
reg_t word;
padreg_s bits;
} padreg_t;
typedef struct filtinreg_s {
reg_t pad1:22; /* 31:10 */
reg_t dma_complete_status:1; /* 9 */
reg_t sync_present_status:1; /* 8 */
reg_t fifo_ovrflw:1; /* 7 */
reg_t vertical_ovrflw:1; /* 6 */
reg_t horizontal_ovrflw:1; /* 5 */
reg_t buffer_ovrflw:1; /* 4 */
reg_t lost_sync:1; /* 3 */
reg_t dma_complete:1; /* 2 */
reg_t vertical_sync:1; /* 1 */
reg_t pad2:1; /* 0 */
} filtinreg_s;
typedef union filtinreg_u {
reg_t word;
filtinreg_s bits;
} filtinreg_t;
typedef struct filtoutreg_s {
reg_t pad1:22; /* 31:10 */
reg_t dma_complete_status:1; /* 9 */
reg_t sync_present_status:1; /* 8 */
reg_t fifo_ovrflw:1; /* 7 */
reg_t vertical_ovrflw:1; /* 6 */
reg_t horizontal_ovrflw:1; /* 5 */
reg_t buffer_ovrflw:1; /* 4 */
reg_t lost_sync:1; /* 3 */
reg_t dma_complete:1; /* 2 */
reg_t vertical_sync:1; /* 1 */
reg_t pad2:1; /* 0 */
} filtoutreg_s;
typedef union filtoutreg_u {
reg_t word;
filtoutreg_s bits;
} filtoutreg_t;
typedef struct vtimoutreg_s {
reg_t pad1:22; /* 31:10 */
reg_t dma_complete_status:1; /* 9 */
reg_t sync_present_status:1; /* 8 */
reg_t fifo_ovrflw:1; /* 7 */
reg_t vertical_ovrflw:1; /* 6 */
reg_t horizontal_ovrflw:1; /* 5 */
reg_t buffer_ovrflw:1; /* 4 */
reg_t lost_sync:1; /* 3 */
reg_t dma_complete:1; /* 2 */
reg_t vertical_sync:1; /* 1 */
reg_t pad2:1; /* 0 */
} vtimoutreg_s;
typedef union vtimoutreg_u {
reg_t word;
vtimoutreg_s bits;
} vtimoutreg_t;
typedef struct intvtimreg_s {
reg_t pad1:22; /* 31:10 */
reg_t dma_complete_status:1; /* 9 */
reg_t sync_present_status:1; /* 8 */
reg_t fifo_ovrflw:1; /* 7 */
reg_t vertical_ovrflw:1; /* 6 */
reg_t horizontal_ovrflw:1; /* 5 */
reg_t buffer_ovrflw:1; /* 4 */
reg_t lost_sync:1; /* 3 */
reg_t dma_complete:1; /* 2 */
reg_t vertical_sync:1; /* 1 */
reg_t pad2:1; /* 0 */
} intvtimreg_s;
typedef union intvtimreg_u {
reg_t word;
intvtimreg_s bits;
} intvtimreg_t;
typedef struct syncdelayreg_s {
reg_t pad1:22; /* 31:10 */
reg_t dma_complete_status:1; /* 9 */
reg_t sync_present_status:1; /* 8 */
reg_t fifo_ovrflw:1; /* 7 */
reg_t vertical_ovrflw:1; /* 6 */
reg_t horizontal_ovrflw:1; /* 5 */
reg_t buffer_ovrflw:1; /* 4 */
reg_t lost_sync:1; /* 3 */
reg_t dma_complete:1; /* 2 */
reg_t vertical_sync:1; /* 1 */
reg_t pad2:1; /* 0 */
} syncdelayreg_s;
typedef union syncdelayreg_u {
reg_t word;
syncdelayreg_s bits;
} syncdelayreg_t;
typedef struct vidinchregs_s {
controlreg_t control;
statusreg_t status;
configinreg_t config;
reg_t next_desc;
reg_t fld_offset;
reg_t line_width;
clipreg_t hclip_odd;
clipreg_t vclip_odd;
clipreg_t hclip_even;
clipreg_t vclip_even;
filtinreg_t filt_in;
reg_t alpha_in;
} vidinchregs_s;
typedef union vidinchregs_u {
vidinchregs_s reg;
reg_t pad[0x8000];
} vidinchregs_t;
typedef struct vidoutchregs_s {
controlreg_t control;
statusreg_t status;
configoutreg_t config;
reg_t next_desc;
reg_t fld_offset;
reg_t line_size;
padreg_t hpad_odd;
padreg_t vpad_odd;
padreg_t hpad_even;
padreg_t vpad_even;
filtoutreg_t filt_out;
vtimoutreg_t vtim_out;
intvtimreg_t int_vtim;
syncdelayreg_t sync_delay;
} vidoutchregs_s;
typedef union vidoutchregs_u {
vidoutchregs_s reg;
reg_t pad[0x8000];
} vidoutchregs_t;
typedef struct vidregs {
vidhwregs_t hw;
vidinchregs_t vidin[2];
vidoutchregs_t vidout;
} vidregs_t;
#define CONTROL 0x0000 /* I/O */
#define STATUS 0x0008 /* I/O */
#define CONFIG 0x0010 /* I/O */
#define NEXT_DESC 0x0018 /* I/O */
#define FLD_OFFSET 0x0020 /* I/O */
#define LINE_WIDTH 0x0028 /* I/O */
#define HCLIP_ODD 0x0030 /* I */
#define VCLIP_ODD 0x0038 /* I */
#define ALPHAIN_ODD 0x0040 /* I */
#define HCLIP_EVEN 0x0048 /* I */
#define VCLIP_EVEN 0x0050 /* I */
#define ALPHAIN_EVEN 0x0058 /* I */
#define HPAD_ODD 0x0030 /* O */
#define VPAD_ODD 0x0038 /* O */
#define HPAD_EVEN 0x0040 /* O */
#define VPAD_EVEN 0x0048 /* O */
#define GEN_DELAY 0x0050 /* O */
#define VHW_CFG 0x0058 /* O */
#define VID_DESC_CACHE 0x0080 /* I/O */
#define VID_DESC_CACHELEN 0x0038 /* I/O */
#define MV_IN_REG_MIN CONTROL
#define MV_IN_REG_MAX ALPHAIN_EVEN
#define MV_OUT_REG_MIN CONTROL
#define MV_OUT_REG_MAX VHW_CFG
#ifdef __cplusplus
/*}*/
#endif
/* === */
stand/arcs/include/sys/newscsi.h
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#ifndef _NSCSI_
#define _NSCSI_
#ident "$Revision: 1.14 $"
/*
* Calls from high level driver to low level driver
*
* The following declares arrays of function pointers. Index into them
* with the driver number of the low level driver. The driver number
* can be found out with SCSI_DRIVER_NUMBER (below). Only scsi_command()
* may be called from interrupt. The others should in general only be
* called from device open and close routines.
*
* Example call:
* (*scsi_command[scsi_driver_number(dev)])(scsi_request)
*
* scsi_command() issues a SCSI command to the low level SCSI driver.
*
* If a contingent allegiance condition is entered (check condition
* command status), a request sense will be automatically performed.
* If the sr_sense field of the request is not null, the sense data
* will be copied to the sr_sense address, but not more than
* sr_senselen bytes.
*
* In addition, whenever there is a contingent allegiance or SCSI bus
* reset, all commands queued in the driver and on the device (except
* for the command causing or noticing the error) will be returned
* with the sr_status field set to SC_ATTN. New commands will continue
* to be returned with this status until the flag bit SRF_AEN_ACK is
* set in sr_flags.
*
* Before any command queueing is done, the device driver should do
* a mode sense on mode page 0xA (control mode page) to discover the
* QErr bit setting. Error handling will not work correctly in a
* queued environment unless the QErr bit is set.
*
* scsi_alloc() initializes a connection between a device level driver and
* a host adaptor driver for a given controller, target, and lun. It
* will cause the low level driver to initialize structures needed for
* communication if it has not already done so.
*
* The opt argument gives additional information about how the driver
* would like to talk to the device. Currently, two options are
* allowed. SCSIALLOC_EXCLUSIVE causes the device to be allocated
* exclusively for the use of the calling driver. If a device is
* allocated for exclusive use, no other driver may access it. Also,
* if a device is already in use by another driver, exclusive or not,
* and exclusive alloc will fail. SCSIALLOC_QDEPTH is a mask for
* an eight bit value specifying how many commands a device driver
* would like to queue. It is to be considered advice only, and
* will not necessarily be followed.
*
* The cb argument is used as a callback if a request sense was done
* as a result of a check condition from a command. If the cb
* argument is NULL, no callbacks will be done. Note that having
* a callback set may result in a driver seeing the error twice.
* The purpose of the callback is to give make sure that a given
* driver gets all sense data from a device, even if it is returned
* with a command issued by a different driver. Only one driver is
* allowed to have a callback. scsi_alloc() will fail if a callback
* is requested, and another driver currently has a callback
* registered.
*
* A return value of 0 indicates an error. Non-zero is success.
*
* scsi_free() terminates a connection between a device level driver and
* the host adaptor driver. The host adaptor driver will free any
* structures that it does not need.
*
* The callback argument should be the same as that given to
* scsi_alloc(). If it does not match, the callback will not be
* freed up.
*
* scsi_info() issues an inquiry to the given controller, target, and lun,
* returning a pointer to the scsi_target_info structure. It should
* be used to see if the device is appropriate to the driver making
* the call.
*
* The si_maxq field in the scsi_target_info structure (returned by
* scsi_info()) will give queueing information.
*
* scsi_abort() aborts the request passed as an argument. If it is
* currently active, an abort message will be sent to the device.
* A non-zero return indicates that the abort was successful. Not
* all host adaptors support this function.
*
* scsi_reset() issues a bus reset to the controller number requested.
* A non-zero return indicates a successful reset. Not all host
* adaptors support this reset function.
*
* scsi_driver_table is an array indexed by adaptor (or bus) number.
* It returns the adaptor type (a constant defined by the
* SCSIDRIVER_XXXX #define's below. The SCSI_XXXSTART #defines
* define the starting adaptor number for the various controller
* types. The SCSI_XXXCOUNT are the number of adaptors (or buses)
* for a given controller type. Both SCSIDRIVER_WD93 and
* SCSIDRIVER_WD95 are part of SGI-built SCSI controllers, and so
* use the SCSI_SGISTART and SCSI_SGICOUNT #define's. To give an
* example of how this works, on an Everest, the second bus on
* jaguar controller 4 would be considered adaptor number 137.
* SCSI_JAGSTART is 128 + (controller 4 * 2 buses per controller) +
* bus 1 (or the second bus on the controller) is adaptor (or bus)
* #137 from the point of view of a SCSI device driver.
*/
struct scsi_request;
extern void (*scsi_command[])(struct scsi_request *req);
extern int (*scsi_alloc[])(u_char c, u_char t, u_char l, int opt, void (*cb)());
extern void (*scsi_free[])(u_char c, u_char t, u_char l, void (*cb)());
extern struct scsi_target_info * (*scsi_info[])(u_char c, u_char t, u_char l);
extern int (*scsi_abort[])(struct scsi_request *req);
extern int (*scsi_dump[])(u_char c);
extern u_char scsi_driver_table[];
#define SCSIALLOC_EXCLUSIVE 0x100
#define SCSIALLOC_QDEPTH 0x0FF
#define SCSIALLOCOK 1 /* succesful return value from scsi_alloc function */
/*
* To find out the driver number of a device, index into scsi_driver_table
* with the adaptor number.
*/
#define SCSI_TYPE_COUNT 4
#define SCSIDRIVER_NULL 0
#define SCSIDRIVER_WD93 1
#define SCSIDRIVER_JAG 2
#define SCSIDRIVER_WD95 3
/*
* Defines for number of SCSI buses
*/
#if defined(EVEREST)
#define SCSI_SGISTART 0
#define SCSI_SGICOUNT 128
#define SCSI_JAGSTART 128
#define SCSI_JAGCOUNT 16
#define SCSI_MAXCTLR 144
#define SCSI_MAXTARG 16
#elif defined(IP22) || defined(IP26)
#define SCSI_SGISTART 0
#define SCSI_SGICOUNT 2
#define SCSI_MAXCTLR 2
#define SCSI_MAXTARG 16
#elif defined(IP30)
#define SCSI_SGISTART 0
#define SCSI_SGICOUNT 2
#define SCSI_MAXCTLR 16
#define SCSI_MAXTARG 16
#elif defined(SN0)
#define SCSI_SGISTART 0
#define SCSI_SGICOUNT 2
#define SCSI_MAXCTLR 128
#define SCSI_MAXTARG 16
#else
#define SCSI_SGISTART 0
#define SCSI_SGICOUNT 1
#define SCSI_MAXCTLR 1
#define SCSI_MAXTARG 8
#endif
#define SCSI_MAXLUN 8
/*
* SCSI minor number masks and shifts
*/
#define SCSI_UNIT_MASK 0xF
#define DKSC_UNIT_SHIFT 4
#define TPSC_UNIT_SHIFT 5
#define SCSI_LUN_MASK 0x7
#define DKSC_LUN_SHIFT 15
#define TPSC_LUN_SHIFT 15
#define DKSC_CTLR_MASK 0x7F
#define TPSC_CTLR_MASK 0x3F
#define DS_CTLR_MASK 0x7F
#define DKSC_CTLR_SHIFT 8
#define TPSC_CTLR_SHIFT 9
#define DS_CTLR_SHIFT 7
#define DKSC_UNIT(dev) ((dev >> DKSC_UNIT_SHIFT) & SCSI_UNIT_MASK)
#define TPSC_UNIT(dev) ((dev >> TPSC_UNIT_SHIFT) & SCSI_UNIT_MASK)
#define DKSC_LUN(dev) ((dev >> DKSC_LUN_SHIFT) & SCSI_LUN_MASK)
#define TPSC_LUN(dev) ((dev >> TPSC_LUN_SHIFT) & SCSI_LUN_MASK)
#define DKSC_CTLR(dev) ((dev >> DKSC_CTLR_SHIFT) & DKSC_CTLR_MASK)
#define TPSC_CTLR(dev) ((dev >> TPSC_CTLR_SHIFT) & TPSC_CTLR_MASK)
#define DS_CTLR(dev) ((dev >> DS_CTLR_SHIFT) & DS_CTLR_MASK)
/*
* SCSI sense defines and message external declarations
*/
#undef SC_NUMADDSENSE
#define SC_NUMSENSE 0x10 /* # of messages in scsi_key_msgtab */
#define SC_NUMADDSENSE 0x4a /* # of messages in scsi_addit_msgtab */
extern char *scsi_key_msgtab[], *scsi_addit_msgtab[];
/* base sense error codes */
#define SC_NOSENSE 0x0
#define SC_ERR_RECOVERED 0x1
#define SC_NOT_READY 0x2
#define SC_MEDIA_ERR 0x3
#define SC_HARDW_ERR 0x4
#define SC_ILLEGALREQ 0x5
#define SC_UNIT_ATTN 0x6
#define SC_DATA_PROT 0x7
#define SC_BLANKCHK 0x8
#define SC_VENDUNIQ 0x9
#define SC_COPY_ABORT 0xA
#define SC_CMD_ABORT 0xB
#define SC_EQUAL 0xC
#define SC_VOL_OVERFL 0xD
#define SC_MISCMP 0xE
/* some common extended sense error codes */
#define SC_NO_ADD 0x0 /* no extended sense code */
#define SC_NOINDEX 0x1
#define SC_NOSEEKCOMP 0x2
#define SC_WRITEFAULT 0x3
#define SC_NOTREADY 0x4
#define SC_NOTSEL 0x5
#define SC_ECC 0x10
#define SC_READERR 0x11
#define SC_NOADDRID 0x12
#define SC_NOADDRDATA 0x13
#define SC_DEFECT_ERR 0x19
#define SC_WRITEPROT 0x27
#define SC_RESET 0x29
/* Possible status bytes returned after a scsi command */
#define ST_GOOD 0
#define ST_CHECK 2
#define ST_COND_MET 4
#define ST_BUSY 8
#define ST_INT_GOOD 16
#define ST_INT_COND_MET 20
#define ST_RES_CONF 24
/* Size of different scsi command classes */
#define SC_CLASS0_SZ 6
#define SC_CLASS1_SZ 10
#define SC_CLASS2_SZ 12
/*
* SCSI host adapter independent target information structure
* This structure is used to pass information between the host adapter drivers
* and the device drivers (disk, tape, etc.).
*/
struct scsi_target_info
{
u_char *si_inq; /* inquiry data */
u_char *si_sense; /* sense data from last request sense */
u_char si_maxq; /* maximum queue depth for driver */
u_char si_qdepth; /* max queue depth so far */
u_char si_qlimit:1; /* boolean "max queue depth reached"? */
};
typedef struct scsi_target_info scsi_target_info_t;
#define SCSI_INQUIRY_LEN 64
#define SCSI_SENSE_LEN 64
#define SCSI_MODESEL_PARAMLIST_LEN 12
/*
* SCSI request structure
* This structure is used by a SCSI device driver to make a request to a
* SCSI host adapter.
*/
struct scsi_request
{
/* values filled in by device driver */
u_char sr_ctlr;
u_char sr_target;
u_char sr_lun;
u_char sr_tag; /* first byte of tag message */
u_char *sr_command; /* scsi command */
ushort sr_cmdlen; /* length of scsi command */
ushort sr_flags; /* direction of data transfer */
ulong sr_timeout; /* in seconds */
u_char *sr_buffer; /* location of data */
uint sr_buflen; /* amount of data to transfer */
u_char *sr_sense; /* where to put sense data in case of CC */
ulong sr_senselen; /* size of buffer allocated for sense data */
void (*sr_notify)(struct scsi_request *); /* callback pointer */
void *sr_bp; /* usually a buf_t pointer */
/* spare pointer used by device driver */
void *sr_dev;
/* spare fields used by host adapter driver */
void *sr_ha; /* usually used for linked list of req's */
void *sr_spare; /* used as spare pointer, int, etc. */
/* results filled in by host adapter driver */
uint sr_status; /* Status of command */
u_char sr_scsi_status; /* SCSI status byte */
u_char sr_ha_flags; /* flags used by host adaptor driver */
short sr_sensegotten; /* number of sense bytes received; -1 == err */
uint sr_resid; /* amount of sr_buflen not transferred */
struct scsi_request *req_forw; /* forward pointer of request */
struct scsi_request *req_back; /* backward pointer of request */
};
typedef struct scsi_request scsi_request_t;
/*
* constants for scsirequest.sr_flags
*/
#define SRF_DIR_IN 0x0001 /* data xfer into memory (DMA write) if set */
#define SRF_FLUSH 0x0002 /* data writeback/inval required */
#define SRF_MAP 0x0008 /* data must be mapped */
#define SRF_MAPBP 0x0010 /* data must be "mapbp"ed */
#define SRF_AEN_ACK 0x0020 /* acknowledge AEN */
/*
* constants for scsirequest.sr_status
*/
#define SC_GOOD 0 /* No error */
#define SC_TIMEOUT 1 /* Timeout on scsi bus */
#define SC_HARDERR 2 /* Hardware or scsi device error */
#define SC_PARITY 3 /* Parity error on the SCSI bus during xfer */
#define SC_MEMERR 4 /* Parity/ECC error on host memory */
#define SC_CMDTIME 5 /* the command timed out */
#define SC_ALIGN 6 /* i/o address wasn't properly aligned */
#define SC_ATTN 7 /* unit attention received on other command */
#define SC_REQUEST 8 /* error in request; malformed, for non-
existent device; no alloc done, etc. */
#endif
stand/arcs/include/sys/ql_firmware_standalone.h
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stand/arcs/include/sys/ql_standalone.h
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stand/arcs/include/sys/scsi.h
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#ifndef __SYS_SCSI_H__
#define __SYS_SCSI_H__
/**************************************************************************
* *
* Copyright (C) 1990, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
#ident "$Revision: 3.40 $"
#include "sys/sema.h" /* mainly so app programs that use this file
will still compile */
/*
* Common SCSI definitions needed by formatter drivers
* and the SCSI interface driver.
*/
#if EVEREST || SN0
#define SC_MAXADAP 150 /* Max number of adapters allowed by the system */
#define SC_MAXTARG 16 /* Max number of targets allowed by the system */
#define SC_MAXLUN 8 /* Max number of lu's allowed by the system */
#elif IP30
#define SC_MAXADAP 16
#define SC_MAXTARG 16
#define SCSI_MAXTARG 16
#define SC_MAXLUN 8
#elif defined(IP32) || defined (MHSIM)
#define SC_MAXADAP 10 /* Moosehead/Roadrunner systems */
#define SC_MAXTARG 16
#define SC_MAXLUN 8
#else
#define SC_MAXADAP 8
#define SC_MAXTARG 8
#define SCSI_MAXTARG 16
#define SC_MAXLUN 8
#endif
#define SCTMSK 7 /* mask to get target id */
#define SCLMSK 7 /* mask to get lun */
/* Possible status bytes returned after a scsi command */
#define ST_GOOD 0
#define ST_CHECK 2
#define ST_COND_MET 4
#define ST_BUSY 8
#define ST_INT_GOOD 16
#define ST_INT_COND_MET 20
#define ST_RES_CONF 24
/* Possible error codes returned by the scsi driver */
#define SC_GOOD 0 /* No error */
#define SC_TIMEOUT 1 /* Timeout on scsi bus */
#define SC_HARDERR 2 /* Hardware or scsi device error */
#define SC_PARITY 3 /* Parity error on the SCSI bus during xfer */
#define SC_MEMERR 4 /* Parity/ECC error on host memory */
#define SC_CMDTIME 5 /* the command timed out */
#define SC_ALIGN 6 /* i/o address wasn't aligned on 4 byte boundary */
#define SC_BUS_RESET 7 /* scsi bus reset occured. The command was */
/* not issued */
/* Size of different scsi command classes */
#define SC_CLASS0_SZ 6
#define SC_CLASS1_SZ 10
#define SC_CLASS2_SZ 12
typedef struct scsisubchan scsisubchan_t;
/*
* Subchannel control record.
*
* This structure encapsulates all the information for a request.
*/
struct scsisubchan {
/* PUBLIC INPUT DATA */
u_char *s_cmd; /* SCSI command */
int s_len; /* Length of command */
struct buf *s_buf; /* transfer data, if any */
void (*s_notify)(scsisubchan_t *); /* Completion routine for async IO */
u_int s_timeoutval; /* Timeout value for transaction */
caddr_t s_caller; /* for callers use; typically identifies
a structure of interest to the caller */
/* PUBLIC OUTPUT DATA */
int s_error; /* SCSI operation error code (below) */
u_char s_status; /* SCSI device status message (below) */
/* PRIVATE DATA */
u_char s_adap; /* Host adapter id */
u_char s_target; /* Target id */
u_char s_lu; /* Logical unit id */
u_char s_syncreg; /* sync reg value if target supports sync */
u_char s_flags; /* Flags, see below */
u_char s_retry; /* Number of error retrys done */
u_char s_syncs; /* this many cmds must succeed before
we can re-enable sync. A hack because it seems to confuse
the drive when we re-enable sync with a check condition
outstanding. */
u_char s_dstid; /* target ORed with direction. Used
with 93A, to set direction flag in chip */
int s_timeid; /* Timeout key */
sema_t s_sem; /* Semaphore for synchronous IO */
caddr_t s_xferaddr; /* Current xfer addr (reselection) */
unsigned s_xferlen; /* Current xfer len (reselection) */
unsigned s_tlen; /* Current working xfer len */
unsigned s_tentative; /* amount transferred during previous
connection -- nonzero when we get a
disconnect without savedatap */
scsisubchan_t *s_link; /* Link for wait or disconnected list */
#ifdef DMA_SCSI /* things like the kernel that actually need it */
dmamap_t *s_map; /* per channel dma map */
#else /* keep struct size the same */
void *s_map;
#endif
};
#define S_BUSY 0x01 /* SCSI operation in progress */
#define S_DISCONNECT 0x02 /* Subchannel is disconnected */
#define S_SAVEDP 0x04 /* Subchannel's data pointers saved */
#define S_SYNC_ON 0x08 /* Channel using synchronous i/o */
#define S_RESYNC 0x10 /* We have (temporarily) negotiated for
async mode on a device because a transfer is too large to be mapped.
Only needed with the 93, not the 93A */
#define S_CANTSYNC 0x20 /* drive can't sync, don't try on
it any more (rejected sync message) */
#define S_RESTART 0x40 /* cmd is being restarted due to
a 'simultaneous' re-select */
#define S_TARGSYNC 0x80 /* target initiated sync mode */
#define SCDMA_IN 0x40 /* bit expected by 93A if data direction
is to host. OR'ed into s_dstid */
#define SC_NUMSENSE 0x10 /* # of messages in scsi_key_msgtab */
#if 0
#define SC_NUMADDSENSE 0x65 /* # of messages in scsi_addit_msgtab */
#endif
#define SC_NUMADDSENSE 0x4a /* A number of drivers use this, but many
* only define 0x4A messages. This is defined
* in multiple header filesi -- want to make
* it the same in all. */
/* base sense error codes */
#define SC_NOSENSE 0x0
#define SC_ERR_RECOVERED 0x1
#define SC_NOT_READY 0x2
#define SC_MEDIA_ERR 0x3
#define SC_HARDW_ERR 0x4
#define SC_ILLEGALREQ 0x5
#define SC_UNIT_ATTN 0x6
#define SC_DATA_PROT 0x7
#define SC_BLANKCHK 0x8
#define SC_VENDUNIQ 0x9
#define SC_COPY_ABORT 0xA
#define SC_CMD_ABORT 0xB
#define SC_EQUAL 0xC
#define SC_VOL_OVERFL 0xD
#define SC_MISCMP 0xE
/* some common extended sense error codes */
#define SC_NO_ADD 0x0 /* no extended sense code */
#define SC_NOINDEX 0x1
#define SC_NOSEEKCOMP 0x2
#define SC_WRITEFAULT 0x3
#define SC_NOTREADY 0x4
#define SC_NOTSEL 0x5
#define SC_ECC 0x10
#define SC_READERR 0x11
#define SC_NOADDRID 0x12
#define SC_NOADDRDATA 0x13
#define SC_DEFECT_ERR 0x19
#define SC_WRITEPROT 0x27
#define SC_RESET 0x29
/* these are the only routines in the low level scsi driver that
can be called by the upper level scsi drivers. */
scsisubchan_t *allocsubchannel(int, int, int);
void freesubchannel(scsisubchan_t *);
void doscsi(scsisubchan_t *);
void scsi_setsyncmode(scsisubchan_t *, int);
u_char *scsi_inq(u_char, u_char, u_char);
int scsidump(int);
extern char *scsi_key_msgtab[], *scsi_addit_msgtab[]; /* in scsi.c */
extern int scsicnt; /* # of SCSI host adapter configured */
void scsi_reset(int adap);
#ifdef IP22_WD95
scsisubchan_t *wd95_allocsubchannel(int, int, int);
void wd95_freesubchannel(scsisubchan_t *);
void wd95_doscsi(scsisubchan_t *);
void wd95_scsi_setsyncmode(scsisubchan_t *, int);
u_char *wd95_scsi_inq(u_char, u_char, u_char);
#endif
#endif /* !__SYS_SCSI_H__ */
stand/arcs/include/sys/scsidev.h
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/**************************************************************************
* *
* Copyright (C) 1986, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
#ident "$Revision: 3.35 $"
/*
* SCSI command interface internal data structures.
*/
#define PSCSI PZERO-1
#define MAXWAIT 4000000 /* Max wait for non-timeout IO
operations */
#define SC_MAXRETRY 4 /* Max number of retries on
parity errs */
typedef struct scsidev scsidev_t;
/*
* Host adapter interface record. Records our state, his info, any
* other nits needed to properly run the adapter. Could be generalized
* by adding a different kind of structure for each device
*/
struct scsidev {
u_char d_flags; /* Flags, see below */
u_char d_ctrlreg; /* value to put in ctrl register */
u_char d_tdata; /* temporary holder for data reg on some intr */
u_char d_adap; /* controller # */
u_char d_ucode; /* ucode revision; 93B only */
struct dmamap *d_map; /* DMA map */
scsisubchan_t *d_consubchan; /* Connected subchannel */
u_int d_retry; /* Retry count */
scsisubchan_t *d_subchan[SC_MAXTARG][SC_MAXLUN];
/* Table of subchannels */
scsisubchan_t *d_waithead; /* Async request waitint list head */
scsisubchan_t *d_waittail; /* Async request waitint list tail */
sema_t d_sleepsem; /* Synchronous request waiting sem */
sema_t d_onlysem; /* 'only' request waiting sem */
short d_sleepcount; /* Synchronous request waiter count */
short d_onlycount; /* Synchronous request waiter count */
lock_t d_qlock; /* Lock for structure flags & queues */
lock_t d_reglock; /* Lock for hardware registers */
volatile u_char *d_addr; /* chip address register */
volatile u_char *d_data; /* chip 'data' register */
};
#define D_BUSY 0x1 /* host adapter in use */
#define D_WD93 0x2 /* is a 93, don't try burst mode dma, etc. */
#define D_WD93A 0x4 /* is a 93A, so we can use burst mode dma */
#define D_WD93B 0x8 /* is a 93B, superset of 93A, fast scsi, queues, etc. */
#define D_ONLY 0x10 /* only onlysem waiters can acquire */
#define D_MAPRETAIN 0x20 /*Set via scuzzy struct d_initflags for systems
* where the DMA map retained across disconnects;
* i.e., a DMA MAP per SCSI channel in use */
#define D_PROMSYNC 0x40 /* Set via scuzzy struct d_initflags for systems
* whose PROM understands sync scsi */
/* Chip registers. */
#define WD93ID 0 /* own id register */
#define WD93CTRL 1 /* control register */
#define WD93TOUT 2 /* timeout register */
#define WD93C1 3 /* command byte 1 */
#define WD93C2 4 /* command byte 1 */
#define WD93C3 5 /* command byte 1 */
#define WD93C4 6 /* command byte 1 */
#define WD93C5 7 /* command byte 1 */
#define WD93C6 8 /* command byte 1 */
#define WD93C7 9 /* command byte 1 */
#define WD93C8 10 /* command byte 1 */
#define WD93C9 11 /* command byte 1 */
#define WD93C10 12 /* command byte 1 */
#define WD93C11 13 /* command byte 1 */
#define WD93C12 14 /* command byte 1 */
#define WD93LUN 15 /* target LUN */
#define WD93PHASE 16 /* command phase */
#define WD93SYNC 17 /* synchronous transfer */
#define WD93CNTHI 18 /* MSB transfer count */
#define WD93CNTMD 19 /* transfer count */
#define WD93CNTLO 20 /* LSB transfer count */
#define WD93DESTID 21 /* destination ID */
#define WD93SRCID 22 /* source ID */
#define WD93STAT 23 /* SCSI Status */
#define WD93CMD 24 /* command register */
#define WD93DATA 25 /* data register */
#define WD93QTAG 26 /* queue tag register (93B only) */
/* Timeout values. */
#if IP20 || IP22 || IP26 /* runs at 20 Mhz */
#define T93SATN 64 /* ~250 ms @ 4 ms per tick (for 20MHz) */
#define T93SATN_SHORT 8 /* ~30 ms during hinv and diags */
#define WD93FREQVAL 0x80 /* bit for chip frequency (ORed into 93ID) */
#else /* all others run at 10 MHz */
#define T93SATN 32 /* ~250 ms @ 8 ms per tick (for 10MHz) */
#define T93SATN_SHORT 4 /* ~30 ms during hinv and diags */
#define WD93FREQVAL 0 /* bit for chip frequency (ORed into 93ID) */
#endif /* IP20 || IP22 */
#define T93SRETRY 3 /* times to attempt selection; same as most
drives will do on re-selects. */
/* Chip commands. */
#define C93RESET 0x00 /* reset the bus and chip */
#define C93ABORT 0x01 /* abort current operation */
#define C93ATN 0x02 /* assert ATN on the bus */
#define C93NACK 0x03 /* negate ACK line */
#define C93DISC 0x04 /* disconnect from bus */
#define C93RESEL 0x05 /* reselect */
#define C93SELATN 0x06 /* select with ATN */
#define C93SELNATN 0x07 /* select with no ATN */
#define C93SELATNTR 0x08 /* select with ATN and transfer */
#define C93SELNATNTR 0x09 /* select without ATN and transfer */
#define C93RESELREC 0x0a /* reselect and receive */
#define C93RESELSND 0x0b /* reselect and send */
#define C93WSELREC 0x0c /* wait for select and receive */
#define C93SENDMSG 0x16 /* send message to target */
#define C93TRADDR 0x18 /* translate address */
#define C93TRINFO 0x20 /* transfer info */
#define C93TRPAD 0x21 /* transfer pad */
/* States of interest */
#define ST_RESET 0x00 /* Reset by command or power-up (MR-) */
#define ST_SELECT 0x11 /* Selection complete (after C93SELATN) */
#define ST_SATOK 0x16 /* Select-And-Transfer completed successfully */
#define ST_TR_DATAOUT 0x18 /* transfer cmd done, target requesting data */
#define ST_TR_DATAIN 0x19 /* transfer cmd done, target sending data */
#define ST_TR_STATIN 0x1b /* Target is sending status in */
#define ST_TR_MSGIN 0x1f /* transfer cmd done, target sending msg */
#define ST_TRANPAUSE 0x20 /* transfer cmd has paused with ACK */
#define ST_SAVEDP 0x21 /* Save Data Pointers message during SAT */
#define ST_A_RESELECT 0x27 /* reselected after disc (93A) */
#define ST_UNEXPDISC 0x41 /* An unexpected disconnect */
#define ST_PARITY 0x43 /* cmd terminated due to parity error */
#define ST_PARITY_ATN 0x44 /* cmd terminated due to parity error
(ATN is asserted) */
#define ST_TIMEOUT 0x42 /* Time-out during Select or Reselect */
#define ST_INCORR_DATA 0x47 /* incorrect message or status byte */
#define ST_UNEX_RDATA 0x48 /* Unexpected receive data phase */
#define ST_UNEX_SDATA 0x49 /* Unexpected send data phase */
#define ST_UNEX_CMDPH 0x4a /* Unexpected cmd phase */
#define ST_UNEX_SSTATUS 0x4b /* Unexpected send status phase */
#define ST_UNEX_RMESGOUT 0x4e /* Unexpected request msg out phase */
#define ST_UNEX_SMESGIN 0x4f /* Unexpected send message in phase */
#define ST_RESELECT 0x80 /* WD33C93 has been reselected */
#define ST_93A_RESEL 0x81 /* reselected while idle (93A) */
#define ST_DISCONNECT 0x85 /* Disconnect has occurred */
#define ST_NEEDCMD 0x8a /* Target is ready for a cmd */
#define ST_REQ_SMESGOUT 0x8e /* REQ signal for send message out */
#define ST_REQ_SMESGIN 0x8f /* REQ signal for send message in */
/* Phases during a Select and Transfer command */
#define PH_NOSELECT 0x00 /* Selection not successful */
#define PH_SELECT 0x10 /* Selection successful */
#define PH_IDENTSEND 0x20 /* Identify message sent */
/* phase 30 indicates none of the cmd bytes have yet been sent; every
* cmd byte sent increments that by one. */
#define PH_CDB_START 0x30 /* Start of CDC transfers */
#define PH_CDB_6 0x36 /* 6th cmd byte sent */
#define PH_CDB_10 0x3a /* 0xAth cmd byte sent */
#define PH_CDB_12 0x3c /* 0xCth cmd byte sent */
#define PH_SAVEDP 0x41 /* Save data pointers */
#define PH_DISCRECV 0x42 /* Disconnect message received */
#define PH_DISCONNECT 0x43 /* Target disconnected */
#define PH_RESELECT 0x44 /* Original target reselected */
#define PH_IDENTRECV 0x45 /* Correct identify (right LUN) message rcv'd */
#define PH_DATA 0x46 /* Data transfer completed */
#define PH_STATUSRECV 0x50 /* Status byte received */
#define PH_COMPLETE 0x60 /* Command complete message received */
/* Auxiliary status register bits */
#define AUX_INT 0x80 /* interrupt pending */
#define AUX_LCI 0x40 /* last command ignored */
#define AUX_BSY 0x20 /* busy -- level II command being performed */
#define AUX_CIP 0x10 /* command in progress */
#define AUX_FFE 0x04 /* WD FIFO full/empty (93B only) */
#define AUX_PE 0x02 /* parity error */
#define AUX_DBR 0x01 /* data buffer ready */
stand/arcs/include/sys/scsimsgs.h
+39
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#ifndef __SYS_SCSIMSGS_H__
#define __SYS_SCSIMSGS_H__
/**************************************************************************
* *
* Copyright (C) 1990, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
#ident "$Revision: 1.1 $"
/*
* scsimsgs.h
*
* This file fixes some of the broken defines in scsi.h and
* newscsi.h
*
* The defines SC_NUMSENSE and SC_NUMADDSENSE are in scsi.h but they
* are overridden by new values in newscsi.h. These arrays are
* defined in controller specific files like ql.c, wd95.c which
* use values in newscsi.h. Including newscsi.h in dksc.c may cause other
* problems. So only these controller file dependent information
* is changed. If any of these change in newscsi.h it should
* be reflected in include/sys/scsimsgs.h
*/
#ifdef SN0 /* || IP30 */
#undef SC_NUMSENSE
#undef SC_NUMADDSENSE
#define SC_NUMSENSE 0x10 /* # of messages in scsi_key_msgtab */
#define SC_NUMADDSENSE 0x4a /* # of messages in scsi_addit_msgtab */
#endif
#endif /* !__SYS_SCSI_H__ */
stand/arcs/include/sys/skpick.h
+73
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/* skpick.h: Allows users of the kernel standalone library to pick-n-choose
* which device drivers and file systems they get linked with by
* stubbing out the externally used routines. This is only needed
* for modules that export more than their install routine.
*
* To use, #define the drivers and filesystems you wish to exclude
* in a C file, and then include this file. It will make
* a stubs to keep the requested drivers from getting linked in.
*
* NOTE: This is usually done automatically by gconf when using
* the node! syntax.
*/
#ifndef __SYS_SKPICK__
#define __SYS_SKPICK__
#ident "$Revision: 1.16 $"
#include <arcs/errno.h>
#define XLEAF(name) int name() {return(0);}
#define XLEAFER(name) int name() {return(ENXIO);}
/* drivers */
#ifdef NO_mgras
XLEAF(pon_graphics)
#endif
#ifdef NO_scsi /* implies NO_dksc and NO_tpsc */
int scsieditintdone;
unsigned char scsi_ha_id[2];
XLEAF(scsiunit_init)
#endif
#if defined(NO_tpsc) && !defined(NO_scsi)
XLEAF(tpsc_strat)
XLEAF(tpsctapetype)
XLEAF(tpsc_tapeid)
XLEAF(_tpscopen)
XLEAF(_tpscclose)
#endif
#if defined(NO_dksc) && !defined(NO_scsi)
XLEAF(dksc_strat)
#endif
#ifdef NO_sgikbd
XLEAFER(config_keyboard) /* called from duart */
XLEAF(kb_translate)
XLEAF(bell)
#endif
#ifdef NO_ms
XLEAFER(ms_config) /* all called from duart */
XLEAF(ms_install)
XLEAF(ms_input)
XLEAF(_mspoll)
XLEAF(_init_mouse)
#endif
#ifdef NO_pcms
XLEAF(_mspoll)
XLEAF(_init_mouse)
#endif
/* file systems */
#if defined(NO_dvh) && !defined(NO_scsi)
XLEAF(vh_checksum)
XLEAF(is_vh)
#endif
#endif /*__SYS_SKPICK__ */
stand/arcs/include/sys/slot_drvr.h
+123
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/**************************************************************************
* *
* Copyright (C) 1996, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
#ifndef __SLOT_DRVR_H__
#define __SLOT_DRVR_H__
/*
* SLOTCONFIG provides card/slot id based matching in standalone, integrated
* with the older driver install based probing methods. Bus providers call
* slot_register() to register a slot and the config code will match this
* against the data provided by standcfg.
*
* This code is an slightly better integrated version of Greg Limes'
* slot_drvr, which is derived from the original pci_intf.
*
* .cf ORDERING: Some of this code requires the .cf file to give the
* propper driver parent dependancies.
*
* CALL ORDERING: If multiple drivers are interested in a device, the
* various drivers' install routines will be called with that device
* in the order in which the drivers are in the .cf file.
*/
typedef struct slotdrvr_id_s slotdrvr_id_t;
typedef struct slotinfo_s slotinfo_t;
typedef struct drvrinfo_s drvrinfo_t;
/*
* slot_register: register a device found.
*/
void slot_register(struct component *,slotinfo_t *);
/*
* slotdrvr_id: common substructure representing the information that
* we might acqiure from a device in a bus-dependent but
* device-independent manner, plus a notation of what kind of bus we
* acquired the data from. In order for a driver and a device to
* rendevous, all fields must "match" (where match means that the
* values are the same, or the driver used an _ANY wildcard, or in the
* case of "rev" the device's value must be greater than or equal to the
* driver's value).
*/
struct slotdrvr_id_s {
unsigned int bus;
unsigned int mfgr;
unsigned int part;
unsigned int rev;
};
/*
* slotinfo_t: information provided by the bus scanner.
*
* Must include enough ID to limit the set of drivers that might be
* interested in looking at these devices; should include the base
* address of any "configuration" space (mostly for PCI) and an
* address (and size) representing the virtual addresses that will get
* to the actual device. Additionally a COMPONENT pointer is made
* available so the device driver can correctly position the resulting
* AddChild within the COMPONENT tree.
*
* bus_base is a pointer to the regsiters for the bus controller,
* useful when a device needs to do something to its controller (like
* a PCI device whacking a Bridge Device(n) regster). bus_slot is the
* logical slot number or id number; on XTalk this is the XTalk ID,
* and on PCI this is the slot number.
*/
struct slotinfo_s {
slotdrvr_id_t id;
struct component *parent;
volatile void *cfg_base;
volatile void *mem_base;
void *bus_base;
int bus_slot;
int drvr_index;
};
/*
* drvrinfo_t: information provided by the device driver.
*
* The ID word is used to filter which devices are actually presented
* to the install routine; in proper environments (PCI, Crosstalk)
* this generally filters out all but the specific device that the
* driver is interested in. The "name" field is optional but suggested
* for debuggability.
*
* It is reasonable for a driver to register itself multiple times,
* using different drvrinfo structures. When using this to cause
* different rendevous routines to be used for different revisions of
* the card, it is suggested that the registrations be done in
* decreasing revision number order.
*/
struct drvrinfo_s {
slotdrvr_id_t *id; /* null terminated array of ids */
char *name;
};
#define BUS_NONE (0) /* terminator */
#define BUS_ANY (1)
#define BUS_GIO (2)
#define BUS_IOC3 (3)
#define BUS_XTALK (4)
#define BUS_PCI (5)
/*
* Wildcards. Using "all bits set" makes it least likely
* that we will collide on a valid value.
*
* NB: PCI "invalid vendor" is 0xFFFF so we have precedent.
*/
#define MFGR_ANY (0xFFFFFFFFu)
#define PART_ANY (0xFFFFFFFFu)
#define REV_ANY (0)
#endif /* __SLOT_DRVR_H__ */
stand/arcs/include/sys/tpsc.h
+792
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/**************************************************************************
* *
* Copyright (C) 1986, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
#ifndef _SYS_TPSC_H_
#define _SYS_TPSC_H_
#ident "sys/tpsc.h: $Revision: 3.49 $"
/* This files contains the definitions and data structures specific to
* the SCSI tape drives (currently 1/4 inch cartridge, 8mm videotape,
* 9 track reel, DAT tape).
*/
/* Layout of the INQUIRY data */
/* max inquiry info we accept */
#define MAX_INQUIRY_DATA (sizeof (ct_g0inq_data_t))
#define INQ_PDT_CT 0x01 /* peripheral device type, for tape */
#define MAX_INQ_VID 8 /* # bytes for vendor ID */
#define MAX_INQ_PID 16 /* # bytes for product ID */
#define MAX_INQ_PRL 8 /* # bytes for product revision level */
/* NOTE: you can't enlarge this structure for drives that return more
* data without breaking old binaries since some of their data would
* be overwritten by an MTSCSIINQ ioctl. This structure is used in
* both user programs and in the driver. */
typedef struct ct_g0inq_data_s {
#ifdef _MIPSEB
u_char id_pqt: 3, /* peripheral qual type */
id_pdt: 5; /* peripheral device type */
u_char id_rmb: 1, /* removable media bit */
id_dtq: 7; /* device type qualifier */
u_char id_iso: 2, /* ISO version */
id_ecma: 3, /* ECMA version */
id_ansi: 3; /* ANSI version */
u_char id_aenc: 1, /* supports async event notification */
id_termiop: 1, /* supports termiop msg */
id_rsv0: 2, /* reserved */
id_respfmt: 4; /* response format */
#else /* _MIPSEL */
u_char id_pdt: 5, /* peripheral device type */
id_pqt: 3; /* peripheral qual type */
u_char id_dtq: 7, /* device type qualifier */
id_rmb: 1; /* removable media bit */
u_char id_ansi: 3, /* ANSI version */
id_ecma: 3, /* ECMA version */
id_iso: 2; /* ISO version */
u_char id_respfmt: 4, /* response format */
id_rsv0: 2, /* reserved */
id_termiop: 1, /* supports termiop msg */
id_aenc: 1; /* supports async event notification */
#endif /* _MIPSEL */
u_char id_ailen; /* additional inquiry length */
u_char id_rsv1; /* reserved */
u_char id_rsv2; /* reserved */
/* next 8 bits valid only if id_respfmt 2 (scsi2) */
#ifdef _MIPSEB
u_char id_reladr: 1, /* supports relative addressing */
id_wide32: 1, /* supports 32 bit wide bus */
id_wide16: 1, /* supports 16 bit wide bus */
id_sync: 1, /* supports sync */
id_linked: 1, /* supports linked cmds */
id_rsv3: 1, /* reserved */
id_cmdq: 1, /* supports command queing */
id_softre: 1; /* supports soft reset */
#else /* _MIPSEL */
u_char id_softre: 1, /* supports soft reset */
id_cmdq: 1, /* supports command queing */
id_rsv3: 1, /* reserved */
id_linked: 1, /* supports linked cmds */
id_sync: 1, /* supports sync */
id_wide16: 1, /* supports 16 bit wide bus */
id_wide32: 1, /* supports 32 bit wide bus */
id_reladr: 1; /* supports relative addressing */
#endif /* _MIPSEL */
u_char id_vid[ MAX_INQ_VID ]; /* vendor ID */
u_char id_pid[ MAX_INQ_PID ]; /* product ID */
u_char id_prl[ MAX_INQ_PRL ]; /* product revision level*/
} ct_g0inq_data_t;
#ifdef _KERNEL
/*
** Layout of the various areas that receive/xmit info.
**
** Layout of the EXTENDED SENSE data
*/
#define MAX_SENSE_DATA (sizeof (ct_g0es_data_t)) /* max sense info */
struct exab_as { /* Exabyte add sense data */
u_char rs0[4]; /* reserved */
u_char as; /* add sense */
u_char aq; /* add sense qualifier */
u_char rs1[2]; /* reserved */
u_char errs[3]; /* recovered errs */
#ifdef _MIPSEB
u_char pf: 1, /* power fail/reset */
bpe: 1, /* bus parity error */
fpe: 1, /* buffer parity error */
me: 1, /* media error (uncorrectable) */
eco: 1, /* error counter (exerrs) overflow */
tme: 1, /* tape motion error */
tnp: 1, /* no tape in drive */
bot: 1; /* at BOT */
u_char xfr: 1, /* disconnect error (while trying to pause transfer) */
tmd: 1, /* error occured during SPACE */
wp: 1, /* write protected */
fmke: 1, /* error while writing FM */
ure: 1, /* data flow underrun from media error */
we1: 1, /* too many retries on write; media error */
sse: 1, /* hardware failure in servo system */
fe: 1; /* hardware failure in data formatter */
u_char rs2: 6, /* reserved */
wseb: 1, /* write splice error, blank tape (hardware) */
wse0: 1; /* write splice error, overshoot (hardware) */
#else /* _MIPSEL */
u_char bot: 1, /* at BOT */
tnp: 1, /* no tape in drive */
tme: 1, /* tape motion error */
eco: 1, /* error counter (exerrs) overflow */
me: 1, /* media error (uncorrectable) */
fpe: 1, /* buffer parity error */
bpe: 1, /* bus parity error */
pf: 1; /* power fail/reset */
u_char fe: 1, /* hardware failure in data formatter */
sse: 1, /* hardware failure in servo system */
we1: 1, /* too many retries on write; media error */
ure: 1, /* data flow underrun from media error */
fmke: 1, /* error while writing FM */
wp: 1, /* write protected */
tmd: 1, /* error occured during SPACE */
xfr: 1; /* disconnect error (while trying to pause transfer) */
u_char wse0: 1, /* write splice error, overshoot (hardware) */
wseb: 1, /* write splice error, blank tape (hardware) */
rs2: 6; /* reserved */
#endif /* _MIPSEL */
u_char rs3; /* reserved */
u_char left[3]; /* remaining tape in 1K blocks to LEOT */
};
struct ciph_as { /* Cipher add sense data */
u_char as; /* add sense */
u_char errs[2]; /* recovered errs */
};
struct viper_as { /* Viper add sense data */
u_char copysrc; /* copy source sense data pointer */
u_char copydst; /* copy destination sense data pointer */
u_char rs0[2]; /* reserved */
u_char errs[2]; /* recovered errs */
u_char copyst; /* copy target status*/
u_char copysns[8]; /* copy target sense data */
};
struct tand_as { /* Tandberg 36[246]0 add sense data */
u_char copysrc; /* copy source sense data pointer */
u_char copydst; /* copy destination sense data pointer */
u_char rs0[2]; /* reserved */
u_char errs[2]; /* recovered errs */
#ifdef _MIPSEB
u_char ercl: 4, ercd: 4; /* err class, and code */
#else /* _MIPSEL */
u_char ercd: 4, ercl: 4; /* err class, and code */
#endif /* _MIPSEL */
u_char exercd; /* extended error code */
u_char blkctr[3]; /* i/o blk cnt since open or space */
u_char fmctr[2]; /* FM cnt since open or space */
u_char underrun[2]; /* underrun cnt since open or space */
u_char margblk; /* marginal blks cnt since open or space */
u_char blksbuf; /* blocks unwritten in buffer after err */
/* up to 20 copy sense bytes follow, but we don't implement COPY */
};
struct kenn_as { /* Kennedy add sense data */
u_char rs0[4]; /* reserved */
u_char as; /* add sense */
u_char aq; /* add sense qualifier */
u_char rs1[2]; /* reserved */
};
struct scsi2_as { /* DAT and other drives in scsi2 mode */
u_char cmdspecific[4]; /* cmd specific; usually used only
for COPY cmd */
u_char as; /* add sense */
u_char aq; /* add sense qualifier */
u_char fru; /* field replaceable unit code (0 non-specific) */
#ifdef _MIPSEB
u_char sksv: 1, /* sense key specific valid */
cd: 1, /* err in cmd if set, otherwise in data out */
rsv: 2, /* reserved */
bpv: 1, /* if 1, bitptr is valid */
bitp: 3; /* if 1, bitptr is valid */
#else /* _MIPSEL */
u_char bitp: 3, /* if 1, bitptr is valid */
bpv: 1, /* if 1, bitptr is valid */
rsv: 2, /* reserved */
cd: 1, /* err in cmd if set, otherwise in data out */
sksv: 1; /* sense key specific valid */
#endif /* _MIPSEL */
u_char sensespecific[2]; /* if sksv, cmd/err specific */
};
typedef struct
{
#ifdef _MIPSEB
u_char esd_valid: 1, /* valid bit */
esd_errclass: 3, /* error class */
esd_mbz0: 3, /* must be zero */
esd_defer: 1; /* deferred err from prev cmd */
u_char esd_copyseg; /* seg from COPY cmd*/
u_char esd_fm: 1, /* file mark */
esd_eom: 1, /* logical EOM (CT_EW) */
esd_ili: 1, /* illegal length indicator */
esd_reserve: 1, /* unused for now */
esd_sensekey: 4; /* sense key */
#else /* _MIPSEL */
u_char esd_defer: 1, /* deferred err from prev cmd */
esd_mbz0: 3, /* must be zero */
esd_errclass: 3, /* error class */
esd_valid: 1; /* valid bit */
u_char esd_copyseg; /* seg from COPY cmd*/
u_char esd_sensekey: 4, /* sense key */
esd_reserve: 1, /* unused for now */
esd_ili: 1, /* illegal length indicator */
esd_eom: 1, /* logical EOM (CT_EW) */
esd_fm: 1; /* file mark */
#endif /* _MIPSEL */
u_char esd_resid[4]; /* residual length */
u_char esd_aslen; /* additional sense length */
union {
struct exab_as _exab; /* Exabyte */
struct ciph_as _ciph; /* Cipher 540 */
struct tand_as _tand; /* Tandberg 36[246]0 */
struct viper_as _viper; /* Viper 150,60 */
struct kenn_as _kenn; /* Kennedy 96X2 */
struct scsi2_as _rsscsi2; /* SCSI 2 DAT, etc. */
} asd;
} ct_g0es_data_t;
#define exab asd._exab
#define ciph asd._ciph
#define tand asd._tand
#define viper asd._viper
#define kenn asd._kenn
#define rsscsi2 asd._rsscsi2
/*
** Layout of the INQUIRY data
*/
/* used to set tape type from the inquiry cmd and info from master.d/tpsc.
This allows SGI and users to add new tape drives of known types without
re-compiling the driver. The assumption is that the SCSI commands,
block size, capablities, and request sense info are constant within
a type. This is rarely completely true, but is often close enough
to allow a drive to work.
*/
struct tpsc_types {
u_char tp_type; /* a type from the tape types below, used for
some capability, and some error code decoding */
u_char tp_hinv; /* a type from the TP* tape types in invent.h;
is returned by the MTCAPABILITY ioctl */
u_char tp_vlen; /* length of vendor string */
u_char tp_plen; /* length of product string */
u_char tp_vendor[MAX_INQ_VID]; /* vendor ID */
u_char tp_product[MAX_INQ_PID]; /* product ID */
u_char tp_msl_pglen; /* # of extra bytes transferred on modeselect
(does not include MSD_IND_SIZE). page 0 is only page done
currently, except for the partition stuff for DAT, which
follows SCSI 2 and so should not require any changes. */
u_char *tp_msl_data; /* values to ALWAYS put in msld_vend when
doing a mode select; ptr should be null if tp_msl_pglen is 0 */
u_char tp_density[4]; /* values for 4 possible densities; used
only when MTCAN_SETDEN is true; indexed by DENSITY_DEV() */
ulong tp_capablity; /* capablities supported */
ulong tp_xfr_divisor; /* transfer timeout; see XFER_TIMEO
(units are inverse ticks) */
ulong tp_mintimeo; /* minimum timeout for any cmd; see
XFER_TIMEO and SHORT_TIMEO (units are seconds) */
ulong tp_spacetimeo; /* space cmd timeout; (units are in seconds),
see SPACE_TIMEO() */
ulong tp_rewtimeo; /* timeout for very long operations, like
rewind, retension, erase; (units are in seconds);
time is doubled for retension. */
ulong tp_dfltblksz; /* default (and often only) block size in
fixed block mode */
ulong tp_recblksz; /* recommended blocking factor, used only for
MTIOCGETBLKINFO ioctl; note that it is given in bytes,
not as a multipier for the blocksize. */
};
/*
** Layout of the MODE SELECT Parameter List
*/
/* maximum amount of mode select info we send */
#define MAX_MODE_SEL_DATA (sizeof (ct_g0msl_data_t))
#define MSD_IND_SIZE 12 /* # bytes in vendor independent mode select (no
page data, just header and block descr) */
#define MSLD_BDLEN 0x08 /* block descriptor cnt */
#define MSLD_BLKCNT_SZ 3 /* number of blocks */
#define MSLD_BLKLEN_SZ 3 /* length of a block */
#define MS_VEND_LEN 0x10 /* DAT is now largest */
typedef struct
{
/* 4 byte header */
u_char msld_mbz0; /* reserved, must be 0 */
u_char msld_mbz1; /* reserved, must be 0 */
#ifdef _MIPSEB
u_char msld_mbz2: 3, /* reserved, must be 0 */
msld_bfm: 1, /* buffered/unbuffered mode */
msld_speed: 4; /* speed */
#else /* _MIPSEL */
u_char msld_speed: 4, /* speed */
msld_bfm: 1, /* buffered/unbuffered mode */
msld_mbz2: 3; /* reserved, must be 0 */
#endif /* _MIPSEL */
u_char msld_bdlen; /* block descriptor length */
/* 8 byte block descr if bdlen is non-zero */
u_char msld_descode; /* density code */
u_char msld_blkcnt[ MSLD_BLKCNT_SZ ]; /* number of blocks */
u_char msld_mbz3; /* reserved, must be 0 */
u_char msld_blklen[ MSLD_BLKLEN_SZ ]; /* block size */
/* page data */
u_char msld_vend[ MS_VEND_LEN ];
} ct_g0msl_data_t;
/*
** Layout of the MODE SENSE Data
*/
/* maximum amount of mode sense info we accept */
#define MAX_MODE_SENS_DATA (sizeof (ct_g0ms_data_t))
#define MSD_BDLEN 0x08 /* block descriptor length */
#define MSD_BLKCNT_SZ 3 /* number of blocks */
#define MSD_BLKLEN_SZ 3 /* length of a block */
typedef struct
{
/* 4 byte header */
u_char msd_len; /* sense data length */
u_char msd_mtype; /* medium type (0?) */
#ifdef _MIPSEB
u_char msd_wrp: 1, /* write protect */
msd_bfm: 3, /* buffered/nonbuffered mode */
msd_speed: 4; /* speed */
#else /* _MIPSEL */
u_char msd_speed: 4, /* speed */
msd_bfm: 3, /* buffered/nonbuffered mode */
msd_wrp: 1; /* write protect */
#endif /* _MIPSEL */
u_char msd_bdlen; /* block descriptor length */
/* 8 byte block descr if bdlen non-zero */
u_char msd_descode; /* density code */
u_char msd_blkcnt[ MSD_BLKCNT_SZ ]; /* number of blocks */
u_char msd_mbz0; /* reserved, must be 0 */
u_char msd_blklen[ MSD_BLKLEN_SZ ]; /* block size */
/* page data */
u_char msd_vend[MS_VEND_LEN];
} ct_g0ms_data_t;
/*
** Command Descriptor Block for Group 0 commands.
*/
typedef struct
{
u_char g0_opcode; /* group code/command code */
#ifdef _MIPSEB
u_char g0_lu: 3, /* logical unit number */
g0_cmd0: 5; /* command dependent 0 */
#else /* _MIPSEL */
u_char g0_cmd0: 5, /* command dependent 0 */
g0_lu: 3; /* logical unit number */
#endif /* _MIPSEL */
u_char g0_cmd1; /* command dependent 1 */
u_char g0_cmd2; /* command dependent 2 */
u_char g0_cmd3; /* command dependent 3 */
#ifdef _MIPSEB
u_char g0_vu67: 2, /* vendor unique bits 6 and 7 */
g0_mbz0: 4, /* must be zero */
g0_flag: 1, /* flag */
g0_link: 1; /* link */
#else /* _MIPSEL */
u_char g0_link: 1, /* link */
g0_flag: 1, /* flag */
g0_mbz0: 4, /* must be zero */
g0_vu67: 2; /* vendor unique bits 6 and 7 */
#endif /* _MIPSEL */
} ct_g0cdb_t;
/*
** Command Descriptor Block for Group 2 commands.
*/
typedef struct
{
u_char g2_opcode; /* group code/command code */
#ifdef _MIPSEB
u_char g2_lu: 3, /* logical unit number */
g2_cmd0: 5; /* command dependent 0 */
#else /* _MIPSEL */
u_char g2_cmd0: 5, /* command dependent 0 */
g2_lu: 3; /* logical unit number */
#endif /* _MIPSEL */
u_char g2_cmd1; /* command dependent 1 */
u_char g2_cmd2; /* command dependent 2 */
u_char g2_cmd3; /* command dependent 3 */
u_char g2_cmd4; /* command dependent 4 */
u_char g2_cmd5; /* command dependent 5 */
u_char g2_cmd6; /* command dependent 6 */
u_char g2_cmd7; /* command dependent 7 */
#ifdef _MIPSEB
u_char g2_vu67: 2, /* vendor unique bits 6 and 7 */
g2_mbz0: 4, /* must be zero */
g2_flag: 1, /* flag */
g2_link: 1; /* link */
#else /* _MIPSEL */
u_char g2_link: 1, /* link */
g2_flag: 1, /* flag */
g2_mbz0: 4, /* must be zero */
g2_vu67: 2; /* vendor unique bits 6 and 7 */
#endif /* _MIPSEL */
} ct_g2cdb_t;
/*
** Opcodes for Group 0 commands. These opcodes are composed of the
** group code and opcode.
*/
#define TST_UNIT_RDY_CMD 0x00
#define REWIND_CMD 0x01
#define REQ_BLKADDR 0x02
#define REQ_SENSE_CMD 0x03
#define REQ_BLKLIM_CMD 0x05
#define READ_CMD 0x08
#define WRITE_CMD 0x0a
#define SEEKBLK_CMD 0x0c
#define WFM_CMD 0x10
#define SPACE_CMD 0x11
#define INQUIRY_CMD 0x12
#define MODE_SEL_CMD 0x15
#define RESERV_UNIT_CMD 0x16
#define REL_UNIT_CMD 0x17
#define ERASE_CMD 0x19
#define MODE_SENS_CMD 0x1a
#define L_UL_CMD 0x1b
#define PREV_MED_REMOV_CMD 0x1e /* not on Kennedy */
#define LOCATEBLK_CMD 0x2b
#define READ_POS_CMD 0x34 /* SCSI 2 (DAT) read position */
#define LOG_SELECT_CMD 0x4C /* SCSI 2 (DAT) set logging params */
#define LOG_SENSE_CMD 0x4D /* SCSI 2 (DAT) get logged info */
/*
** LED controll subfunctions
*/
#define CT_PREV_REMOV 0x01
#define CT_ALLOW_REMOV 0x00
/*
** Space sub-function codes
*/
#define SPACE_BLKS_CODE 0 /* space blocks code */
#define SPACE_FM_CODE 1 /* space filemarks code */
#define SPACE_SFM_CODE 2 /* space sequential filemarks code */
#define SPACE_EOM_CODE 3 /* space to end of recorded media code */
#define SPACE_SETM_CODE 4 /* space setmarks code */
/*
** Load sub-function bits.
*/
#define L_UL_RETENSION 0x02 /* bit to set in the load/unload CDB to do a */
/* retention */
#define L_UL_LOAD 0x01 /* bit to set if you want a load operation */
/*
**
** This structure contains the info for each logical unit.
** The arrangement of this structure is such that a hex dump is
** elatively easy to interpret, and minimize gaps.
** sub structures must follow a long or ptr, OR have a
** long or ptr as first member OR be part of union that has
** a long if they will be used for DMA, since compiler won't
** force quad alignment otherwise. (marked with DMA in comments)
*/
typedef struct
{
union {
ct_g0cdb_t g0cdb; /* group 0 command descriptor block (DMA) */
ct_g2cdb_t g2cdb; /* group 2 command descriptor block (DMA) */
} ct_cmd;
u_char ct_lastcmd; /* last command issued, except request sense */
u_char ct_openflags; /* flags from current open call */
u_char ct_partnum; /* for partitioned tapes, which partition. */
u_char ct_scsiv; /* scsi1 or scsi2, from inq */
u_char ct_cansync; /* set if scsiv >=2 and id_sync set */
dev_t ct_lastdev; /* dev on last open; for density/mode changes */
uint ct_sili: 1, /* suppress illegal length error (MTCAN_SILI) */
ct_cipherrec: 1, /* cipher 540 report recovered errors */
ct_speed: 1, /* high or low speed if MTCAN_SETSP */
ct_density: 8; /* density value for modesel if MTCAN_SETDEN */
scsisubchan_t *ct_subchan; /* pointer to allocated subchan */
struct tpsc_types ct_typ; /* a copy of the tpsc_type struct, not
a pointer, because extra code to de-reference really adds up */
buf_t *ct_bp; /* pointer to allocated buf_t */
buf_t *ct_reqbp; /* buf_t * for reqsense */
ulong ct_state; /* state of the device */
ulong ct_tent_state; /* state of the device; set while performing
* immediate mode commands such as rew, unload, etc. When they
* complete successfully (drive no longer reports BUSY status;
* no abort command issued, etc.), then ct_tent_state is OR'ed
* into state and cleared. */
ulong ct_recov_err; /* # recoverable errors */
ulong ct_blksz; /* current blksz in bytes for fixed mode */
ulong ct_fixblksz; /* blksz in bytes for fixed mode, set only
on first open (from dfltblksz), and by SETFIXED ioctl.
Used when switching between variable and fixed modes */
ulong ct_cur_minsz; /* min size block drive supports, may be diff
than blkinfo value */
ulong ct_cur_maxsz; /* max size block drive supports, may be diff
than blkinfo value */
ulong ct_readcnt; /* reads on this open (not bytes) */
ulong ct_writecnt; /* writes on this open (not bytes) */
ulong ct_extrabusy; /* extra 'delay' because an imm rewind in prog */
ct_g0es_data_t ct_es_data; /* extended sense info */
union ct_bufarea { /* info that isn't needed across commands */
int resid; /* for ctgetblklen */
ct_g0inq_data_t inq_data; /* inquiry data */
ct_g0msl_data_t msl; /* mode select */
ct_g0ms_data_t ms; /* mode sense */
u_char posninfo[20]; /* tmp read buffer for READPOSN */
u_char blklenbuf[4]; /* tmp read buffer for GETBLKLEN */
u_char reqblkinfo[6]; /* get block limits */
} *ct_bufarea;
struct mtblkinfo blkinfo; /* from mtio.h */
} sa_ct_target_t;
typedef sa_ct_target_t ctinfo_t; /* keep old name for back compat,
but use shorter and more descriptive name */
#define ct_g0cdb ct_cmd.g0cdb
#define ct_g2cdb ct_cmd.g2cdb
#define ct_resid ct_bufarea->resid
#define ct_inq_data ct_bufarea->inq_data
#define ct_msl ct_bufarea->msl
#define ct_ms ct_bufarea->ms
#define ct_blklenbuf ct_bufarea->blklenbuf
#define ct_posninfo ct_bufarea->posninfo
#define ct_reqblkinfo ct_bufarea->reqblkinfo
/*
** Masks for the various bits of the minor device number
*/
#define SCSIID_MSK 0x07 /* mask for SCSI ID of target */
#define HAID_MSK 0x08 /* mask for Host adaptor number */
#define REWIND_MSK 0x10 /* mask for rewind/norewind bit */
#define SWAP_MSK 0x20 /* mask for swap/noswap bit */
#define VAR_MSK 0x40 /* mask for fixed/variable bit */
#define DRIVE_MSK (3<<3) /* mask for drive specific bits, (in
'real' minor #, not internal form); currently used only for
density. */
#define CT_LUNIT 0 /* only lun 0 supported */
/*
** Shift values to convert various bits in the minor device to a number
*/
#define HAID_SHIFT 3
/*
** Macros for convience sake (use tpsc internal version of minor #)
*/
#define SCSIID_DEV(dev) ((dev) & SCSIID_MSK)
/* rewind devices rewind on close ONLY, unless media changed,
* in which case they rewind on next open also */
#define ISTPSCREWIND_DEV(dev) (((dev) & REWIND_MSK ) == 0)
#define ISSWAP_DEV(dev) ((dev) & SWAP_MSK)
#define ISVAR_DEV(dev) (((dev) & VAR_MSK) && (ctinfo->ct_typ.tp_capablity&MTCAN_VAR))
#define DENSITY_DEV(dev) (((dev) & DRIVE_MSK)>>3) /* if MTCAN_SETDEN */
/*
** Stuff to map a host adaptor logical number to the SCSI ID.
*/
#define HA_SCSI_ID 0
/*
** Flag value passed by ctcmd() to the specific function routine
*/
#define CTCMD_SETUP 0 /* setup to issue cdb */
#define CTCMD_ERROR 1 /* error */
#define CTCMD_NO_ERROR 2 /* no error */
/* The transfer timeout needs to be proportional to the amount of i/o
being done. This is fairly easy for the fixed block devices.
For variable mode, one also needs to take into account the
size of the i/o, but since the max i/o size is much smaller,
this really isn't much of a problem. Loading and rewinding
tapes is more problematical, since we may not know where we
are. Exabyte tapes take a max of 2:15 sec, plus possible load
time of ~15 seconds. On Kennedy, rewind of 2400' tape is
aprox 4 minutes. Space commands are straight forward for
space block, but space filemark is something else. On
Exabyte, space is ~10 times as fast as i/o, so max would
be 20 minutes, while on Kennedy, for a 2400 ft tape, it
would be ~4 minutes. See tp_xfr_divisor and tp_spacetimeo also.
All times should be a bit on the generous side; the xfer
timeout should allow for retries, possible start/stop time,
and for held off reads/writes like the Kennedy will do.
*/
/* rewind, retension, erase, and load/unload timeouts */
#define REWIND_TIMEO (ctinfo->ct_typ.tp_rewtimeo)
/* tpsc_min_delay is for cmds that don't do media i/o,
and min for any i/o. This long because if tape isn't moving
some devices take considerably longer than you would expect;
and we want to be conservative. lbootable so customers can
more easily add non-standard drives.
*/
#define XFER_TIMEO(cnt) max(cnt/ctinfo->ct_typ.tp_xfr_divisor, \
ctinfo->ct_typ.tp_mintimeo)
/* this is only for space FM, and space to EOM; space record uses
* XFER_TIMEO, partly because some QIC drives implement them
* (particularly back spacing) as read and check, which is
* very slow. */
#define SPACE_TIMEO ctinfo->ct_typ.tp_spacetimeo
/* delay time between retries when status BUSY is returned */
#define BUSY_INTERVAL (2*HZ)
#define SHORT_TIMEO ctinfo->ct_typ.tp_mintimeo
/* macros for determining drive type */
/*
* The CIPHER 540S drives have a couple of bothers:
* 1) they don't identify themselves through the INQUIRY command
* 2) by default, they report recoverable errors, however they
* do it incorrectly - if one for example is spacing forward
* and encounters a recoverable error, it issues a check-condition
* with the RECERR sense key - but the FILE MARK bit is NOT ON
* so we lose track of where we are.
* To get around this, we set the CIPHER specific SEC bit on
*/
#define IS_CIPHER(ctinfo) (ctinfo->ct_typ.tp_type == CIPHER540)
#define IS_TANDBERG(ctinfo) (ctinfo->ct_typ.tp_type == TANDBERG3660)
/*
* want to know if drive is a viper 150 because it can read 310 oersted
* tapes, but it can't write them.
*/
#define IS_VIPER150(ctinfo) (ctinfo->ct_typ.tp_type == VIPER150)
#define IS_VIPER60(ctinfo) (ctinfo->ct_typ.tp_type == VIPER60)
/* claimed to be 100% compatible with the 150, with some extra
* capablities (can do tape updates like 9 track), has variable
* block size. */
#define IS_DATTAPE(ctinfo) (ctinfo->ct_typ.tp_type == DATTAPE)
/*
** Exabyte uniquenesses:
** 1. does not support the RESERVE UNIT or RELEASE UNIT commands.
** 2. uses 1K blocks in fixed mode.
*/
#define IS_EXABYTE(ctinfo) ((ctinfo->ct_typ.tp_type == EXABYTE8200) || \
(ctinfo->ct_typ.tp_type == EXABYTE8500))
/* Kennedy 9 track drives */
#define IS_KENNEDY(ctinfo) (ctinfo->ct_typ.tp_type == KENNEDY96X2)
#endif /* _KERNEL */
/* The values for ct_typ.tp_type, not same as hinv types */
#define TPUNKNOWN 0 /* type not known */
#define CIPHER540 1 /* cipher QIC24 */
#define TANDBERG3660 2 /* TANDBERG 3660 QIC150 */
#define VIPER150 3 /* VIPER 150 QIC150 */
#define KENNEDY96X2 4 /* Kennedy 96[16]2 1/2" 9 track */
#define EXABYTE8200 5 /* Exabyte EXB-8200 8mm cartridge tape */
#define VIPER60 6 /* VIPER 60 QIC24 */
#define DATTAPE 7 /* Digital Audio Tape */
#define EXABYTE8500 8 /* Exabyte EXB-8500 8mm cartridge tape */
/* States for the logical unit (ct_state). states common with
mtio.h as much as possible. Note that for MTIOCGET, the position
bits get put in dposn, the low 16 bits in dsreg, and the upper 16
bits in erreg. These bits are all available to users now, so they
are no longer ifdef _KERNEL.
*/
#define CT_ONL MT_ONL /* drive is online */
#define CT_WRP MT_WPROT /* drive is write-protected */
#define CT_EOM MT_EOT /* drive is at end of media */
#define CT_BOT MT_BOT /* drive is at beginning of media */
#define CT_FM MT_FMK /* drive is at file mark */
#define CT_QIC24 MT_QIC24 /* tape is low density (310 oersted);
only set for Viper 150 drives */
#define CT_QIC120 MT_QIC120 /* tape is high density (550 oersted);
QIC120 15 tracks. */
#define CT_EOD MT_EOD /* at end of data, may also be EOT; sometimes,
in audio mode, we will set this (along with CT_AUD_MED) when
the drive is confused due to incorrect subcodes on the tape,
particularly at the leadin area. If both these bits are set
near BOT, then that is probably the problem. Both may legitimately
be set near EOD, particularly if audio was recorded on top of a
data tape, and doesn't extend past the end of the data portion.
See also CT_INCOMPAT_MEDIA for this case. */
/* beware the bits defined in mtio.h! */
#define CT_EW 0x08 /* hit early warning marker */
#define CT_GETBLKLEN 0x10 /* in the process of determining block
length of data on the tape */
#define CT_MOTION 0x20 /* a command has been performed that
(potentially) moves the tape since last tape change or reset */
#define CT_OPEN 0x200 /* device open */
#define CT_READ 0x400 /* opened for reading */
#define CT_WRITE 0x800 /* opened for writing */
#define CT_CHG 0x1000 /* unit attn occurred */
#define CT_DIDIO 0x2000 /* i/o has been successfully done on this open.
Used to handle case where first read after open hits a FM, in which
case we automatically skip over the FM. Driver no longer spaces
to a FM on first tape command after open, since that made mt [bf]sr
relatively worthless, with no way around it except writing a program
that does all the ioctls itself. This gets cleared on any of the
space, rewind, etc. commands. */
#define CT_NEEDBOT 0x10000 /* program needs to position at BOT
before doing any i/o. Set if opening Kennedy for diff
density/mode and not at BOT on open */
#define CT_LOADED 0x20000 /* The tape has been loaded, but is not
necessarily at BOT. */
#define CT_ANSI 0x40000 /* allow i/o after EOT marker for 9 track tapes.
This allows ANSI labels to be used. Works for QIC tapes also.
(see MTANSI in mtio.h) */
#define CT_SMK 0x80000 /* drive is at a setmark. Note that a skip
block or skip fm command will stop if a setmark is encountered. */
#define CT_AUDIO 0x100000 /* Drive is in audio mode; persists until
reset, tape change, or reboot */
#define CT_AUD_MED 0x200000 /* the media in the drive is in audio
format. Set if the drive tells us that we have audio media, or
when we are in audio mode and first write to the tape. Cleared
if we are not in audio mode, and we write to the tape. */
#define CT_MULTPART 0x400000 /* the media in the drive is a multi-
partition tape. Currently only DAT supports this */
#define CT_SEEKING 0x800000 /* a seek or rewind done with the
immediate bit set is still in progress; returned in the mt_erreg
field on MTIOCGET; never set in ct_state itself. Also set during
MTIOCGET if the drive is busy loading or unloading media.
This will currently happen only while in audio mode. */
#define CT_HITFMSHORT 0x1000000 /* in fixed blk mode, we hit a FM,
and returned a short count (not 0); the next read must return 0
(assuming no other intervening tape movement) so program knows a
FM has been reached. Can't happen in variable block mode */
#define CT_INCOMPAT_MEDIA 0x2000000 /* we have successfully read
data in audio mode with audio media, and have now gotten status
from the drive that tells us we have incompatible media. This
doesn't get set if we see incompat media near BOT, or if we aren't
in audio mode. It gets cleared on any tape motion command after it
was set. */
#ifdef _KERNEL
/* tape postion flags cleared on tape motion cmds and tape change */
#define CTPOS (CT_BOT|CT_EOM|CT_FM|CT_SMK|CT_EOD|CT_EW|CT_HITFMSHORT|\
CT_INCOMPAT_MEDIA)
/* states that persist across close/open. (if tape changes, etc.
some may be cleared at interrupt time) */
#define CTKEEP (CTPOS|CT_LOADED|CT_MOTION|CT_ONL|CT_QIC24|CT_QIC120|CT_WRP\
|CT_AUDIO|CT_MULTPART)
/* these states don't persist across a tape change */
#define CHGSTATES (CTKEEP|CT_NEEDBOT|CT_AUD_MED)
/* these states get cleared on a rewind, load, or a space BSF */
#define BACKSTATES (CT_DIDIO|CT_NEEDBOT|CTPOS)
#endif /* _KERNEL */
#endif /* _SYS_TPSC_H_ */
stand/arcs/include/sys/wd95a.h
+278
View File
@@ -0,0 +1,278 @@
/**************************************************************************
* *
* Copyright (C) 1992, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/*
* wd95a.h -- Western Digital 95a chip and associated data structures.
*/
#ident "$Revision: 1.1 $"
#ifndef _SYS_WD95A_
#define _SYS_WD95A_
/*
* register definitions - Setup Mode
*/
#define WD95A_S_CTL 0 /* control register */
#define WD95A_S_SCNF 2 /* scsi configuration */
#define WD95A_S_OWNID 4 /* Own ID register */
#define WD95A_S_TIMOUT 6 /* Sel & Resel timout period */
#define WD95A_S_SLEEP 8 /* Sleep Countdown register */
#define WD95A_S_TIMER 10 /* scsi timeout countdown residue */
#define WD95A_S_CDBSIZ1 12 /* Special CDB Size reg (grp 3,4) */
#define WD95A_S_CDBSIZ2 14 /* Special CDB Size reg (grp 6,7) */
#define WD95A_S_IDFLAG0 16 /* SCSI-ID specific flags (0..7) */
#define WD95A_S_IDFLAG1 18 /* SCSI-ID specific flags (8..15) */
#define WD95A_S_DMACNF 20 /* DMA Configuration */
#define WD95A_S_DMATIM 22 /* DMA Timing control */
#define WD95A_S_TEST0 24 /* Factory Test Register */
#define WD95A_S_SC0 26 /* SCSI Low-level control */
#define WD95A_S_SC1 28 /* SCSI Low-level control */
#define WD95A_S_SC2 30 /* SCSI Low-level control */
#define WD95A_S_SC3 32 /* SCSI Low-level control */
#define WD95A_S_CSADR 34 /* WCS Address Register */
#define WD95A_S_CSPRT0 36 /* WCS port for window 0 */
#define WD95A_S_CSPRT1 38 /* WCS port for window 1 */
#define WD95A_S_CSPRT2 40 /* WCS port for window 2 */
#define WD95A_S_CSPRT3 42 /* WCS port for window 3 */
#define WD95A_S_SQSEL 44 /* WCS Sel reponse addr */
#define WD95A_S_SQRSL 46 /* WCS ReSel reponse addr */
#define WD95A_S_SQDMA 48 /* WCS Start addr for DMA req */
#define WD95A_S_DPRADD 50 /* DPR address Pointer */
#define WD95A_S_DPRTC 52 /* DPR Transfer Counter */
#define WD95A_S_PLR 54 /* Physical:Logical Block Ratio */
#define WD95A_S_PSIZE0 56 /* Physical Block Size */
#define WD95A_S_PSIZE1 58 /* Physical Block Size */
#define WD95A_S_PING 60 /* Mirroring Ping-pong value */
#define WD95A_S_CMPIX 62 /* Data Compare Index */
#define WD95A_S_CMPVAL 64 /* Data Compare Value Register */
#define WD95A_S_CMPMASK 66 /* Data Compare Mask Register */
#define WD95A_S_BBDL 68 /* Buffered BD[0..7] */
#define WD95A_S_BBDH 70 /* Buffered BD[8..15] */
#define WD95A_S_CVER 72 /* Chip/Design Version */
#define WD95A_S_TEST1 74 /* Factory Test Register */
#define WD95A_S_OFFSET 76 /* REQ/ACK offset counter */
/*
* register definitions - Normal Mode
*/
#define WD95A_N_CTL 0 /* Control Register */
#define WD95A_N_CTLA 2 /* Control Register, Auxiliary */
#define WD95A_N_ISR 4 /* Interrupt Status Register */
#define WD95A_N_STOPU 6 /* Unexpected Stop Status Register */
#define WD95A_N_UEI 8 /* Unexpected Event Intr Register */
#define WD95A_N_ISRM 10 /* ISR Mask Register */
#define WD95A_N_STOPUM 12 /* STOPU Mask Register */
#define WD95A_N_UEIM 14 /* UEI Mask Register */
#define WD95A_N_RESPONSE 16 /* Automatic Response Control */
#define WD95A_N_SQINT 18 /* WCS Sequencer Interrupt Addr */
#define WD95A_N_SQADR 20 /* Current addr WCS is executing */
#define WD95A_N_STC 22 /* SCSI Transfer Control Register */
#define WD95A_N_SPW 24 /* SCSI Pulse Width Control Reg */
#define WD95A_N_DESTID 26 /* Destination ID Register */
#define WD95A_N_SRCID 28 /* Source ID Register */
#define WD95A_N_FLAG 30 /* Flag Register */
#define WD95A_N_TC_0_7 32 /* Transfer Count 0..7 */
#define WD95A_N_TC_8_15 34 /* Transfer Count 8..15 */
#define WD95A_N_TC_16_23 36 /* Transfer Count 16..23 */
#define WD95A_N_DATA 38 /* Data Access Port */
#define WD95A_N_SR 40 /* Status Register */
#define WD95A_N_FIFOS 42 /* Fifo Status Register */
#define WD95A_N_PBR 44 /* Physical Block Residue */
#define WD95A_N_BR0 46 /* Byte Residue */
#define WD95A_N_BR1 48 /* Byte Residue */
#define WD95A_N_PINGR 50 /* PING Residue */
#define WD95A_N_LRCR0 52 /* LRC Residue Register (Low) */
#define WD95A_N_LRCR1 54 /* LRC Residue Register (High) */
#define WD95A_N_ODDR 56 /* Odd-Byte Reconnect Register */
#define WD95A_N_DPR 64 /* address of first DPR */
#define W95_DPR_R(_reg) (64 + (_reg << 1))
/* Control register definition */
#define W95_CTL_SETUP (1 << 0) /* change between setup and normal */
#define W95_CTL_ABORT (1 << 1) /* Abort any operation */
#define W95_CTL_KILL (1 << 2) /* Kill any operation */
#define W95_CTL_LDTC (1 << 3) /* load transfer count */
#define W95_CTL_LDTCL (1 << 4) /* load transfer count last */
#define W95_CTL_RSTO (1 << 5) /* reset the scsi bus */
/* SCNF - SCSI Configuration Register */
#define W95_SCNF_LRCCE (1 << 0) /* LRC Checking Enable */
#define W95_SCNF_SCSIL (1 << 1) /* start low-level micro bus control */
#define W95_SCNF_SPDEN (1 << 2) /* Enable Checking for parity on bus */
#define W95_SCNF_SPUE (1 << 3) /* SCSI Pullup Enable */
#define W95_SCNF_RSTFM (1 << 4) /* RSTF output Mask */
#define W95_SCNF_SCLK (7 << 5) /* LRC Checking Enable */
#define W95_SCNF_CLK_SHFT 5 /* number of bits to shift a value */
/* DMACNF - DMA Config register */
#define W95_DCNF_BURST (1 << 0) /* burst/single cycle DMA */
#define W95_DCNF_MASTER (1 << 1) /* Master/slave DMA */
#define W95_DCNF_PGEN (1 << 2) /* Generate Parity */
#define W95_DCNF_DPEN (1 << 3) /* check for odd parity on dma data */
#define W95_DCNF_DRQAH (1 << 4) /* Active high for DRQ Signal */
#define W95_DCNF_DACAH (1 << 5) /* Active high for DACK Signal */
#define W95_DCNF_DMA16 (1 << 6) /* Transfer size 8/16 */
#define W95_DCNF_SWAP (1 << 7) /* Swap high and low bytes on dma */
/* DMATIM - dma timing register */
#define W95_DTIM_DCLKH (7 << 0) /* DMA read/write high pulse width */
#define W95_DTIM_DCLKL (7 << 3) /* DMA read/write low pulse width */
#define W95_DTIM_DSRW (1 << 6) /* DACK setup time from leading edge */
#define W95_DTIM_DMAOE (1 << 7) /* DMA output enable */
#define W95_DTIM_CH_SHFT 0 /* bits to shift width value (high) */
#define W95_DTIM_CL_SHFT 3 /* bits to shift width value (low) */
/* SC0, SC1 - low level control regiseters */
#define W95_SC0_SELO (1 << 0) /* SEL output value */
#define W95_SC0_SELI (1 << 1) /* SEL input value */
#define W95_SC0_BSYO (1 << 2) /* BSY output value */
#define W95_SC0_BSYI (1 << 3) /* BSY input value */
#define W95_SC0_RSTI (1 << 5) /* RST input value */
#define W95_SC0_SDP (1 << 6) /* SCSI parity for SD 0..7 */
#define W95_SC0_SDP1 (1 << 7) /* SCSI parity for SD 8..15 */
#define W95_SC1_REQ (1 << 0) /* REQ output/input value on bus */
#define W95_SC1_ACK (1 << 1) /* ACK output/input value on bus */
#define W95_SC1_MSG (1 << 2) /* MSG output/input value on bus */
#define W95_SC1_CD (1 << 3) /* C/D output/input value on bus */
#define W95_SC1_IO (1 << 4) /* I/O output/input value on bus */
#define W95_SC1_ATNL (1 << 5) /* ATN output/input value on bus */
#define W95_SC1_TGS (1 << 6) /* Target group sel (REQ,MSG,CD,IO) */
#define W95_SC1_IGS (1 << 7) /* Init. group sel (REQ,MSG,CD,IO) */
/* CVER - version and bus type reg */
#define W95_CVER_CVER (0xf)
#define W95_CVER_CV(_val) ((_val) & W95_CVER_CVER)
#define W95_CVER_DSENS (1 << 4) /* Differential without SE drive */
#define W95_CVER_SE (1 << 5) /* Single ended bus */
/* CTLA - Control Register, Auxiliary */
#define W95_CTLA_MRM (1 << 0) /* Mirror-Restore Mode */
#define W95_CTLA_ATNHD (1 << 1) /* Halt data transfer on ATN */
#define W95_CTLA_LRCGS (1 << 2) /* LRC generation/strip */
#define W95_CTLA_PIO (1 << 3) /* Polled IO of Fifo enabled */
#define W95_CTLA_PPEN (1 << 4) /* Ping/pong striping enable */
#define W95_CTLA_PAS (1 << 5) /* DMA port A enable */
#define W95_CTLA_PBS (1 << 6) /* DMA port B enable */
#define W95_CTLA_BYTEC (1 << 7) /* TC pipeline values are byte/block */
/* ISR - Interrupt status register */
#define W95_ISR_STOPWCS (1 << 0) /* WCS executed STOP instruction */
#define W95_ISR_INTWCS (1 << 1) /* WCS instruction with INT set */
#define W95_ISR_STOPU (1 << 2) /* WCS stopped unexpectedly */
#define W95_ISR_UEI (1 << 3) /* Unexpected Exception inter */
#define W95_ISR_BUSYI (1 << 4) /* TC trans from busy to empty */
#define W95_ISR_VBUSYI (1 << 5) /* TC trans from very busy to busy */
#define W95_ISR_SREJ (1 << 6) /* micro wrote to SQADR while inhib. */
#define W95_ISR_INT0 (1 << 7) /* INT output line asserted by ESBC */
/* STOPU - Unexpected stop status register */
#define W95_STPU_ABORTI (1 << 0) /* Abort Issued by micro */
#define W95_STPU_SCSIT (1 << 1) /* SCSI timeout during sel or resel */
#define W95_STPU_PARE (1 << 2) /* Parity Error */
#define W95_STPU_LRCE (1 << 3) /* LRC Error */
#define W95_STPU_TCUND (1 << 4) /* Transfer-count pipeline underrun */
#define W95_STPU_SOE (1 << 5) /* SCSI offset error */
/* UEI - Unexpected interrupt status register */
#define W95_UEI_FIFOE (1 << 0) /* FIFO overflow/underflow */
#define W95_UEI_ATNI (1 << 1) /* ATN asserted */
#define W95_UEI_UDISC (1 << 2) /* Unexpected SCSI bus disconnect */
#define W95_UEI_TCOVR (1 << 3) /* TC pipeline Overrun */
#define W95_UEI_USEL (1 << 4) /* Unexpected Selection */
#define W95_UEI_URSEL (1 << 5) /* Unexpected Reselection */
#define W95_UEI_UPHAS (1 << 6) /* Unexpected SCSI phase */
#define W95_UEI_RSTINTL (1 << 7) /* Reset received on SCSI bus */
/* ISRM - Interrupt mask register */
#define W95_ISRM_STOPWCSM (1 << 0) /* WCS executed Stop instruction */
#define W95_ISRM_INTWCSM (1 << 1) /* WCS instruction with INT */
#define W95_ISRM_STOPUM (1 << 2) /* WCS stopped unexpectedly */
#define W95_ISRM_UEIM (1 << 3) /* Unexpected Exception intr. */
#define W95_ISRM_BUSYIM (1 << 4) /* TC pipeline becomes empty */
#define W95_ISRM_VBUSYIM (1 << 5) /* TC pipeline becomes not full */
#define W95_ISRM_SREJM (1 << 6) /* write to SQADR while inhibited */
/* STOPUM - Unexpected stop mask register */
#define W95_STPUM_ABORTM (1 << 0) /* Abort Issued by micro */
#define W95_STPUM_SCSITM (1 << 1) /* SCSI timeout during sel or resel */
#define W95_STPUM_PAREM (1 << 2) /* Parity Error */
#define W95_STPUM_LRCEM (1 << 3) /* LRC Error */
#define W95_STPUM_TCUNDM (1 << 4) /* Transfer-count pipeline underrun */
#define W95_STPUM_SOEM (1 << 5) /* SCSI offset error */
/* UEIM - Unexpected interrupt mask register */
#define W95_UEIM_FIFOEM (1 << 0) /* FIFO overflow/underflow */
#define W95_UEIM_ATNIM (1 << 1) /* ATN asserted */
#define W95_UEIM_UDISCM (1 << 2) /* Unexpected SCSI bus disconnect */
#define W95_UEIM_TCOVRM (1 << 3) /* TC pipeline Overrun */
#define W95_UEIM_USELM (1 << 4) /* Unexpected Selection */
#define W95_UEIM_URSELM (1 << 5) /* Unexpected Reselection */
#define W95_UEIM_UPHASM (1 << 6) /* Unexpected SCSI phase */
#define W95_UEIM_RSTINTM (1 << 7) /* Reset received on SCSI bus */
/* RESPONSE - Automatic response control register */
#define W95_RESP_SELL (1 << 0) /* Enable low-level sel resp */
#define W95_RESP_SELH (1 << 1) /* Enable high-level sel resp */
#define W95_RESP_RSELL (1 << 2) /* Enable low-level resel resp */
#define W95_RESP_RSELH (1 << 3) /* Enable high-level resel resp */
#define W95_RESP_AUTOR (1 << 4) /* Automatic reconnect on DMA req */
#define W95_RESP_AUTOD (1 << 5) /* pause data trans at logical blk */
#define W95_RESP_ALLRR (1 << 6) /* Auto low-level response reset */
/* STC - SCSI trasfer control register */
#define W95_STC_OFF_M 0x3f /* synchronous transfer offset */
#define W95_STC_WSCSI (1 << 7) /* enable wide SCSI trans for data */
/* SPW - SCSI Synchronous clock Pulse width */
#define W95_SPW_SCLKA (7 << 0) /* clock assertion pulse width */
#define W95_SPW_SCLKA_SFT 0 /* bit position for shift */
#define W95_SPW_SCLKN (7 << 4) /* clock negation pulse width */
#define W95_SPW_SCLKN_SFT 4 /* bit position for shift */
/* SRCID - source ID register */
#define W95_SRCID_M 0xf /* mask for source id */
#define W95_SRCID_SIV (1 << 4) /* valid se/reselection */
/* SR - status register */
#define W95_SR_BUSY (1 << 0) /* ESBC is busy */
#define W95_SR_VBUSY (1 << 1) /* ESBC is very busy */
#define W95_SR_ACTIVE (1 << 2) /* WCS is running */
#define WCS_NOWHERE 0x7f /* don't do anything */
#endif /* _SYS_WD95A_ */
stand/arcs/include/sys/wd95a_struct.h
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/**************************************************************************
* *
* Copyright (C) 1992, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
/*
* wd95a_struct.h -- Western Digital 95a driver data structures.
*/
#ident "$Revision: 1.4 $"
#ifndef _SYS_WD95A_STRUCT
#define _SYS_WD95A_STRUCT
#if defined(EVEREST) && !defined(SCSI_3)
#define SCSI_3
#endif
/* definitions for numbers of things */
#if !defined(EVEREST)
#define WD95_CTLRS 8 /* max # of controllers */
#endif
#define WD95_QDEPTH 1 /* number of outstanding que'd */
#ifdef SCSI_3
#define WD95_LUPC 16 /* logical units per controller */
#else
#define WD95_LUPC 8 /* logical units per controller */
#endif
/* defines for scsirequest.sr_ha_flags */
#define WFLAG_ODDBYTEFIX 1
/*
* WD95a driver equivalent of scsirequest -- once a slot is
* free, a wd95request gets matched with a scsirequest.
*/
struct wd95request {
u_char active : 1,
starting : 1;
u_char ctlr;
u_char unit;
u_char lun;
u_char cmd_tag; /* command tag */
u_char reset_num; /* reset number when timeout started */
int timeout_id;
int resid;
int tlen;
struct scsi_request *sreq;
struct wd95request *next;
};
typedef struct wd95request wd95request_t;
/* per logical unit (lun) information structure */
struct wd95luninfo {
u_char lun_num; /* lun number for this device */
u_char sense:1, /* request sense in progress */
excl_act:1, /* exclusive access active */
cmdt_en:1; /* cmd tag queueing available */
uint refcnt;
scsi_request_t *u_sense_req; /* scsi request for sense info */
wd95request_t *wqueued; /* queue of active for this device */
struct scsi_target_info tinfo;
};
typedef struct wd95luninfo wd95luninfo_t;
/* per unit (device) information structure */
struct wd95unitinfo {
u_char number; /* unit number of this unit (0-13) */
u_char wreq_cnt; /* count of total wreqs for this target */
ushort sense:1, /* request sense in progress */
active:1, /* unit is currently active */
u_ca:1, /* contingent allegiance occurred */
abortqueue:1, /* work queues aborted */
aenreq:1, /* need AEN acknowledge */
tostart:1, /* start timeout running */
disc:1, /* disconnect enabled */
sync_en:1, /* sync is OR should be enabled */
sync_req:1, /* sync negotiation needed */
wide_en:1, /* wide is OR should be enabled */
wide_req:1, /* wide negotiation needed */
ext_msg:1, /* extended message in progress */
cmdt_en:1; /* enable cmd tag queueing */
u_char sync_off; /* negotiated sync offset */
u_char sync_per; /* required sync period */
u_char sel_tar; /* location for selection */
u_char lun_round; /* round robin queue lun checking */
u_char cur_lun; /* current lun under service */
scsi_request_t *reqhead; /* queue commands here normally */
scsi_request_t *reqtail;
scsi_request_t *auxhead; /* queue commands here when u_ca set */
scsi_request_t *auxtail;
wd95request_t *wrfree; /* pointer to free wd95request structs */
wd95request_t wreq[WD95_QDEPTH];
wd95luninfo_t *lun_info[SCSI_MAXLUN];
wd95luninfo_t lun_0;
void (*sense_callback)(char *);
struct wd95ctlrinfo *ctrl_info;
sema_t opensem;
sema_t start; /* queue for no-notify semaphore */
sema_t done; /* semaphore for no-notify commands */
#if WD95_CMDHIST
char prevcmd[16][12];
int prevcmd_rotor;
#endif
};
typedef struct wd95unitinfo wd95unitinfo_t;
struct wd95ctlrinfo {
lock_t lock;
lock_t qlock; /* Lock for structure queues */
lock_t auxlock;
u_char number; /* number of this controller */
u_char ci_idmsgin; /* resel & looks like id msg in */
u_char host_id; /* host id of this controller */
u_char round_robin; /* last unit number that was checked */
u_char max_round; /* unit to wrap at */
u_char cur_target; /* current target id */
u_char reset_num; /* current reset number */
ushort present:1, /* flag indicating if ctlr is installed */
reset:1, /* set if resetting scsi busses */
pagebusy:1, /* odd-byte fixup buffer use status */
active:1, /* controller is currently active */
intr:1, /* currently processing intr on this ctlr */
narrow:1, /* this is a narrow bus (limited by hw) */
diff:1; /* clear if single ended, set if differential */
u_char sync_period; /* synchronous period for this controller */
u_char sync_offset; /* and offset for this controller */
u_char *page; /* odd-byte fixup buffer */
ushort *wdi_log; /* log all accesses to wd95 */
sema_t d_sleepsem; /* Synchronous request waiting sem */
sema_t d_onlysem; /* 'only' request waiting sem */
short d_sleepcount; /* Synchronous request waiter count */
short d_onlycount; /* Synchronous request waiter count */
scsi_request_t *acthead; /* queue commands here while active */
scsi_request_t *acttail;
caddr_t ha_addr; /* address of the associated wd95a chip */
dmamap_t *d_map;
struct wd95unitinfo *unit[WD95_LUPC]; /* unit info */
};
typedef struct wd95ctlrinfo wd95ctlrinfo_t;
/* flags for each bus */
#define WD95BUS_SYNC 0x01 /* Synchronous enable */
#define WD95BUS_DISC 0x02 /* Disconnect/reconnect enable */
#define WD95BUS_WIDE 0x04 /* Wide enable */
#define WD95BUS_LUN_CK 0x08 /* check all the luns on the bus */
#define WD95BUS_CMDT 0x10 /* cmd tag queueing enable */
extern u_char wd95_bus_flags[];
extern u_char wd95_syncperiod[];
#endif /* _SYS_WD95A_ */
stand/arcs/include/sys/wd95a_wcs.h
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/***********************************************************************\
* File: wd95a_wcs.h *
* *
* Contains the defines for the Control Store for the wd95a *
* *
* NOTE: This file needs to maintain strict coordianation with *
* wd95a_wcs.c *
* *
\***********************************************************************/
#ifndef _SYS_WD95A_WCS_
#define _SYS_WD95A_WCS_
#ident "$Revision: 1.4 $"
/* WCS - info (Initiator) */
#define WCS_I_SEL 0 /* initiator starts sel */
#define WCS_I_SEL_NOMSG 0x01 /* where we tend to stop without msgs*/
#define WCS_I_ITL_NEXUS 0x02 /* go do just a straight id */
#define WCS_I_RESEL 0x0a /* initiator starts resel */
#define WCS_I_RSL_UNK 0x0a /* unknown message on resel */
#define WCS_I_RSL_ID 0x0b /* ID message */
#define WCS_I_RSL_QT 0x0c /* que tag type message */
#define WCS_I_RSL_QUE 0x0d /* que tag message */
#define WCS_I_DISPATCH 0x0e /* initiator phase change handler */
#define WCS_I_DATA 0x1b /* in the midst of the data phase */
#define WCS_I_UNK_MSG 0x24 /* unknown message in phase */
/* possibly save/restore pointer */
#define WCS_I_MSGI_0 0x27 /* extended message in with 0 len */
#define WCS_I_MSGI_1 0x29 /* extended message in with 1 len */
#define WCS_I_MSGI_2 0x2b /* extended message in with 2 len */
#define WCS_I_MSGI_3 0x2d /* extended message in with 3 len */
#define WCS_I_MSGI_4 0x2f /* extended message in with 4 len */
#define WCS_I_MSGI_5 0x30 /* extended message in with 5 len */
#define WCS_I_DISC 0x33 /* disconnected from bus */
#define WCS_I_CONCLUDE 0x46 /* starting the conclusion sequence */
#define WCS_I_EOP_FREE 0x4d /* waiting for bus free */
#define WCS_I_COMPLETE 0x4e /* completed command */
#define WCS_I_NATN 0x64 /* negate attention, go to dispatch */
#define WCS_I_SEL_EXT 0x70 /* selection with extended message */
#define WCS_I_SEL_E_NM 0x71 /* selection with extended but no msg*/
#define WCS_I_NRESEL 0x75 /* new initiator starts resel */
#define WCS_I_RSLCONT 0x75 /* after reselection, continue here */
#define WCS_I_NRSL_ID 0x76 /* just simple id reconnect */
#define WCS_I_SEL_NATN 0x7d /* select without atn */
/* Initiator flag values */
#define WCS_I_DATA_OK (1<<0) /* data phase ok */
#define WCS_I_DIR (1<<1) /* data phase direction (set == in) */
#define WCS_I_MULTI_MSG (1<<2) /* multiple byte message out */
/* Initiator Dual port reg locations */
#define WCS_I_MSG_OUT 0 /* message out block */
#define WCS_I_TAG_OUT 2 /* tag message for initial conn. */
#define WCS_I_QUE_OUT 3 /* tag value for initial conn. */
#define WCS_I_ID_OUT 5 /* Identify message out */
#define WCS_I_MSG_OUT_L 7 /* message out length */
#define WCS_I_ID_IN 8 /* identify message in for reconn. */
#define WCS_I_TAG_IN 9 /* tag message for reconn. */
#define WCS_I_QUE_IN 10 /* queue message for reconn. */
#define WCS_I_STATUS 11 /* status byte */
#define WCS_I_MSG_IN 12 /* message in block */
#define WCS_I_CMD_BLK 20 /* command bytes */
/* WCS - info (Target) */
#define WCS_T_SELECTED 0 /* where to start when sel */
#define WCS_T_CMD_FIN 0x26 /* finish after command read */
#define WCS_T_DATA 0x31 /* data transfer location */
/* CMP register values */
#define WCS_T_IDENT_IDX 0 /* Identify compare regs */
#define WCS_T_QUE_IDX 1 /* queue tag compare regs */
#define WCS_T_CMP_TAG_IDX 2 /* compare tag index */
#define WCS_T_CMP_LUN_IDX 3 /* compare lun index */
#define WCS_T_GRP_7_IDX 4 /* Group 7 index */
#define WCS_T_ID_DISC_IDX 5 /* Identify with disc regs */
#define WCS_T_ID_AND 0xf8 /* mask value for ID regs */
#define WCS_T_ID_XOR 0x80 /* compare value for ID regs */
#define WCS_T_QUE_AND 0xfc /* mask value for QUEUE regs */
#define WCS_T_QUE_XOR 0x20 /* compare value for QUEUE regs */
#define WCS_T_ID_D_AND 0xc0 /* mask value for ID/disc regs */
#define WCS_T_ID_D_XOR 0xc0 /* compare value for ID/disc regs */
/* Target flag values */
#define WCS_T_QT (1<<0) /* que'd tag ok */
#define WCS_T_DWD (1<<1) /* disconnect on w data */
#define WCS_T_DISC_OK (1<<2) /* disconnect ok */
#define WCS_T_SDP (1<<3) /* SDP before Disconn. */
#define WCS_T_TTD (1<<4) /* transfer data */
#define WCS_T_DIR_OUT (1<<5) /* data phase dir is out */
#define WCS_T_LINK (1<<6) /* Linking ok */
#define WCS_T_LAST (1<<7) /* high bit set */
/* Target Dual Port Reg locations */
#define WCS_T_MSG_OUT 0x03 /* message out block */
#define WCS_T_ID_OUT 0x00 /* id message for initial conn. */
#define WCS_T_TAG_OUT 0x02 /* tag message for initial conn. */
#define WCS_T_QUE_OUT 0x01 /* tag value for initial conn. */
#define WCS_T_ID_IN 0x07 /* id message for reconn. */
#define WCS_T_TAG_IN 0x09 /* tag message for reconn. */
#define WCS_T_QUE_IN 0x08 /* tag value for reconn. */
#define WCS_T_CMD_CMPL 0x0b /* image of message for sending */
#define WCS_T_DISC 0x06 /* image of disconnect for sending */
#define WCS_T_SP_MSG 0x05 /* image of save pointer for send */
#define WCS_T_MSG_IN 0x04 /* message in block location */
#define WCS_T_MSG_IN_L 0x0c /* message in length */
#define WCS_T_CMD 0x14 /* command bytes (up to 12) */
#define WCS_T_STATUS 0x0a /* loc for status */
#define WCS_SIZE 128 /* maximum size in the wcs */
/* WCS values */
#define WCS_INITIATOR 0 /* set up as initiator */
extern unsigned long _wcs_ini_load[];
#endif /* _SYS_WD95A_WCS_ */