calmsacibis995
362 lines
7.2 KiB
C
362 lines
7.2 KiB
C
;Common software definitions for the 29K firmware
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; Copyright 1994 Silicon Graphics, Inc. All rights reserved.
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; "$Revision: 1.14 $"
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;move between registers without affecting ALU flags
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.macro mov, reg1,reg2
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sll reg1,reg2,0
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.endm
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;conditional call
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.macro callt, reg,ret,tgt,branch
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CK reg != ret
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.ifeqs "@branch@",""
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const ret,$1
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jmpt reg,tgt
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consth ret,$1
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$1:
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.else
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jmpf reg,branch
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const ret,branch
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jmp tgt
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consth ret,branch
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.endif
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.endm
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;load a constant which we promise is <64K
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.macro const0, reg,val
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.if (val) != 0x8000000 && ((val)&0xffff0000) != 0 && ((val)&0xffff0000) != 0xffff0000
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.print " ** Error: @val@ cannot be set in one instruction"
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.err
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.endif
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constx reg,val
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.endm
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;load a constant
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.macro constx, reg,val
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.if ((val) & 0xffff0000) == 0xffff0000
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constn reg,val
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.exitm
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.endif
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.if (val) == 0x80000000
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cpeq reg,reg,reg
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.exitm
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.endif
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const reg,val
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.if ((val) & 0xffff0000) != 0
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consth reg,val
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.endif
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.endm
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;load the contents of a memory location
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.macro lod, reg,addr
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constx reg,addr
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load 0,WORD,reg,reg
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.endm
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;store a register
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.macro sto, val,addr,st1,st2
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.if $ISREG(addr)
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.if $ISREG(val)
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store 0,WORD,val,addr
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.else
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constx st1,val
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store 0,WORD,st1,addr
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.endif
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.else
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constx st1,addr
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.if $ISREG(val)
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store 0,WORD,val,st1
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.else
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constx st2,val
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store 0,WORD,st2,st1
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.endif
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.endif
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.endm
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;read or write (op) a value (val) an address (tag) within "structure" (strc)
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; which has a pointer in a register (p_strc) using a temporary
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; register (tmp)
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.macro OPST, op,wid,strc,p_strc,tag,val,tmp,fs
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.if tag == strc
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.ifeqs "@fs@","fast"
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.else
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.ifnes "@fs@",""
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.print "** Error: @fs@ is not 'fast' or null"
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.err
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.endif
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mtsrim MMU,0xff
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.endif
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op 0,@wid@WORD,val,p_strc
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.else
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.if tag > strc
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.if strc == 0
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constx tmp,tag
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.else
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add tmp,p_strc,tag-strc
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.endif
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.else
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sub tmp,p_strc,strc-tag
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.endif
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.ifeqs "@fs@","fast"
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.else
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.ifnes "@fs@",""
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.print "** Error: @fs@ is not 'fast' or null"
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.err
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.endif
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mtsrim MMU,0xff
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.endif
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op 0,@wid@WORD,val,tmp
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.endif
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.endm
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;define a bit
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.macro DEFBT, nam, bitno
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.equ nam,1<<(bitno)
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.if (bitno)>31
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.print " ** Error: '@bitno@' is an invalid bit number"
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.err
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.endif
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.equ @nam@_BT,bitno
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.endm
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;define the next bit in a register
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; NEXT_BT should be set =0 before each series of uses of this macro.
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.macro NXTBT, nam
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DEFBT nam,NEXT_BT
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.set NEXT_BT,NEXT_BT+1
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.endm
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;check a bit
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; handy to prevent the common errors of forgetting the "31-" or "_BT"
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.macro tbit, tgt, src, bitnam
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sll tgt,src,31-@bitnam@_BT
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.endm
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;move a bit from one register to another
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.macro mv_bt, tgt,tbit, src,sbit
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.if @tbit@_BT < @sbit@_BT
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srl tgt,src, @sbit@_BT-@tbit@_BT
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.else
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.if @tbit@_BT > @sbit@_BT || tgt != src
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sll tgt,src, @tbit@_BT-@sbit@_BT
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.endif
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.endif
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.endm
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;check that something is true
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.macro CK, exp
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.if !(exp)
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.print " ** Error: !(@exp@)"
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.err
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.endif
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.endm
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;check that a value is a power of 2
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.macro CK2, exp
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.if (exp) != ((exp) & -(exp))
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.print " ** Error: @exp@ is not a power of 2"
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.err
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.endif
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.endm
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;align data
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.macro DALIGN, exp
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.block (0-.) & ((exp)-1)
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.endm
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;check alignment
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.macro CKALIGN, exp
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.if ((0-.) & ((exp)-1)) != 0
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.print " ** Error: not aligned to @exp@"
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.err
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.endif
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.endm
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;common constants
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.equ TRUE,0x80000000
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.equ FALSE,0
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.equ USEC_SEC, 1000000
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;Common register definitions
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.reg rsp, gr1 ;Register Stack Pointer
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;.reg xxx, gr64-gr95 ;available
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.reg v0, gr96 ;16 function value return regs
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.reg v1, gr97
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.reg v2, gr98
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.reg v3, gr99
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.reg v4, gr100
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.reg v5, gr101
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.reg v6, gr102
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.reg v7, gr103
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.ifndef FEW_VS
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.reg v8, gr104
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.reg v9, gr105
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.reg v10,gr106
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.reg v11,gr107
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.reg v12,gr108
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.reg v13,gr109
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.reg v14,gr110
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.reg v15,gr111
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.endif
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; .reg ret,gr96 ;First word of return value
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;gr97-gr111 or v1-v15 are the rest of the return value
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.reg u0, gr112 ;"Reserved for Programmer" by Metaware
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.reg u1, gr113
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.reg u2, gr114
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.reg u3, gr115
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.reg t0, gr116 ;temporaries
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.reg t1, gr117
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.reg t2, gr118
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.reg t3, gr119
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.reg t4, gr120
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.reg tav,gr121 ;Temporary, Argument for Trap Handlers
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.reg tpc,gr122 ;Temporary, Return PC for Trap Handlers
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.reg lrp,gr123 ;Large Return Pointer
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.reg slp,gr124 ;Static Link Pointer
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.reg msp,gr125 ;Memory Stack Pointer
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.reg rab,gr126 ;Register Allocate Bound
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.reg rfb,gr127 ;Register Free Bound
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.reg raddr,lr0 ;subroutine link
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;These macros allocate register, saving the hassle of ensuring that the
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; same register is not allocated twice.
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; greg allocates the next general purpose register,
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; lreg allocates the next local register,
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; A variable with the same name as the register but with "_" appended
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; is defined to make it easier to discover the number of the register
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; in the Metaware as29 listing.
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;Allocate a general purpose register register
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.macro greg, nam
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.if NEXT_GREG >= 112
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.print " ** Error: no more rgisters available for @nam@"
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.err
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.endif
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.reg nam, %%NEXT_GREG
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.if NEXT_GREG==95
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.set NEXT_GREG, 104 ;use the extra V registers
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.ifdef v8
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.set NEXT_GREG, 112 ;unless they are not available
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.endif
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.else
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.set NEXT_GREG, NEXT_GREG+1
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.endif
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.endm
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;Allocate a local register
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.macro lreg, nam
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.if NEXT_LREG >= 128
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.print " ** Error: no more rgisters available for @nam@"
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.err
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.endif
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.reg nam, %%(NEXT_LREG+128)
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.set NEXT_LREG, NEXT_LREG+1
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.endm
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; say how to start generating registers
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.set NEXT_LREG, 0 ;start at lr0
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.set NEXT_GREG, 64 ;start at gr64
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;common CNTL field values for load and store instructions.
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.equ AS, 0x40
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.equ PA, 0x20
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.equ SB, 0x10
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.equ UA, 0x08
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.equ WORD, 0
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.equ BYTE, 1
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.equ HWORD,2
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;common CPS and OPS values
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DEFBT PS_DA, 0
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DEFBT PS_DI, 1
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DEFBT PS_SM, 4
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DEFBT PS_PI, 5
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DEFBT PS_PD, 6
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DEFBT PS_WM, 7
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; DEFBT PS_RE, 8 ;29000 only
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DEFBT PS_FZ, 10
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.equ PS_IM, 0x00c
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DEFBT PS_TU, 11
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DEFBT PS_IP, 14
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.ifdef AM20935
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DEFBT PS_TD, 17
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.endif
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.equ PS_INTSON, PS_SM | PS_PI | PS_PD | PS_IM
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.equ PS_INTSOFF, PS_INTSON | PS_DI | PS_DA
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.equ PS_FREEZE, PS_INTSOFF | PS_FZ
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;common CFG values
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.equ CFG_PMB_16K,0x00030000
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.ifdef AM20935
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DEFBT CFG_D16, 15
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.equ CFG_ILU, 0x00000600 ;unlock cache
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.equ CFG_IL, 0x00000000 ;lock cache
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.endif
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DEFBT CFG_ID, 8 ;disable cache
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.ifdef AM29030
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.equ CFG_ILU, 0x00000000 ;unlock cache
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.equ CFG_IL, 0x00000600 ;lock cache
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.endif
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; DEFBT CFG_DW, 5 ;29000 only
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; DEFBT CFG_VF, 4 ;29000 only
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DEFBT CFG_BO, 2
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; DEFBT CFG_CD, 0 ;29000 only
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;bits in Cache Interface Register
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.equ CIR_FSEL_INST, 0
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.equ CIR_FSEL_TAG, 0x10000000
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DEFBT CIR_RW, 24
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;timer bits
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DEFBT TMR_IE, 24
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DEFBT TMR_IN, 25
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DEFBT TMR_OV, 26
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.equ USEC_PER_SEC, 1000000
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;common trap numbers
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.equ V_MULIPLY, 32
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.equ V_DIVIDE, 33
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.equ V_MULIPLU, 34
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.equ V_DIVIDU, 35
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.equ V_TIMER, 14
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.equ V_INTR0, 16
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.equ V_INTR1, 17
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.equ V_INTR2, 18
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.equ V_INTR3, 19
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.equ V_TRAP0, 20
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.equ V_TRAP1, 21
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.equ V_SPILL,64
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.equ V_FILL, 65
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.equ NUM_V, 256 ;# of traps and interrupts
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