197 lines
3.9 KiB
ArmAsm
197 lines
3.9 KiB
ArmAsm
/*
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* IP20 specific assembly routines; cpuid always 0, also make semaphore
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* macros a no-op.
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*/
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#ident "$Revision: 1.13 $"
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#include "ml/ml.h"
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/* dummy routines whose return value is unimportant (or no return value).
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Some return reasonable values on other machines, but should never
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be called, or the return value should never be used on other machines.
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*/
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LEAF(dummy_func)
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XLEAF(check_delay_tlbflush)
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XLEAF(check_delay_iflush)
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XLEAF(da_flush_tlb)
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XLEAF(dma_mapinit)
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XLEAF(dma_mapfree)
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XLEAF(apsfail)
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XLEAF(disallowboot)
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XLEAF(rmi_fixecc)
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j ra
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END(dummy_func)
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LEAF(dcache_wb)
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XLEAF(dcache_wbinval)
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XLEAF(dki_dcache_wb)
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XLEAF(dki_dcache_wbinval)
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LI a2,CACH_DCACHE|CACH_INVAL|CACH_WBACK|CACH_IO_COHERENCY
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j cache_operation
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END(dcache_wb)
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LEAF(dki_dcache_inval)
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LI a2,CACH_DCACHE|CACH_INVAL|CACH_IO_COHERENCY
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j cache_operation
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END(dki_dcache_inval)
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/* dummy routines that return 0 */
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LEAF(dummyret0_func)
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XLEAF(vme_adapter)
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XLEAF(is_vme_space)
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XLEAF(getcpuid)
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XLEAF(dma_mapaddr)
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#ifdef DEBUG
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XLEAF(getcyclecounter)
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#endif /* DEBUG */
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/* Semaphore call stubs */
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XLEAF(appsema)
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XLEAF(apvsema)
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XLEAF(apcvsema)
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move v0,zero
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j ra
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END(dummy_func)
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/* dummy routines that return 1 */
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LEAF(dummyret1_func)
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XLEAF(apcpsema) /* can always get on non-MP machines */
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li v0, 1
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j ra
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END(dummy_func)
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/* return time stamp */
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LEAF(_get_timestamp)
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.set noreorder
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mfc0 v0,C0_COUNT
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.set reorder
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j ra
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END(get_timestamp)
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/*
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*
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* writemcreg (reg, val)
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*
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* Basically this does *(volatile uint *)(PHYS_TO_K1(reg)) = val;
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* a0 - physical register address
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* a1 - value to write
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*
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* This is a workaround for a bug in the first rev MC chip.
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*
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* Because of (what I'd call a bug in) ld, we have to
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* resort to a kludge in order to ensure that this code
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* will never share its cache-line.
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*/
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LEAF(writemcreg)
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/*
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* Reserve a cacheline.
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*/
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.set noreorder
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j 4f
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nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop
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4:
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la v0,1f
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or v0,SEXT_K1BASE
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j v0 # run uncached
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1: or a0,SEXT_K1BASE # a0 = PHYS_TO_K1(a0)
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#ifdef MIPSEB
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lw v0,0xbfc00004 # dummy read from prom to flush mux fifo
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#else
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lw v0,0xbfc00000 # dummy read from prom to flush mux fifo
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#endif
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sw a1,(a0) # write val in a1 to MC register *a0
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j ra
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/*
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* Reserve a cacheline.
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*/
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop
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.set reorder
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END(writemcreg)
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/*
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* Write the VDMA MEMADR, MODE, SIZE, STRIDE registers
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*
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* write4vdma (buf, mode, size, stride);
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*/
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LEAF(write4vdma)
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.set noreorder
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j 4f # These nops are just for show.
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nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop
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4:
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la v0,1f
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or v0,SEXT_K1BASE # run uncached
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j v0
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1:
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#ifdef MIPSEB
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lw v1,0xbfc00004 # dummy read from prom to flush mux fifo
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#else
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lw v1,0xbfc00000 # dummy read from prom to flush mux fifo
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#endif
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/* XXX Only works because bit 15 not set in DMA_MEMADR */
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lui v0, (K1BASE | DMA_MEMADR)>>16
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sw a0,DMA_MEMADR & 0xffff(v0)
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sw a1,DMA_MODE & 0xffff(v0)
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sw a2,DMA_SIZE & 0xffff(v0)
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sw a3,DMA_STRIDE & 0xffff(v0)
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/*
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sw ??,DMA_ GIOADRS & 0xffff(v0)
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*/
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j ra
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/*
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* Reserve a cacheline.
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*/
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop;
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nop; nop; nop; nop
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.set reorder
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END(write4vdma)
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