108 lines
2.1 KiB
ArmAsm
108 lines
2.1 KiB
ArmAsm
/*
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* IP22 specific assembly routines; cpuid always 0, also make semaphore
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* macros a no-op.
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*/
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#ident "$Revision: 1.1 $"
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#include "ml/ml.h"
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/* dummy routines whose return value is unimportant (or no return value).
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Some return reasonable values on other machines, but should never
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be called, or the return value should never be used on other machines.
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*/
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LEAF(dummy_func)
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XLEAF(check_delay_tlbflush)
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XLEAF(check_delay_iflush)
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XLEAF(da_flush_tlb)
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XLEAF(dma_mapinit)
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XLEAF(apsfail)
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XLEAF(disallowboot)
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XLEAF(rmi_fixecc)
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XLEAF(vme_init)
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XLEAF(vme_ivec_init)
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j ra
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END(dummy_func)
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LEAF(dcache_wb)
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XLEAF(dcache_wbinval)
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XLEAF(dki_dcache_wb)
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XLEAF(dki_dcache_wbinval)
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LI a2,CACH_DCACHE|CACH_INVAL|CACH_WBACK|CACH_IO_COHERENCY
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j cache_operation
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END(dcache_wb)
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LEAF(dki_dcache_inval)
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LI a2,CACH_DCACHE|CACH_INVAL|CACH_IO_COHERENCY
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j cache_operation
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END(dki_dcache_inval)
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/* dummy routines that return 0 */
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LEAF(dummyret0_func)
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XLEAF(vme_adapter)
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XLEAF(is_vme_space)
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XLEAF(getcpuid)
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XLEAF(disarm_threeway_trigger)
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XLEAF(threeway_trigger_armed)
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#ifdef DEBUG
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XLEAF(getcyclecounter)
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#endif /* DEBUG */
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/* Semaphore call stubs */
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XLEAF(appsema)
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XLEAF(apvsema)
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XLEAF(apcvsema)
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move v0,zero
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j ra
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END(dummy_func)
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/* dummy routines that return 1 */
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LEAF(dummyret1_func)
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XLEAF(apcpsema) /* can always get on non-MP machines */
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li v0, 1
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j ra
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END(dummy_func)
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#if 0
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EXPORT(prom_dexec)
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li v0,PROM_DEXEC
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j v0
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/* load the nvram table from the prom.
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prom_nvram_tab(addr, size)
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This means we don't embed the info of the current layout
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anywhere but in the prom.
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*/
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EXPORT(prom_nvram_tab)
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li v0,PROM_NVRAM_TAB
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j v0
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#endif
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/* return time stamp */
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LEAF(_get_timestamp)
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j get_r4k_counter
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END(get_timestamp)
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/*
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*
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* writemcreg (reg, val)
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*
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* Basically this does *(volatile uint *)(PHYS_TO_K1(reg)) = val;
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* a0 - physical register address
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* a1 - value to write
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*
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* This was a workaround for a bug in the first rev MC chip, but IP22
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* has only rev B (or greater) MCs, so just do the actual operation.
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*/
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LEAF(writemcreg)
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/*
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* Reserve a cacheline.
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*/
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or a0,K1BASE # a0 = PHYS_TO_K1(a0)
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sw a1,(a0)
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j ra
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END(writemcreg)
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