302 lines
12 KiB
C
302 lines
12 KiB
C
/**************************************************************************
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* *
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* Copyright (C) 1994, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ident "$Revision: 1.51 $"
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/* IP26.h -- CPU module specific defines for IP26. We use IP22.h for system
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* board information since they use the same board.
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*
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* The Power Indigo2, Power Challenge M and Indigo2 100000 systems implement
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* an ECC memory system that does not allow uncached writes to sytem memory
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* while the system is running in normal mode. It is possible to write to
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* uncached memory by either:
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*
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* * Using the 'ucmem' routines around uncached accesses:
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*
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* long ucmem;
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* ...
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* ucmem = ip26_enable_ucmem();
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* ... uncached access ...
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* ip26_return_ucmem(ucmem);
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*
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* * Setting the system to always run in slow mode by setting the
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* systune 'ip26_allow_ucmem' flag to 1. This will result in
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* lower memory performance and overall system performance and
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* should only be used as a last resort.
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*
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* Implications of these features impose mostly on device drivers that
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* access shared data structures (DMA descriptors, etc) uncached to
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* avoid race conditions. Often this can often be fixed by aligning
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* data on cache line boundries and flushing the cache, or by using
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* the ucmem routines.
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*
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* Lastly, user mode use of the cachectl(2) call with UNCACHEABLE is
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* not honored unless the global systune flag ip26_enable_ucmem is set
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* is set to true. This may have an impact on user level device drivers.
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*/
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#ifndef __SYS_IP26_H__
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#define __SYS_IP26_H__
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#include <sys/IP22.h>
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/* TCC address map:
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*/
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#define TCC_BASE 0x18000000 /* Base of TCC registers */
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#define TCC_FIFO 0x18000000 /* FIFO Control Register */
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#define TCC_GCACHE 0x18000008 /* GCache Control Register */
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#define TCC_INTR 0x18000010 /* Interrupt Register */
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#define TCC_BE_ADDR 0x18000018 /* Bus Error Addr Register */
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#define TCC_ERROR 0x18000020 /* Error Info Register */
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#define TCC_PARITY 0x18000028 /* Parity Control Register */
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#define TCC_COUNT 0x18000030 /* Count Register */
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#define TCC_COMPARE 0x18000038 /* Compare Register */
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#define TCC_CAM0 0x18010000 /* Prefetch CAM 0 */
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#define TCC_CAM1 0x18010008 /* Prefetch CAM 1 */
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#define TCC_CAM2 0x18010010 /* Prefetch CAM 2 */
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#define TCC_CAM3 0x18010018 /* Prefetch CAM 3 */
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#define TCC_CAM4 0x18010020 /* Prefetch CAM 4 */
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#define TCC_PREFETCH_A 0x18010028 /* Prefetch Address A */
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#define TCC_PREFETCH_B 0x18010030 /* Prefetch Address B */
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#define TCC_PREFETCH 0x18010038 /* Prefetch Control Register */
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#define TCC_ETAG_DA 0x18100000 /* Even Tag Data Access */
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#define TCC_OTAG_DA 0x18200000 /* Odd Tag Data Access */
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#define TCC_ETAG_ST 0x18300000 /* Even Tag State Access */
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#define TCC_OTAG_ST 0x18400000 /* Odd Tag State Access */
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/* TCC_FIFO -- graphics FIFO Control Register
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*/
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#define FIFO_INPUT_EN 0x00000001 /* Gfx fifo input enable */
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#define FIFO_OUTPUT_EN 0x00000002 /* Gfx fifo output enable */
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#define FIFO_HW 0x000003f0 /* High water setting */
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#define FIFO_HW_SHIFT 4
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#define FIFO_LW 0x0003f000 /* Low water setting */
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#define FIFO_LW_SHIFT 12
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#define FIFO_LEVEL 0x03f00000
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#define FIFO_LEVEL_SHIFT 20
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/* TCC_GCACHE -- GCache Control Register
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*/
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#define GCACHE_SETALLOW 0x0000000f /* Bitmap of enabled sets */
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#define GCACHE_SET0 0x00000001 /* Enable set 0 */
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#define GCACHE_SET1 0x00000002 /* Enable set 1 */
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#define GCACHE_SET2 0x00000004 /* Enable set 2 */
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#define GCACHE_SET3 0x00000008 /* Enable set 3 */
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#define GCACHE_FORCE_SET3 0x00000010 /* Force set 3 */
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#define GCACHE_WBACK_INH 0x00000020 /* Inhibits dirty writeback */
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#define GCACHE_RR_FULL 0x000003c0 /* Read response full level */
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#define GCACHE_RR_FULL_SHIFT 6
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#define GCACHE_WB_RESTART 0x00003c00 /* Writeback restart level */
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#define GCACHE_WB_RESTART_SHIFT 10
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#define GCACHE_REL_DELAY 0x0003c000 /* Release delay */
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#define GCACHE_REL_DELAY_SHIFT 14
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#define GCACHE_REV 0x003c0000 /* TCC revision */
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#define GCACHE_REV_SHIFT 18
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/* TCC_INTR -- Interrupt Register
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*/
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#define INTR_PENDING 0x0000003f /* Intrrupts pending IP<7:2> */
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#define INTR_FIFO_HW 0x00000040 /* Gfx FIFO high water intr */
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#define INTR_FIFO_LW 0x00000080 /* Gfx FIFO low water intr */
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#define INTR_TIMER 0x00000100 /* TCC Timer Interrupt */
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#define INTR_BUSERROR 0x00000200 /* TCC detected Bus Error */
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#define INTR_MACH_CHECK 0x00000400 /* TCC detected Machine Check */
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#define INTR_FIFO_HW_EN 0x00000800 /* Gfx FIFO HW Enabled */
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#define INTR_FIFO_LW_EN 0x00001000 /* Gfx FIFO LW Enabled */
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#define INTR_TIMER_EN 0x00002000 /* TCC Timer Intr Enable */
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#define INTR_BUSERROR_EN 0x00004000 /* TCC Bus Error Enable */
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#define INTR_MACH_CHECK_EN 0x00008000 /* TCC Mach Check Enable */
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/* TCC_ERROR -- Error Info Register
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*/
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#define ERROR_NESTED_BE 0x00000001 /* Second bus error */
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#define ERROR_NESTED_MC 0x00000002 /* Second machine check */
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#define ERROR_TYPE 0x0000001c /* Error type */
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#define ERROR_TYPE_SHIFT 2
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#define ERROR_OFFSET 0x000001e0 /* GCache parity err word */
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#define ERROR_OFFSET_SHIFT 5
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#define ERROR_INDEX 0x001ffe00 /* GCache parity err index */
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#define ERROR_INDEX_SHIFT 9
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#define ERROR_PARITY_SET 0x00C00000 /* GCache parity err set */
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#define ERROR_PARITY_SET_SHIFT 22
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#define ERROR_SYSCMD 0xff000000 /* SysCmd<7:0> sysAD UFO */
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#define ERROR_SYSCMD_SHIFT 24
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/* TCC_ERROR -- ERROR_TYPE
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*/
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#define ERROR_SYSAD_TDB 0x00 /* sysAD data parity (TDB) */
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#define ERROR_SYSAD_TCC 0x01 /* sysAD data parity (TCC) */
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#define ERROR_SYSAD_CMD 0x02 /* sysAD commad parity */
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#define ERROR_SYSAD_UFO 0x03 /* sysAD unknown command */
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#define ERROR_GCACHE_PARITY 0x04 /* GCache data parity error */
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#define ERROR_TBUS_UFO 0x05 /* T-Bus unknown command */
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/* TCC_PARITY -- Parity Control Register
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*/
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#define PAR_TDB_EN 0x00000001 /* Enable TDB sysAD check */
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#define PAR_TCC_EN 0x00000002 /* Enable TCC sysAD check */
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#define PAR_DATA_TDB_EN 0x00000004 /* Enable TDB store check */
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#define PAR_SYSAD_PS_TCC 0x00000008 /* TCC sysad parity gen */
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#define PAR_SYSAD_PS_DB0 0x00000010 /* DB0 sysad parity gen */
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#define PAR_SYSAD_PS_DB1 0x00100000 /* DB1 sysad parity gen */
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#define PAR_SYSAD_SYND_TCC 0x000f0000 /* TCC sysad parity err byte */
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#define PAR_SYSAD_SYND_DB0 0x0000f000 /* DB0 sysad parity err byte */
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#define PAR_SYSAD_SYND_DB1 0xf0000000 /* DB1 sysad parity err byte */
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#define PAR_DATA_PS_DB0 0x00000020 /* DB0 data parity gen */
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#define PAR_DATA_PS_DB1 0x00200000 /* DB1 data parity gen */
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#define PAR_DATA_SYND_DB0 0x00000c00 /* DB0 data parity err byte */
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#define PAR_DATA_SYND_DB1 0x0c000000 /* DB1 data parity err byte */
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#define PAR_REV_DB0 0x000003c0 /* DB0 revision */
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#define PAR_REV_DB1 0x03c00000 /* DB1 revision */
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/* TCC_CAMX, TCC_PREFETCH_Y -- Prefetch CAM X, Prefetch Address Y
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*/
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#define PRE_VALID 0x00000001 /* Valid prefetch entry */
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#define PRE_ADDRESS 0xffffff80 /* Address of prefetch */
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/* TCC_PREFETCH -- Prefetch Control Register
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*/
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#define PRE_INV 0x00000001 /* Invalidate prefetch cache */
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#define PRE_TIMEOUT 0x0000001e /* Prefetch ageing control */
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#define PRE_TIMEOUT_SHIFT 1
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#define PRE_A_EN 0x00000020 /* Prefetch buffer A enable */
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#define PRE_B_EN 0x00000040 /* Prefetch buffer B enable */
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#define PRE_CAM_DEPTH 0x00000380 /* Prefetch queue depth */
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#define PRE_CAM_DEPTH_SHIFT 7
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#define PRE_A_VALID 0x00001000 /* Prefetch buffer A valid */
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#define PRE_B_VALID 0x00002000 /* Prefetch buffer B valid */
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#define PRE_CAM0_VALID 0x00010000 /* CAM buffer 0 valid */
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#define PRE_CAM1_VALID 0x00020000 /* CAM buffer 1 valid */
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#define PRE_CAM2_VALID 0x00040000 /* CAM buffer 2 valid */
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#define PRE_CAM3_VALID 0x00080000 /* CAM buffer 3 valid */
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#define PRE_CAM4_VALID 0x00100000 /* CAM buffer 4 valid */
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#define PRE_A_AGE 0x0f000000 /* Prefetch buffer A age */
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#define PRE_B_AGE 0xf0000000 /* Prefetch buffer B age */
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#define PRE_DEFAULT ((3<<PRE_TIMEOUT_SHIFT)|PRE_A_EN|PRE_B_EN|PRE_CAM_DEPTH)
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/* Tag Data
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*/
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#define GCACHE_TAG 0xfff80000 /* Valid bits of tag data */
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#define GCACHE_INDEX 0x0003ff80
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#define GCACHE_OFFSET 0x0000007f
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#define GCACHE_TAG_SHIFT 19
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#define GCACHE_INDEX_SHIFT 7
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/* Tag State
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*/
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#define GCACHE_DIRTY 0x00100000 /* Dirty bit */
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#define GCACHE_VSYN_EN 0x00200000 /* Virtual synonym enable */
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#define GCACHE_STATE_EN 0x00400000 /* State/Dirty write enable */
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#define GCACHE_STATE 0x01800000 /* GCache state bits */
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#define GCACHE_STATE_SHIFT 23
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#define GCACHE_VSYN 0x1e000000 /* Virtual synonym */
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#define GCACHE_INITSTATE (GCACHE_VSYN_EN|GCACHE_STATE_EN)
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/* Tag State -- GCACHE_STATE
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*/
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#define GCACHE_INVALID 0
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#define GCACHE_VALID 2
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/* Tag Data/State address generation
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*/
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#define TAGADDR_INDEX_SHIFT 7
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#define TAGADDR_SET_SHIFT 5
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#define tcc_tagaddr(base,index,set) \
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(base | (index << TAGADDR_INDEX_SHIFT) | (set << TAGADDR_SET_SHIFT))
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/* TCC GCache flushing
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*/
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#define TCC_INDEX_OP 0x00000004 /* Index/Hit operation */
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#define TCC_DIRTY_WB 0x00000008 /* Dirty Writeback enable */
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#define TCC_INVALIDATE 0x00000010 /* Invalidate Enable */
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#define TCC_CACHE_SET 0x00000060 /* Cache set for index ops */
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#define TCC_CACHE_SET_SHIFT 5
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#define TCC_CACHE_INDEX 0x0007ff80 /* Cache index for index ops */
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#define TCC_CACHE_INDEX_SHIFT 7
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#define TCC_PHYSADDR 0x7fffff80 /* Physical address */
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#define TCC_CACHE_OP 0x100000000 /* Flag load as cache op */
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#define TCC_LINESIZE 128 /* IP26 GCache line size */
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#define CACHE_SLINE_SIZE TCC_LINESIZE /* compat with other cpus */
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/* Undefined TCC registers used clear the TFP Store Address Queue.
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*/
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#define SAQ_INIT_ADDRESS 0x18180000
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#define SAQ_DEPTH 32
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#define OSPL_SPDBG 0x0080 /* undefined in TFP SR */
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/* Defines to make uncached processor ordered access easier. Stores
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* to this mode go through the TCC fifo, which is primarily used for
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* graphics. Hence we call it KG, or 'kernel graphics' space.
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*
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* When mapping with the TLB we should use TLBLO_UNC_PROCORD.
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*/
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#define KGBASE 0x8000000000000000
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#define KG_TO_K1(x) PHYS_TO_K1(x)
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#define KG_TO_PHYS(x) KDM_TO_PHYS(x)
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#if _LANGUAGE_ASSEMBLY
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#define PHYS_TO_KG(x) ((x) | KGBASE)
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#define K1_TO_KG(x) PHYS_TO_KG((x) & TO_PHYS_MASK)
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#else
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#define PHYS_TO_KG(x) ((__psunsigned_t)(x) | KGBASE)
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#define K1_TO_KG(x) PHYS_TO_KG((__psunsigned_t)(x) & TO_PHYS_MASK)
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#endif
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/* Additional VECTOR_ defines for setlclvector() for the TCC managed
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* interrupts.
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*/
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#define VECTOR_TCCHW 1000 /* TCC fifo High Water */
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#define VECTOR_TCCLW 1001 /* TCC fifo Low Water */
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/* Prototypes for IP26 specific routines.
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*/
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#if _LANGUAGE_C
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void settccfifos(int lw, int hw);
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void enabletccintrs(int mask);
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void cleartccintrs(int mask);
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long tune_tcc_gcache(void); /* internal */
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#endif
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#if _STANDALONE
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#if LANGUAGE_ASSEMBLY
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/* The IP26 PROM uses some of the TFP misc CP0 registers.
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*/
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#define TETON_BEV C0_WORK0 /* early handler ptr */
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#define TETON_GERROR C0_WORK1 /* early GCache err count */
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#endif
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#define GERROR_PARITY 0x000000000000ffff
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#define GERROR_TAG 0x00000000ffff0000
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#define GERROR_DATA 0x0000ffff00000000
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#define GERROR_SET0 0x1000000000000000
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#define GERROR_SET1 0x2000000000000000
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#define GERROR_SET2 0x4000000000000000
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#define GERROR_SET3 0x8000000000000000
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#define GERROR_MAXPONERR 50
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#define GERROR_TAG_SHIFT 16
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#define GERROR_DATA_SHIFT 32
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#define GERROR_SET_SHIFT 60
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/* Base PROM SR settings. Most of prom runs with SR_IBIT4 (for soft power)
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* enabled as well.
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*/
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#define SR_PROMBASE SR_CU0|SR_CU1|SR_FR|SR_PAGESIZE|SR_IE|SR_IBIT7|SR_IBIT9|SR_IBIT10
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#endif /* _STANDALONE */
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#endif /* __SYS_IP26_H__ */
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