364 lines
11 KiB
C
364 lines
11 KiB
C
#ifndef __SYS_IP32_H__
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#define __SYS_IP32_H__
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#define _ARCSPROM
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#ifdef _STANDALONE
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#include <sys/mips_addrspace.h>
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#endif
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#include <sys/crime.h>
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#include <sys/mace.h>
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#define SPLMIN 0
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#define SPLMAX 5
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/*
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* Symbolic constants for use w/setcrimevector()
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*/
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#define VICE_CPU_INTR 31
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#define MEMERR_INTR 21
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#define CRMERR_INTR 20
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#define SOFT_INTR(x) (28 + (x)) /* x = 0 - 2 */
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#define RE_INTR(x) (22 + (x)) /* x = 0 - 5 */
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#define GBE_INTR(x) (16 + (x)) /* x = 0 - 3 */
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#define MACE_INTR(x) (x) /* x = 0 - 15 */
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#define SPL0 0 /* spl0() */
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#define SPL1 1 /* spl1() */
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#define SPL3 1 /* splnet(), spl3() */
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#define SPL5 1 /* spltty(), spl5() */
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#define SPLHINTR 1 /* splhintr(), splgio2() */
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#define SPL6 1 /* splhi(), spl6() */
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#define SPL65 2 /* splprof(), spl65() */
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#define SPL7 3 /* spl7() */
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#define SPLECC 4 /* splecc() */
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#define CRM_EXCL 0x1 /* no ganged intrs here */
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#define CRM_CHKSTAT 0x2 /* check interrupt status */
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/* before calling handler */
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#define CRM_DRVENB 0x4 /* driver enables CRIME intr */
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#define TLBLO_HWBITS 0x0fffffff /* 22 bit ppn, plus CDVG */
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#define TLBLO_PFNTOKDMSHFT 4 /* tlblo pfn to direct mapped */
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#define TLBLO_HWBITSHIFT 4 /* A shift value for masking */
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#define PHYS_RAMBASE 0x00000000 /* base addr for 256Mb space */
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#define LINEAR_BASE 0x40000000
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#define SEG0_BASE 0x00000000 /* can be mapped to k0/k1 */
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#define SEG0_SIZE 0x10000000
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#define SEG1_BASE (LINEAR_BASE+SEG0_SIZE)
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/* cannot be mapped to k0/k1 */
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/* address skips over 256Mb */
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/* double mapped at 0x0 */
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#define MINMEMSIZE 0x2000000 /* 32Mb, min mem config */
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#define K0_RAMBASE PHYS_TO_K0(PHYS_RAMBASE)
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#define K1_RAMBASE PHYS_TO_K1(PHYS_RAMBASE)
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#define PHYS_TO_K0_RAM(x) PHYS_TO_K0((x)+K0_RAMBASE)
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#define PHYS_TO_K1_RAM(x) PHYS_TO_K1((x)+K1_RAMBASE)
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#define SYMMON_STACK PHYS_TO_K0_RAM(0x6000)
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#define SYMMON_STACK_ADDR(x) SYMMON_STACK
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#if _MIPS_SIM == _ABI64
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#define SYMMON_STACK_SIZE 0x2000
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#else
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#define SYMMON_STACK_SIZE 0x1000
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#endif
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#define RESTART_ADDR PHYS_TO_K0_RAM(0x400)
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#define ECCBYPASS_BASE 0x80000000 /* ECC-bypass memory alias */
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#ifndef _STANDALONE
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#include <sys/IP32flash.h>
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#endif
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#ifdef _LANGUAGE_C
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#define RT_CLOCK_ADDR \
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(struct ds17287_clk *)PHYS_TO_K1(ISA_RTC_BASE+7)
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#else
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#define RT_CLOCK_ADDR PHYS_TO_K1(ISA_RTC_BASE+7)
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#endif
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#define RT_RAM_FLAGS 0x0
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#define RT_FLAGS_INVALID 0x1
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#define RT_RAM_BASE 0x1 /* offset for general r/w nvram */
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#if 0
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#define PROM_RAMBASE PHYS_TO_K0_RAM(0x400000)
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#define PROM_STACK PHYS_TO_K1_RAM(0x800000)
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#define PROM_TILE_BASE PHYS_TO_K1_RAM(0x500000)
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#define PROM_TILE_CNT 21
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#else
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#define PROM_RAMBASE PHYS_TO_K0_RAM(0x1000000)
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#define PROM_STACK PHYS_TO_K1_RAM(0x1400000)
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#define PROM_TILE_BASE PHYS_TO_K1_RAM(0x1100000)
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#define PROM_TILE_CNT 21
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#endif
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/*
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* RTC configuration data.
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*/
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#define RTC_BASE PHYS_TO_K1(ISA_RTC_BASE+7)
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/*
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* Firmware RTC_NVRAM constants
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*/
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#define RTC_SAVE_UST 37 /* Saved UST value */
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#define RTC_SAVE_REG 41 /* Beginning of 8 byte register save area */
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#define RTC_RESET_CTR 49 /* Firmware reset counter byte */
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/*
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* IP32 Serial port configuration data
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*/
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#define N16550PORTS 2 /* Number of 16550 serial ports */
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#define SERIAL_PORT0_BASE PHYS_TO_K1(ISA_SER1_BASE + 7)
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#define SERIAL_PORT1_BASE PHYS_TO_K1(ISA_SER2_BASE + 7)
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#define SERIAL_CLOCK_FREQ (1843200)
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#if 0
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/*
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* Flash memory parameters
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*/
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#define FLASH_BASE 0x1fc00000
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#define FLASH_PAGE_SIZE 0x200
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#define FLASH_PROTECTED 0x4000 /* Size of protected segment */
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#define FLASH_SIZE (512*1024)
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#define FLASH_PROGRAMABLE (FLASH_BASE+FLASH_PROTECTED)
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#endif
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/*
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* Ethernet configuration data
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*/
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#define MAC110_BASE PHYS_TO_K1(MACE_ENET)
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/*
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* Firmware dispatch codes
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*
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* NOTE: Probably shouldn't be here.
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*/
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#define FW_HARD_RESET 0 /* Power on or hard reset*/
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#define FW_SOFT_RESET 1 /* Soft reset or NMI */
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#define FW_EIM 2 /* Enter Interactive Mode */
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#define FW_HALT 3 /* Halt */
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#define FW_POWERDOWN 4 /* Power down */
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#define FW_RESTART 5 /* Restart */
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#define FW_REBOOT 6 /* Reboot */
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#define FW_INIT 7 /* fw init callback */
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#ifdef LANGUAGE_C
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/* chip interface structure for IP22 / HPC / WD33C93 */
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typedef struct scuzzy {
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volatile unsigned char *d_addr; /* address register */
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volatile unsigned char *d_data; /* data register */
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volatile unsigned long *d_ctrl; /* control address */
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volatile unsigned long *d_bcnt; /* byte count register */
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volatile unsigned long *d_curbp; /* current buffer pointer */
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volatile unsigned long *d_nextbp; /* next buffer pointer */
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volatile unsigned long *d_dmacfg; /* fifo pointer register */
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volatile unsigned long *d_piocfg; /* fifo data register */
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unsigned char d_initflags; /* initial flags for d_flags */
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} scuzzy_t;
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#endif
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/* Location of the eframe and stack for the ecc handler.
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* Since the R4000 'replaces' KUSEG with an unmapped, uncached space
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* corresponding to physical memory when a cache error occurs, these are
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* the actual addresses used.
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*/
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#if R4000
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#define CACHE_ERR_EFRAME (0x1000 - EF_SIZE)
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#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME - ECCF_SIZE)
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/* 4 arguments on the stack. */
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#define CACHE_ERR_SP (CACHE_ERR_ECCFRAME - 4 * sizeof(long))
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#else
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/* scratch area and ptr to ECC frame/stack */
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#define CACHE_ERR_K1_SAVE 0x0ff8
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#define CACHE_ERR_FRAMEPTR 0x0ff0
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#define ECC_SCRATCH_LINE 0x0f00
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#endif
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/*
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* ECC error handler defines.
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* Define an additional exception frame for the ECC handler.
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* Save 3 more registers on this frame: C0_CACHE_ERR, C0_TAGLO,
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* and C0_ECC.
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* Call this an ECCF_FRAME.
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*/
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#define ECCF_CACHE_ERR 0
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#define ECCF_TAGLO 1
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#define ECCF_ECC 2
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#define ECCF_ERROREPC 3
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#define ECCF_PADDRHI 4 /* because CPU bus error address is 34 bits */
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#define ECCF_PADDR 5
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#define ECCF_CES_DATA 6
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#define ECCF_CPU_ERR_STAT 7
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#define ECCF_MEM_ERR_STAT 8
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#define ECCF_CPU_ERR_ADDRHI 9 /* CPU bus error address is 34 bits */
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#define ECCF_CPU_ERR_ADDR 10
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#define ECCF_MEM_ERR_ADDR 11
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#define ECCF_SIZE (12 * sizeof(long))
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#define MAXCPU 1
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#define CAUSE_BERRINTR 0x100000 /* bit 20 of CRM_INTSTAT */
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#define EGUN_PHYS 1 /* bad ecc to phys address */
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#define EGUN_PHYS_WORD 2 /* bad ecc at memory word offset */
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#define EGUN_PROCVIRT 3 /* bad ecc in proc virtual address */
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#ifdef LANGUAGE_C
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struct egun_cmd {
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unsigned long addr;
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int ecc_repl;
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pid_t pid;
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};
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#endif /* LANGUAGE_C */
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#ifndef STANDALONE
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#if _SYSTEM_SIMULATION
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#include <sys/MHSIM.h>
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#endif
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#endif
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#ifdef LANGUAGE_C
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#define MAXNVNAMELEN 32
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/* format used to store nvram table information
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*/
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struct nvram_entry {
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char nt_name[MAXNVNAMELEN]; /* string name of entry */
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char *nt_value; /* current value of entry */
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};
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/* function prototypes for IP32 functions */
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typedef void (*intvec_func_t)(eframe_t *, __psint_t);
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/* IP32 specific functions */
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#ifndef _STANDALONE
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/*
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* Routines defined within 'mace.c', the MACE driver.
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*/
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extern int setcrimevector(int, int, intvec_func_t, __psint_t, short);
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extern int unsetcrimevector(int, intvec_func_t);
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extern void crime_intr_enable(int);
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extern void crime_intr_disable(int);
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typedef __uint64_t _macereg_t;
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extern void setmaceisavector(int intr, _macereg_t macebits, intvec_func_t isr);
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extern void unsetmaceisavector(int intr, _macereg_t macebits);
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extern void mace_mask_write(_macereg_t m_mask);
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extern _macereg_t mace_mask_read();
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extern void mace_mask_enable(_macereg_t driver_mask);
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extern void mace_mask_disable(_macereg_t driver_mask);
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extern void mace_mask_update(_macereg_t driver_mask,
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_macereg_t current_mask);
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/* End of routines defined within 'mace.c' */
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extern paddr_t get_isa_dma_buf_addr(void);
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extern void isa_dma_buf_init(void);
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extern int splint(int);
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extern int splhintr(void);
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extern void set_autopoweron(void);
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extern void scrub_memory(caddr_t);
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extern int addr_to_bank(paddr_t);
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extern int vice_err(_crmreg_t, _crmreg_t);
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extern int bank_size(_crmreg_t);
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extern void load_nvram_tab(void);
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extern unsigned char *etoh(char *);
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extern void flash_write_env(void);
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#ifdef TILES_TO_LPAGES
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extern int splretr(void);
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#endif /* TILES_TO_LPAGES */
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/* from ml/ust_conv.c - use to fill in high 32 bits for 64-bit nanotime */
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extern void fill_ust_highbits(unsigned int mace32, unsigned long long *mace64);
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/* stuff which should be in a different header file (sys/ecc.h?) */
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extern int _r4600sc_disable_scache(void);
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extern void _r4600sc_enable_scache(void);
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extern int _read_tag(int, caddr_t, int *);
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extern int tlb_to_phys(k_machreg_t , paddr_t *, int *);
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extern unsigned int r_phys_word(paddr_t);
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extern unsigned int r_phys_word_erl(paddr_t);
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extern int ecc_same_cache_block(int,paddr_t,paddr_t);
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extern int decode_inst(eframe_t *, int, int *, k_machreg_t *, int *);
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extern int ecc_meminit(pfn_t, pfn_t);
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extern void ecc_enable(void);
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extern void ecc_disable(void);
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extern pfn_t last_phys_pfn(void);
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extern int ecc_meminited; /* amount of memory cleared by ecc_meminit */
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extern void early_mte_zero(paddr_t, size_t);
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#endif
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#if (_MIPS_ISA == 3 || _MIPS_ISA == 4)
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#define WRITE_REG64(val, addr, type) \
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(*(volatile uint64_t *)(addr) = (val))
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#else
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#define WRITE_REG64(val, addr, type) \
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write_reg64((long long)(val), (__psunsigned_t)(addr))
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#endif /* _MIPS_ISA == 3 or 4 */
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#if (_MIPS_ISA == 3 || _MIPS_ISA == 4)
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#define READ_REG64(addr, type) \
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((type)(*(volatile long long *)(addr)))
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#else
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#define READ_REG64(addr, type) \
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((type)read_reg64((__psunsigned_t)(addr)))
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#endif /* _MIPS_ISA == 3 or 4 */
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#define REG_RDANDWR8(_a, _m) pciio_pio_write8(pciio_pio_read8((_a))&(_m),(_a))
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#define REG_RDORWR8(_a, _m) pciio_pio_write8(pciio_pio_read8((_a))|(_m),(_a))
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/* Defines for CRIME Texture TLB */
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#define CRM_TEX_MAX_RESIDENT 128 /* Max. # of loadable tex. MipMaps */
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#define CRM_TEX_TLB_SIZE 28 /* Texture TLB size */
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#define CRM_TEX_FIFOMAX 24 /* High level for fast tex. loads */
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#define CRM_TEX_FIFOSRL 18 /* FIFO level shift right count */
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#define CRM_TEX_FIFOMASK 0x7f /* FIFO level mask */
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#define CRM_TEX_IBSTAT_ADDR 0xb5004000 /* Address of IB status */
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#define CRM_TEX_TLB_FIRST_ADDR 0xb5001600 /* Address of 1st TLB entry */
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#define CRM_TEX_TLB_LAST_ADDR 0xb50016d8 /* Address of last TLB entry */
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struct CrmTexTlb {
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long long tlbAddr;
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union {
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u_short taddr[4];
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u_long laddr[2];
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long long dw;
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}tlbData;
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};
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#ifdef MH_R10000_SPECULATION_WAR
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/*
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* Kernel vaddr where extk0 is mapped ... this is aligned to make
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* the mapping starting at (SMALLMEM_K0_R10000_PFNMAX+1), so the
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* area can be mapped with big ptes (see extk0_avail_alloc).
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*/
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#define EXTK0_OFFSET 0x1800000
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#define EXTK0_BASE (K2BASE + EXTK0_OFFSET)
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#endif /* MH_R10000_SPECULATION_WAR */
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#endif /* LANGUAGE_C */
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#ifdef R10000
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/* scratch area and ptr to ECC frame/stack */
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#define CACHE_TMP_EMASK 0x3e00
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#define CACHE_TMP_EFRAME1 0x0c00
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#define CACHE_TMP_EFRAME2 0x0e00
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#endif /* R10000 */
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#endif /* __SYS_IP32_H__ */
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