306 lines
10 KiB
C
306 lines
10 KiB
C
/**************************************************************************
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* *
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* Copyright (C) 1992, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ident "sys/IPMHSIM.h: $Revision: 1.2 $"
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/*
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* IPMHSIM.h -- cpu board specific defines for IPMHSIM
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*
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* The IP22 is equipped with an R4000, MC, HPC3, and INT2 chip. HPC3 and MC
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* definitions are contained in header files that are included here.
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*
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* The IP24 cpu board is architecturally the same as the IP22 with the
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* following exceptions:
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* 1. Uses an IOC1 chip containing the following parts:
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* INT3 - replaces INT2
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* VTI85CX30 - replaces Z85230
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* VTI8042 - replaces Intel 8242
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* 2. Sys_ID register identifies IP24 cpu board and ioc1 presence.
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* 3. Other register name and offset changes as noted in this file and
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* sys/hpc3.h.
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*/
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#ifndef __SYS_IPMHSIM_H__
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#define __SYS_IPMHSIM_H__
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#define LIO_0_MASK_ADDR 0x1fbd9000 /* Local IO register 0 mask (b) */
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#define LIO_1_MASK_ADDR 0x1fbd9010 /* Local IO register 1 mask (b) */
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#define LIO_0_ISR_ADDR 0x1fbd9100 /* Local IO interrupt status (b,ro) */
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#define LIO_1_ISR_ADDR 0x1fbd9110 /* Local IO interrupt status (b,ro) */
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/* LIO 0 status bits */
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#define LIO_FIFO 0x01 /* FIFO full / GIO-0 interrupt */
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#define LIO_SCSI_0 0x02 /* SCSI controller 0 interrupt */
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#define LIO_SCSI_1 0x04 /* SCSI controller 1 interrupt */
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#define LIO_CENTR 0x20 /* Parallel port interrupt */
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#define LIO_GIO_1 0x40 /* IP22: GE/GIO-1/2nd-HPC interrupt */
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#define LIO_LIO2 0x80 /* LIO2 interrupt */
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/* LIO 1 status bits */
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#define LIO_LIO3 0x08 /* LIO3 interrupt */
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#define LIO_HPC3 0x10 /* HPC3 interrupt */
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#define LIO_AC 0x20 /* ACFAIL interrupt */
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/* Mapped LIO interrupts. These interrupts may be mapped to either 0, or 1 */
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#define LIO_PASSWD 0x02 /* Pasword checking enable */
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#define LIO_KEYBD_MOUSE 0x10 /* Keyboard/Mouse interrupt */
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#define LIO_DUART 0x20 /* Duart interrupt */
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/* LIO 0 mask bits */
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#define LIO_FIFO_MASK 0x01 /* FIFO full/GIO-0 interrupt mask */
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#define LIO_SCSI_0_MASK 0x02 /* SCSI 0 interrupt mask */
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#define LIO_SCSI_1_MASK 0x04 /* SCSI 1 interrupt mask */
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#define LIO_LIO2_MASK 0x80 /* LIO2 interrupt mask */
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/* LIO 1 mask bits */
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#define LIO_MASK_BIT0_UNUSED 0x01 /* IP22: Unused */
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#define LIO_MASK_BIT2_UNUSED 0x04 /* IP22: Unused */
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#define LIO_LIO3_MASK 0x08 /* LIO3 interrupt */
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#define LIO_HPC3_MASK 0x10 /* HPC3 interrupt */
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/* Mapped interrupt mask bits */
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#define LIO_DUART_MASK 0x20 /* Duart interrupts mask*/
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/* Local I/O vector numbers for setlclvector().
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* - local 1 starts at 8
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* - local 2 starts at 16 (VME register)
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*/
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#define VECTOR_SCSI 1
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#define VECTOR_SCSI1 2
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#define VECTOR_DUART 3
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#define VECTOR_GDMA 4 /* mc dma complete */
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#define VECTOR_LCL2 7
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#define VECTOR_LCL3 11
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#define VECTOR_HPCDMA 12
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#define VECTOR_KBDMS 20
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#define VECTOR_DRAIN0 22 /* IP22: fifo not full */
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#define VECTOR_DRAIN1 23 /* IP22: fifo not full */
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/* clear timer 2 bits (ws) */
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#define TIMER_ACK_ADDR PHYS_TO_K1(0x1fbb0000)
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#define ACK_TIMER0 0x1 /* write strobe to clear timer 0 */
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#define ACK_TIMER1 0x2 /* write strobe to clear timer 1 */
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/* wd33c93 chip registers accessed through HPC3 */
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#define MHSIM_CPU_FREQ 240
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#define RESTART_ADDR PHYS_TO_K0(0x400)
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/*
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* MHSIM I/O Registers
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*/
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#define MHSIM_SCSI0A_ADDR PHYS_TO_K1(0x1fbc0000)
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#define MHSIM_SCSI0D_ADDR PHYS_TO_K1(0x1fbc8000)
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#define MHSIM_DUART1B_DATA PHYS_TO_K1(0x1fbd0000)
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#define MHSIM_DUART_INTR_ENBL_ADDR PHYS_TO_K1(0x1fbd0010)
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#define MHSIM_DUART_INTR_STATE_ADDR PHYS_TO_K1(0x1fbd0020)
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#define MHSIM_DUART_SYNC_WR_ADDR PHYS_TO_K1(0x1fbd0030)
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#define MHSIM_DUART_RX_INTR_STATE 0x1
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#define MHSIM_DUART_TX_INTR_STATE 0x2
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#define MHSIM_GETTIMEOFDAY_ADDR PHYS_TO_K1(0x1fbe0000)
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#define MHSIM_MEMSIZE_ADDR PHYS_TO_K1(0x1fbe0010)
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#define MHSIM_SC_SIZE_ADDR PHYS_TO_K1(0x1fa00056)
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/*
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* Support for MHSIM's version of Sabledsk
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*/
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#define MHSIM_DISK_MAX_TRANSFER_SIZE (1000 * 1024)
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#define MHSIM_DISK_DATA PHYS_TO_K1(0x1f100000)
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#define MHSIM_DISK_DISKNUM PHYS_TO_K1(0x1fbf0000)
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#define MHSIM_DISK_SECTORNUM PHYS_TO_K1(0x1fbf0010)
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#define MHSIM_DISK_SECTORCOUNT PHYS_TO_K1(0x1fbf0020)
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#define MHSIM_DISK_STATUS PHYS_TO_K1(0x1fbf0030)
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#define MHSIM_DISK_BYTES_TRANSFERRED PHYS_TO_K1(0x1fbf0040)
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#define MHSIM_DISK_PROBE_UNIT PHYS_TO_K1(0x1fbf0050)
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#define MHSIM_DISK_SIZE PHYS_TO_K1(0x1fbf0060)
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#define MHSIM_DISK_OPERATION PHYS_TO_K1(0x1fbf0070)
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#define MHSIM_DISK_NOP 0x0
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#define MHSIM_DISK_READ 0x1
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#define MHSIM_DISK_WRITE 0x2
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#define MHSIM_DISK_PROBE 0x3
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/*
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* Relevant portion of mc.h
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*/
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#define CAUSE_BERRINTR CAUSE_IP7 /* bus error interrupt */
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#define CPU_ERR_STAT 0x1fa000ec
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#define GIO_ERR_STAT 0x1fa000fc
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#define CPU_ERR_ADDR 0x1fa000e4
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#define GIO_ERR_ADDR 0x1fa000f4
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#define CPUCTRL0 0x1fa00004
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#define CPUCTRL0_R4K_CHK_PAR_N 0x04000000 /* R4000 not to check parity
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/* CPU error status, CPU_ERR_STAT */
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#define CPU_ERR_STAT_RD 0x00000100 /* read parity error */
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#define CPU_ERR_STAT_PAR 0x00000200 /* CPU parity error */
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#define CPU_ERR_STAT_ADDR 0x00000400 /* memory bus error. bad
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address */
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#define CPU_ERR_STAT_SYSAD_PAR 0x00000800 /* sysad parity error */
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#define CPU_ERR_STAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */
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#define CPU_ERR_STAT_BAD_DATA 0x00002000 /* bad data identifier */
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#define CPU_ERR_STAT_PAR_MASK 0x00001f00 /* parity error mask */
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#define CPU_ERR_STAT_RD_PAR (CPU_ERR_STAT_RD | CPU_ERR_STAT_PAR)
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#define ERR_STAT_B0 0x00000001
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#define ERR_STAT_B1 0x00000002
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#define ERR_STAT_B2 0x00000004
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#define ERR_STAT_B3 0x00000008
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#define ERR_STAT_B4 0x00000010
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#define ERR_STAT_B5 0x00000020
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#define ERR_STAT_B6 0x00000040
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#define ERR_STAT_B7 0x00000080
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/*
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* Mode argument to perr_save_info()
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*/
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#define PERC_CACHE_SYSAD 0 /* cache exception, from SysAD */
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#define PERC_CACHE_LOCAL 1 /* cache exception, from cache */
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/* (may be due to late detection of */
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/* a SysAD error) */
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#define PERC_IBE_EXCEPTION 2 /* Instruction fetch bus error exception */
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#define PERC_DBE_EXCEPTION 3 /* Data fetch bus error exception */
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#define PERC_BE_INTERRUPT 4 /* MC bus error interrupt */
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/*
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* ECC error handler defines.
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* Define an additional exception frame for the ECC handler.
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* Save 3 more registers on this frame: C0_CACHE_ERR, C0_TAGLO,
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* and C0_ECC.
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* Call this an ECCF_FRAME.
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*/
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#define ECCF_CACHE_ERR 0
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#define ECCF_TAGLO 1
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#define ECCF_ECC 2
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#define ECCF_ERROREPC 3
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#define ECCF_PADDR 4
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#define ECCF_CES_DATA 5
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#ifndef _MEM_PARITY_WAR
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#define ECCF_SIZE (6 * sizeof(k_machreg_t))
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#else /* _MEM_PARITY_WAR */
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#define ECCF_STACK_BASE 6
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#define ECCF_BUSY 7
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#define ECCF_ECCINFO 8
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#define ECCF_SECOND_PHASE 9
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#define ECCF_CPU_ERR_STAT 10
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#define ECCF_CPU_ERR_ADDR 11
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#define ECCF_GIO_ERR_STAT 12
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#define ECCF_GIO_ERR_ADDR 13
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#define ECCF_SIZE (14 * sizeof(k_machreg_t))
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#endif /* _MEM_PARITY_WAR */
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/* Location of the eframe and stack for the ecc handler.
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* Since the R4000 'replaces' KUSEG with an unmapped, uncached space
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* corresponding to physical memory when a cache error occurs, these are
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* the actual addresses used.
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*/
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#define CACHE_ERR_EFRAME (0x1000 - EF_SIZE)
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#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME - ECCF_SIZE)
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#ifdef _MEM_PARITY_WAR
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#define ECCF_ADDR(x) (CACHE_ERR_ECCFRAME + ((x) * 4))
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/* pointer to top of cache error exception stack */
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#define CACHE_ERR_STACK_BASE ECCF_ADDR(ECCF_STACK_BASE)
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#define CACHE_ERR_STACK_BASE_P (*((long *) PHYS_TO_K1(CACHE_ERR_STACK_BASE)))
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#define CACHE_ERR_STACK_SIZE (1 * NBPP)
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/* pointer to cache error log structure */
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#define CACHE_ERR_ECCINFO ECCF_ADDR(ECCF_ECCINFO)
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#define CACHE_ERR_ECCINFO_P (*((long *) PHYS_TO_K1(CACHE_ERR_ECCINFO)))
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#endif /* _MEM_PARITY_WAR */
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#define CACHE_ERR_CES_DATA ECCF_ADDR(ECCF_CES_DATA)
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#define CACHE_ERR_CES_DATA_P (*((long *) PHYS_TO_K1(CACHE_ERR_CES_DATA)))
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/* 4 arguments on the stack. */
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#define CACHE_ERR_SP (CACHE_ERR_ECCFRAME - 4 * sizeof(int))
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/* Mask to remove SW bits from pte. Note that the high-order
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* address bits are overloaded with SW bits, which limits the
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* physical addresses to 32 bits
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*/
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#define TLBLO_HWBITS 0x03ffffff /* 20 bit ppn, plus CDVG */
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#define TLBLO_HWBITSHIFT 6 /* A shift value, for masking */
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#define TLBLO_PFNTOKDMSHFT 6 /* tlblo pfn to direct mapped */
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#ifdef LANGUAGE_C
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/* chip interface structure for IP22 / HPC / WD33C93 */
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typedef struct scuzzy {
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volatile unsigned char *d_addr; /* address register */
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volatile unsigned char *d_data; /* data register */
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unsigned char d_vector; /* hardware interrupt vector */
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} scuzzy_t;
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/* Map up to 256Kb per transfer. This is sufficient
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* for almost all disk and tape acesses. Things like scanners or
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* printers often transfer far more than a Mb per cmd, so they will
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* have to re-map anyway, no matter how many we allocate.
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*/
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#define NSCSI_DMA_PGS 64
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/* this saves a lot of hard to read and type code in various places,
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and also ensures that we get the register size correct */
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#define K1_LIO_0_MASK_ADDR ((volatile unchar *)PHYS_TO_K1(LIO_0_MASK_ADDR))
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#define K1_LIO_1_MASK_ADDR ((volatile unchar *)PHYS_TO_K1(LIO_1_MASK_ADDR))
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#define K1_LIO_2_MASK_ADDR ((volatile unchar *)PHYS_TO_K1(LIO_2_MASK_ADDR))
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#define K1_LIO_0_ISR_ADDR ((volatile unchar *)PHYS_TO_K1(LIO_0_ISR_ADDR))
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#define K1_LIO_1_ISR_ADDR ((volatile unchar *)PHYS_TO_K1(LIO_1_ISR_ADDR))
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#define K1_LIO_2_ISR_ADDR ((volatile unchar *)PHYS_TO_K1(LIO_2_3_ISR_ADDR))
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#define PHYS_RAMBASE 0x00000000
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#define K0_RAMBASE PHYS_TO_K0(PHYS_RAMBASE)
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/* function prototypes for IP22 functions */
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extern int spl1(void);
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extern int splnet(void);
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extern int spl3(void);
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extern int spllintr(void);
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extern int splhintr(void);
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extern int splretr(void);
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struct eframe_s;
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extern void setlclvector(int, void (*)(int,struct eframe_s *), int);
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extern void setgiovector(int, int, void (*)(int, struct eframe_s *), int);
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extern void setgioconfig(int, int);
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extern void sethpcdmaintr(int, void (*)(int,struct eframe_s *), int);
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extern void hpcdma_intr(int, struct eframe_s *);
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extern int is_fullhouse(void), board_rev(void);
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#endif /* LANGUAGE_C */
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#ifdef _STANDALONE
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#if _MIPS_SIM == _ABI64
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#define SR_PROMBASE SR_CU0|SR_CU1|SR_KX
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#else
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#define SR_PROMBASE SR_CU0|SR_CU1
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#endif
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#endif /* _STANDALONE */
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#endif /* __SYS_IPMHSIM_H__ */
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