359 lines
11 KiB
C
359 lines
11 KiB
C
/**************************************************************************
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* *
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* Copyright (C) 1990-1993, Silicon Graphics, Inc *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ifndef __PCI_PCIBR_H__
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#define __PCI_PCIBR_H__
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#ident "sys/RACER/pcibr.h: $Revision: 1.38 $"
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#include <sys/types.h>
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#include <sys/cpu.h>
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#include <sys/systm.h>
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#include <sys/cmn_err.h>
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#include <sys/buf.h>
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#include <sys/ioctl.h>
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#include <sys/invent.h>
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#include <sys/debug.h>
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#include <sys/sbd.h>
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#include <sys/kmem.h>
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#include <sys/edt.h>
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#include <sys/dmamap.h>
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#include <sys/hwgraph.h>
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#include <sys/iobus.h>
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#include <sys/iograph.h>
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#include <sys/param.h>
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#include <sys/pio.h>
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#include <sys/sema.h>
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#include <sys/pda.h>
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#include <sys/PCI/pciio.h>
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#include <sys/PCI/bridge.h>
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/* =====================================================================
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* symbolic constants used by pcibr's xtalk bus provider
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*/
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#define PCIBR_PIOMAP_BUSY 0x80000000
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#define PCIBR_DMAMAP_BUSY 0x80000000
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#define PCIBR_DMAMAP_SSRAM 0x40000000
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#define PCIBR_INTR_BLOCKED 0x40000000
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#define PCIBR_INTR_BUSY 0x80000000
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#if LANGUAGE_C
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/* =====================================================================
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* opaque types used by pcibr's xtalk bus provider
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*/
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typedef struct pcibr_piomap_s *pcibr_piomap_t;
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typedef struct pcibr_dmamap_s *pcibr_dmamap_t;
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typedef struct pcibr_intr_s *pcibr_intr_t;
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/* =====================================================================
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* primary entry points: Bridge (pcibr) device driver
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*
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* These functions are normal device driver entry points
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* and are called along with the similar entry points from
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* other device drivers. They are included here as documentation
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* of their existance and purpose.
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*
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* pcibr_init() is called to inform us that there is a pcibr driver
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* configured into the kernel; it is responsible for registering
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* as a crosstalk widget and providing a routine to be called
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* when a widget with the proper part number is observed.
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*
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* pcibr_attach() is called for each vertex in the hardware graph
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* corresponding to a crosstalk widget with the manufacturer
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* code and part number registered by pcibr_init().
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*/
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extern void pcibr_init(void);
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extern int pcibr_attach(vertex_hdl_t);
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/* =====================================================================
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* bus provider function table
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*
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* Normally, this table is only handed off explicitly
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* during provider initialization, and the PCI generic
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* layer will stash a pointer to it in the vertex; however,
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* exporting it explicitly enables a performance hack in
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* the generic PCI provider where if we know at compile
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* time that the only possible PCI provider is a
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* pcibr, we can go directly to this ops table.
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*/
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extern pciio_provider_t pcibr_provider;
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/* =====================================================================
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* secondary entry points: pcibr PCI bus provider
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*
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* These functions are normally exported explicitly by
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* a direct call from the pcibr initialization routine
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* into the generic crosstalk provider; they are included
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* here to enable a more aggressive performance hack in
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* the generic crosstalk layer, where if we know that the
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* only possible crosstalk provider is pcibr, and we can
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* guarantee that all entry points are properly named, and
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* we can deal with the implicit casting properly, then
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* we can turn many of the generic provider routines into
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* plain brances, or even eliminate them (given sufficient
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* smarts on the part of the compilation system).
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*/
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extern pcibr_piomap_t pcibr_piomap_alloc(vertex_hdl_t dev,
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device_desc_t dev_desc,
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pciio_space_t space,
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iopaddr_t pci_addr,
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size_t byte_count,
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size_t byte_count_max,
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unsigned flags);
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extern void pcibr_piomap_free(pcibr_piomap_t piomap);
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extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap,
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iopaddr_t xtalk_addr,
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size_t byte_count);
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extern void pcibr_piomap_done(pcibr_piomap_t piomap);
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extern caddr_t pcibr_piotrans_addr(vertex_hdl_t dev,
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device_desc_t dev_desc,
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pciio_space_t space,
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iopaddr_t pci_addr,
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size_t byte_count,
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unsigned flags);
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extern iopaddr_t pcibr_piospace_alloc(vertex_hdl_t dev,
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device_desc_t dev_desc,
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pciio_space_t space,
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size_t byte_count,
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size_t alignment);
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extern void pcibr_piospace_free(vertex_hdl_t dev,
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pciio_space_t space,
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iopaddr_t pciaddr,
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size_t byte_count);
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extern pcibr_dmamap_t pcibr_dmamap_alloc(vertex_hdl_t dev,
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device_desc_t dev_desc,
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size_t byte_count_max,
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unsigned flags);
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extern void pcibr_dmamap_free(pcibr_dmamap_t dmamap);
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extern iopaddr_t pcibr_dmamap_addr(pcibr_dmamap_t dmamap,
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paddr_t paddr,
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size_t byte_count);
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extern alenlist_t pcibr_dmamap_list(pcibr_dmamap_t dmamap,
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alenlist_t palenlist,
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unsigned flags);
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extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap);
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extern iopaddr_t pcibr_dmatrans_addr(vertex_hdl_t dev,
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device_desc_t dev_desc,
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paddr_t paddr,
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size_t byte_count,
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unsigned flags);
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extern alenlist_t pcibr_dmatrans_list(vertex_hdl_t dev,
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device_desc_t dev_desc,
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alenlist_t palenlist,
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unsigned flags);
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extern void pcibr_dmamap_drain(pcibr_dmamap_t map);
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extern void pcibr_dmaaddr_drain(vertex_hdl_t vhdl,
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paddr_t addr,
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size_t bytes);
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extern void pcibr_dmalist_drain(vertex_hdl_t vhdl,
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alenlist_t list);
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typedef unsigned pcibr_intr_ibit_f(pciio_info_t info,
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pciio_intr_line_t lines);
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extern void pcibr_intr_ibit_set(vertex_hdl_t, pcibr_intr_ibit_f *);
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extern pcibr_intr_t pcibr_intr_alloc(vertex_hdl_t dev,
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device_desc_t dev_desc,
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pciio_intr_line_t lines,
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vertex_hdl_t owner_dev);
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extern void pcibr_intr_free(pcibr_intr_t intr);
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extern int pcibr_intr_connect(pcibr_intr_t intr,
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intr_func_t intr_func,
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intr_arg_t intr_arg,
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void *thread);
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extern void pcibr_intr_disconnect(pcibr_intr_t intr);
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extern vertex_hdl_t pcibr_intr_cpu_get(pcibr_intr_t intr);
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extern void pcibr_provider_startup(vertex_hdl_t pcibr);
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extern void pcibr_provider_shutdown(vertex_hdl_t pcibr);
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extern int pcibr_reset(vertex_hdl_t dev);
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extern int pcibr_write_gather_flush(vertex_hdl_t dev);
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extern pciio_endian_t pcibr_endian_set(vertex_hdl_t dev,
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pciio_endian_t device_end,
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pciio_endian_t desired_end);
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extern pciio_priority_t pcibr_priority_set(vertex_hdl_t dev,
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pciio_priority_t device_prio);
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extern uint64_t pcibr_config_get(vertex_hdl_t conn,
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unsigned reg,
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unsigned size);
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extern void pcibr_config_set(vertex_hdl_t conn,
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unsigned reg,
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unsigned size,
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uint64_t value);
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extern int pcibr_error_devenable(vertex_hdl_t pconn_vhdl,
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int error_code);
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extern pciio_slot_t pcibr_error_extract(vertex_hdl_t pcibr_vhdl,
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pciio_space_t *spacep,
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iopaddr_t *addrp);
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extern int pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl,
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int *count_vchan0,
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int *count_vchan1);
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extern int pcibr_rrb_check(vertex_hdl_t pconn_vhdl,
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int *count_vchan0,
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int *count_vchan1,
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int *count_reserved,
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int *count_pool);
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extern int pcibr_alloc_all_rrbs(vertex_hdl_t vhdl, int even_odd,
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int dev_1_rrbs, int virt1,
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int dev_2_rrbs, int virt2,
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int dev_3_rrbs, int virt3,
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int dev_4_rrbs, int virt4);
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typedef void
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rrb_alloc_funct_f (vertex_hdl_t xconn_vhdl,
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int *vendor_list);
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typedef rrb_alloc_funct_f *rrb_alloc_funct_t;
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void pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl,
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rrb_alloc_funct_f *func);
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/*
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* Bridge-specific flags that can be set via pcibr_device_flags_set
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* and cleared via pcibr_device_flags_clear. Other flags are
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* more generic and are maniuplated through PCI-generic interfaces.
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*
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* Note that all PCI implementation-specific flags (Bridge flags, in
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* this case) are in the upper half-word. The lower half-word of
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* flags are reserved for PCI-generic flags.
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*
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* Some of these flags have been "promoted" to the
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* generic layer, so they can be used without having
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* to "know" that the PCI bus is hosted by a Bridge.
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*/
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#define PCIBR_WRITE_GATHER 0x00010000 /* please use PCIIO version */
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#define PCIBR_NOWRITE_GATHER 0x00020000 /* please use PCIIO version */
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#define PCIBR_PREFETCH 0x00040000 /* please use PCIIO version */
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#define PCIBR_NOPREFETCH 0x00080000 /* please use PCIIO version */
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#define PCIBR_PRECISE 0x00100000
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#define PCIBR_NOPRECISE 0x00200000
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#define PCIBR_BARRIER 0x00400000
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#define PCIBR_NOBARRIER 0x00800000
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#define PCIBR_VCHAN0 0x01000000
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#define PCIBR_VCHAN1 0x02000000
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#define PCIBR_64BIT 0x04000000
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#define PCIBR_NO64BIT 0x08000000
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#define PCIBR_EXTERNAL_ATES 0x40000000 /* uses external ATEs */
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#define PCIBR_ACTIVE 0x80000000 /* need a "done" */
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/* Flags that have meaning to pcibr_device_flags_{set,clear} */
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#define PCIBR_DEVICE_FLAGS ( \
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PCIBR_WRITE_GATHER |\
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PCIBR_NOWRITE_GATHER |\
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PCIBR_PREFETCH |\
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PCIBR_NOPREFETCH |\
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PCIBR_PRECISE |\
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PCIBR_NOPRECISE |\
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PCIBR_BARRIER |\
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PCIBR_NOBARRIER \
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)
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/* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */
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#define PCIBR_DMA_FLAGS ( \
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PCIBR_PREFETCH |\
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PCIBR_NOPREFETCH |\
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PCIBR_PRECISE |\
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PCIBR_NOPRECISE |\
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PCIBR_BARRIER |\
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PCIBR_NOBARRIER |\
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PCIBR_VCHAN0 |\
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PCIBR_VCHAN1 \
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)
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typedef int pcibr_device_flags_t;
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/*
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* Set bits in the Bridge Device(x) register for this device.
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* "flags" are defined above. NOTE: this includes turning
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* things *OFF* as well as turning them *ON* ...
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*/
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extern int pcibr_device_flags_set(vertex_hdl_t dev,
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pcibr_device_flags_t flags);
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/*
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* Allocate Read Response Buffers for use by the specified device.
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* count_vchan0 is the total number of buffers desired for the
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* "normal" channel. count_vchan1 is the total number of buffers
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* desired for the "virtual" channel. Returns 0 on success, or
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* <0 on failure, which occurs when we're unable to allocate any
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* buffers to a channel that desires at least one buffer.
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*/
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extern int pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl,
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int *count_vchan0,
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int *count_vchan1);
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/*
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* Get the starting PCIbus address out of the given DMA map.
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* This function is supposed to be used by a close friend of PCI bridge
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* since it relies on the fact that the starting address of the map is fixed at
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* the allocation time in the current implementation of PCI bridge.
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*/
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extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
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extern xwidget_intr_preset_f pcibr_xintr_preset;
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extern void pcibr_hints_fix_rrbs(vertex_hdl_t);
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extern void pcibr_hints_dualslot(vertex_hdl_t, pciio_slot_t, pciio_slot_t);
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extern void pcibr_hints_subdevs(vertex_hdl_t, pciio_slot_t, ulong_t);
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extern void pcibr_hints_handsoff(vertex_hdl_t);
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typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t);
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extern void pcibr_hints_intr_bits(vertex_hdl_t, pcibr_intr_bits_f *);
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extern int pcibr_asic_rev(vertex_hdl_t);
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#endif /* _LANGUAGE_C */
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#endif /* __PCI_PCIBR_H__ */
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