581 lines
19 KiB
C
581 lines
19 KiB
C
/**************************************************************************
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* *
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* Copyright (C) 1995-1997, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ifndef __SYS_BEAST_H__
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#define __SYS_BEAST_H__
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#include <sys/mips_addrspace.h>
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/* The following base addresses are used in any compile mode when dealing
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* with the full 64-bit addresses.
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*/
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#define KV0BASE 0x4000000000000000
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#define KPBASE 0x8000000000000000
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#define KPUNCACHED_BASE 0x9000000000000000
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#define KPCACHED_BASE 0xa800000000000000
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#define KV1BASE 0xc000000000000000
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/*
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* Exception vectors
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*/
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#define SIZE_EXCVEC 0x400 /* Size (bytes) of an exc vec */
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#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
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#ifdef _LANGUAGE_ASSEMBLY
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#define UT_VEC "not at a constant address. read C0_TrapBase register."
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#define KV0T_VEC "not at a constant address. read C0_TrapBase register."
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#define KV1T_VEC "not at a constant address. read C0_TrapBase register."
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#define E_VEC "not at a constant address. read C0_TrapBase register."
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#endif /* _LANGUAGE_ASSEMBLY */
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#ifdef _LANGUAGE_C
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#include <sys/types.h> /* needed for following extern */
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extern __psunsigned_t get_trapbase(void);
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extern void set_trapbase(__psunsigned_t);
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extern void set_kptbl(__psunsigned_t);
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#define UT_VEC (get_trapbase()+0x000) /* utlbmiss vector */
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#define KV0T_VEC (get_trapbase()+0x400) /* Kernel private tlbmiss */
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#define KV1T_VEC (get_trapbase()+0x800) /* Kernel global tlbmiss */
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#define E_VEC (get_trapbase()+0xc00) /* Gen. exception vector */
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#endif /* _LANGUAGE_C */
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#ifdef MAPPED_KERNEL
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#define NKMAPENTRIES 1
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#define KMAP_INX 1
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#else /* MAPPED_KERNEL */
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#define NKMAPENTRIES 0
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#endif /* MAPPED_KERNEL */
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#define NWIREDENTRIES 8
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#define TLBWIREDBASE (1 + NKMAPENTRIES)
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#define NTLBENTRIES 128
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#define NTLBSETS 8
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#define TLBRANDOMBASE 0
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#define NRANDOMENTRIES NTLBENTRIES
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#define TLBFLUSH_NONPDA TLBWIREDBASE /* dont flush PDA + kernel*/
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#define TLBFLUSH_NONKERN (TLBWIREDBASE+TLBKSLOTS) /* all but PDA/UPG/KSTACK */
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#define TLBFLUSH_RANDOM TLBRANDOMBASE /* flush all random tlbs */
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#define TLBLO_PFNMASK 0x000003FFFFFFFC00
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#define TLBLO_PFNSHIFT 10
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#define TLBLO_CACHMASK 0x380 /* cache coherency algorithm */
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#define TLBLO_CACHSHIFT 7
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#define TLBLO_UNCACHED 0x100 /* not cached */
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#if _RUN_UNCACHED
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#define TLBLO_NONCOHRNT TLBLO_UNCACHED
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#define TLBLO_EXL TLBLO_UNCACHED
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#define TLBLO_EXLWR TLBLO_UNCACHED
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#else /* _RUN_UNCACHED */
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#define TLBLO_NONCOHRNT 0x180 /* Cacheable non-coherent */
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#define TLBLO_EXL 0x200 /* Exclusive */
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#define TLBLO_EXLWR 0x280 /* Exclusive write */
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#endif /* _RUN_UNCACHED */
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#define TLBLO_UNCACHED_ACC 0x380 /* Uncached Accelerated */
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#define TLBLO_D 0x40 /* writeable */
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#define TLBLO_V 0x20 /* valid bit */
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#define TLBLO_G 0x10 /* global access bit */
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/*
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* TLBLO system hint field.
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*/
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#define TLBLO_SHINTMASK 0x00003C0000000000 /* system xface hint */
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#define TLBLO_SHINTSHIFT 42
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#define TLBLO_HWBITS 0x00003FFFFFFFFFFF
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#if defined (PSEUDO_BEAST)
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/* NOTE: TLBHI_VPNMASK and TLBHI_VPBSHIFT are NOT used to take the contents
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* of TLBHI and extract the VPN. Rather, they are used to take a
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* virtual address and extract the page number.
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*/
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#if _PAGESZ==4096
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#define TLBHI_VPNMASK 0xfffffffffffff000
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#define TLBHI_VPNSHIFT 12
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#endif
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#if _PAGESZ==16384
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#define TLBHI_VPNMASK 0xffffffffffffc000
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#define TLBHI_VPNSHIFT 14
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#endif
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#define TLBHI_PIDMASK 0xff0
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#define TLBHI_PIDSHIFT 4
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#define TLBHI_NPID 255 /* 255 to fit in 8 bits */
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#define TLBHI_REGIONSHIFT 62
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#ifdef _LANGUAGE_C
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#define TLBHI_REGIONMASK (3L<<TLBHI_REGIONSHIFT)
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#else
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#define TLBHI_REGIONMASK (3<<TLBHI_REGIONSHIFT)
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#endif
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#define TLBSET_PROBE 0x8000000000000000
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#define TLBSET_WIRED 0x4000000000000000
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#define TLBSET_MASK 0x7
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#define ICACHE_NPID 255
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#define SHIFTAMT_MASK 0xf
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#endif /* PSEUDO_BEAST */
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/*
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* Cache size constants
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*/
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#define MINCACHE (512 * 1024) /* 512 KB */
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#define MAXCACHE (32*1024*1024) /* 32 MB */
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#define MAXPCACHESIZE (64*1024) /* 64 KB */
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#if _PAGESZ > MAXPCACHESIZE
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#define CACHECOLORSIZE 1
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#else
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#define CACHECOLORSIZE (MAXPCACHESIZE/NBPP)
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#endif
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#define CACHECOLORMASK (CACHECOLORSIZE - 1)
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/*
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* Status register
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*/
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#define SR_CUMASK 0x70000000 /* coproc usable bits */
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#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
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#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
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#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
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#define SR_FR 0x04000000 /* enable additional fp registers */
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#define SR_RE 0x02000000 /* reverse endian in user mode */
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#define SR_HWRESET 0x00400000 /* reverse endian in user mode */
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#define SR_TLBSHUTDN 0x00200000 /* reverse endian in user mode */
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/* Diagnostic status bits */
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#define SR_SR 0x00100000 /* soft reset occured */
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#define SR_NMI 0x00080000 /* NMI bit */
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#define SR_CE 0x00040000 /* Create ECC */
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#define SR_IMASK 0x0003ff00 /* Interrupt mask */
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#define SR_IMASK10 0x00000000 /* mask level 10 */
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#define SR_IMASK9 0x00010000 /* mask level 9 */
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#define SR_IMASK8 0x00030000 /* mask level 8 */
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#define SR_IMASK7 0x00038000 /* mask level 7 */
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#define SR_IMASK6 0x0003c000 /* mask level 6 */
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#define SR_IMASK5 0x0003e000 /* mask level 5 */
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#define SR_IMASK4 0x0003f000 /* mask level 4 */
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#define SR_IMASK3 0x0003f800 /* mask level 3 */
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#define SR_IMASK2 0x0003fc00 /* mask level 2 */
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#define SR_IMASK1 0x0003fe00 /* mask level 1 */
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#define SR_IMASK0 0x0003ff00 /* mask level 0 */
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#define SR_IBIT10 0x00020000 /* bit level 8 */
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#define SR_IBIT9 0x00010000 /* bit level 8 */
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#define SR_IBIT8 0x00008000 /* bit level 8 */
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#define SR_IBIT7 0x00004000 /* bit level 7 */
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#define SR_IBIT6 0x00002000 /* bit level 6 */
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#define SR_IBIT5 0x00001000 /* bit level 5 */
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#define SR_IBIT4 0x00000800 /* bit level 4 */
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#define SR_IBIT3 0x00000400 /* bit level 3 */
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#define SR_IBIT2 0x00000200 /* bit level 2 */
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#define SR_IBIT1 0x00000100 /* bit level 1 */
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#define SR_KSU_MSK 0x00000018 /* 2 bit mode: 00b=>k, 10b=>u */
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#define SR_KSU_USR 0x00000010 /* 2 bit mode: 00b=>k, 10b=>u */
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#define SR_KSU_KS 0x00000008 /* 0-->kernel 1-->supervisor */
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#define SR_ERL 0x00000004 /* Error level, 1=>cache error */
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#define SR_EXL 0x00000002 /* Exception level, 1=>exception */
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#define SR_IE 0x00000001 /* interrupt enable, 1=>enable */
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#define SR_IEC SR_IE /* compat with R3000 source */
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#define SR_PREVMODE SR_KSU_MSK /* previous kernel/user mode */
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#define SR_PAGESIZE 0 /* No pagesize bits in SR */
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#define SR_DM 0 /* No FP Debug Mode bits in SR */
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#define SR_DEFAULT 0 /* Bits to preserve in SR */
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#define SR_KERN_SET SR_KADDR|SR_UXADDR /*Bits to set in SR for kernel mode*/
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#define SR_KERN_USRKEEP 0 /* Bits to keep in SR from user mode*/
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/*
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* SR_KADDR defines the desired state of the kernel address mode bit
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* in C0_SR, if such bits exist. We could actually enable SR_KX when
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* compiled under 32-bit compilers, though there is no real reason to do so.
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*/
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#if defined (PSEUDO_BEAST)
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/*
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* hack so that spl is not 0.
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*/
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#define SR_KADDR SR_CU0 /* kernel 32 bit addressing */
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#else
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#define SR_KADDR 0 /* kernel 32 bit addressing */
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#endif
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#define SR_UXADDR 0 /* no user ext. address/opcodes */
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#define SR_UX 0
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#define SR_KX 0
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#define SR_DE 0
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#define SR_IMASKSHIFT 8
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/*
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* Cause Register
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*/
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#define CAUSE_BD 0x80000000 /* Branch delay slot */
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#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
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#define CAUSE_CESHIFT 28
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/* Interrupt pending bits */
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#define CAUSE_IP10 0x00020000 /* External level 10 pending */
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#define CAUSE_IP9 0x00010000 /* External level 9 pending */
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#define CAUSE_IP8 0x00010000 /* External level 8 pending */
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#define CAUSE_IP7 0x00004000 /* External level 7 pending */
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#define CAUSE_IP6 0x00002000 /* External level 6 pending */
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#define CAUSE_IP5 0x00001000 /* External level 5 pending */
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#define CAUSE_IP4 0x00000800 /* External level 4 pending */
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#define CAUSE_IP3 0x00000400 /* External level 3 pending */
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#define CAUSE_SW2 0x00000200 /* Software level 2 pending */
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#define CAUSE_SW1 0x00000100 /* Software level 1 pending */
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#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
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#define CAUSE_IPSHIFT 8
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#define CAUSE_EXCMASK 0x00000078 /* Cause code bits */
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#define CAUSE_EXCSHIFT 3
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#define CAUSE_FMT "\20\40BD\36CE1\35CE0\20IP8\17IP7\16IP6\15IP5\14IP4\13IP3\12SW2\11SW1\1INT"
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#define setsoftclock() siron(CAUSE_SW1)
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#define setsoftnet() siron(CAUSE_SW2)
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#define acksoftclock() siroff(CAUSE_SW1)
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#define acksoftnet() siroff(CAUSE_SW2)
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/* Cause register exception codes */
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#define EXC_CODE(x) ((x)<<3)
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/* Hardware exception codes */
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#define EXC_INT EXC_CODE(0) /* interrupt */
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#define EXC_MOD EXC_CODE(1) /* TLB mod */
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#define EXC_RMISS EXC_CODE(2) /* Read TLB Miss */
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#define EXC_WMISS EXC_CODE(3) /* Write TLB Miss */
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#define EXC_RADE EXC_CODE(4) /* Read Address Error */
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#define EXC_WADE EXC_CODE(5) /* Write Address Error */
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#define EXC_IBE EXC_CODE(6) /* Instruction Bus Error */
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#define EXC_DBE EXC_CODE(7) /* Data Bus Error */
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#define EXC_SYSCALL EXC_CODE(8) /* SYSCALL */
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#define EXC_BREAK EXC_CODE(9) /* BREAKpoint */
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#define EXC_II EXC_CODE(10) /* Illegal Instruction */
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#define EXC_CPU EXC_CODE(11) /* CoProcessor Unusable */
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#define EXC_OV EXC_CODE(12) /* OVerflow */
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#define EXC_TRAP EXC_CODE(13) /* Trap exception */
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#define EXC_RSVD EXC_CODE(14) /* Unused */
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#define EXC_FPE EXC_CODE(15) /* Floating Point Exception */
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#define EXC_RSVD1 EXC_CODE(16) /* Unused */
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/* software exception codes */
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#define SEXC_SEGV EXC_CODE(32) /* Software detected seg viol */
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#define SEXC_RESCHED EXC_CODE(33) /* resched request */
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#define SEXC_PAGEIN EXC_CODE(34) /* page-in request */
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#define SEXC_CPU EXC_CODE(35) /* coprocessor unusable */
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#define SEXC_BUS EXC_CODE(36) /* software detected bus error */
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#define SEXC_KILL EXC_CODE(37) /* bad page in process (vfault) */
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#define SEXC_WATCH EXC_CODE(38) /* watchpoint (vfault) */
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#define SEXC_RSVD EXC_CODE(39) /* unused */
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#define SEXC_RSVD1 EXC_CODE(40) /* unused */
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#define SEXC_UTINTR EXC_CODE(41) /* post-interrupt uthread processing */
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/*
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* Coprocessor 0 operations
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*/
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#define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */
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#define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */
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#define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */
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#define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */
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/*
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* BEAST Cache Definitions
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* Cache sizes are in bytes
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*/
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#define CACHE_ILINE_SIZE 128 /* Primary instruction line size */
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#define CACHE_ILINE_MASK ~(CACHE_ILINE_SIZE-1)
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#define CACHE_DLINE_SIZE 128 /* Primary data line size */
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#define CACHE_DLINE_MASK ~(CACHE_DLINE_SIZE-1)
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#define CACHE_SLINE_SIZE 128 /* Secondary cache line size */
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#define CACHE_SLINE_MASK ~(CACHE_SLINE_SIZE-1)
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/*
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* Coprocessor 0 registers
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* Some of these are r4000 specific.
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*/
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#ifdef _LANGUAGE_ASSEMBLY
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#define C0_TLBSET $0 /* Select set in set-associative tlb */
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#define C0_TLBRAND $1 /* Pseudo-Random counter for tlb repl*/
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#define C0_TLBLO $2 /* Low half of tlb entry */
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#define C0_KPS $3 /* Kernel/Supervisor page size */
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#define C0_WORK0 $4 /* Uninterpreted temp. register */
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#define C0_UPS $5 /* User page size */
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#define C0_TRAPBASE $6 /* Base addr of exception vectors */
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#define C0_ICACHE $7 /* Icache address space id */
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#define C0_BADVADDR $8 /* Virtual address register */
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#define C0_COUNT $9 /* Free-running counter */
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#define C0_TLBHI $10 /* High half of tlb entry */
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#define C0_COMPARE $11 /* Timer Compare */
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#define C0_SR $12 /* Status register */
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#define C0_CAUSE $13 /* Cause register */
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#define C0_EPC $14 /* Exception program counter */
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#define C0_PRID $15 /* Revision identifier */
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#define C0_CONFIG $16 /* Hardware configuration */
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#define C0_WORK1 $17 /* Uninterpreted temp. register */
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#define C0_WORK2 $20 /* Uninterpreted temp. register */
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#define C0_WORK3 $21 /* Uninterpreted temp. register */
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#define C0_SERINTFC $22 /* Serial Interface */
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#define C0_DIAG $23 /* Diagnostic */
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#define C0_PERFCNT $25 /* Performance Counters */
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#define C0_ECC $26 /* S-cache ECC and primary parity */
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#define C0_CACHE_ERR $27 /* cache error status */
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#define C0_TAGLO $28 /* cache operations */
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# else /* ! _LANGUAGE_ASSEMBLY */
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#define C0_TLBSET 0 /* Select set in set-associative tlb */
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#define C0_TLBRAND 1 /* Pseudo-Random counter for tlb repl*/
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#define C0_TLBLO 2 /* Low half of tlb entry */
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#define C0_KPS 3 /* Kernel/Supervisor page size */
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#define C0_WORK0 4 /* Uninterpreted temp. register */
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#define C0_UPS 5 /* User page size */
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#define C0_TRAPBASE 6 /* Base addr of exception vectors */
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#define C0_ICACHASID 7 /* Icache address space id */
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#define C0_BADVADDR 8 /* Virtual address register */
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#define C0_COUNT 9 /* Free-running counter */
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#define C0_TLBHI 10 /* High half of tlb entry */
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#define C0_COMPARE 11 /* Timer Compare */
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#define C0_SR 12 /* Status register */
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#define C0_CAUSE 13 /* Cause register */
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#define C0_EPC 14 /* Exception program counter */
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#define C0_PRID 15 /* Revision identifier */
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#define C0_CONFIG 16 /* Hardware configuration */
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#define C0_WORK1 17 /* Uninterpreted temp. register */
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#define C0_WORK2 20 /* Uninterpreted temp. register */
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#define C0_WORK3 21 /* Uninterpreted temp. register */
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#define C0_SERINTFC 22 /* Serial Interface */
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#define C0_DIAG 23 /* Diagnostic */
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#define C0_PERFCNT 25 /* Performance Counters */
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#define C0_ECC 26 /* S-cache ECC and primary parity */
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#define C0_CACHE_ERR 27 /* cache error status */
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#define C0_TAGLO 28 /* cache operations */
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#endif /* _LANGUAGE_ASSEMBLY */
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#define TLB_PSIZE_SHFT 4
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#define TLB_PSIZE_MASK 0xf
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#define TLB_PSIZE_SET_SHFT(_set) ((_set) * TLB_PSIZE_SHFT)
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#define TLB_PSIZE_SET_VAL(_set, _val) ((_val) << TLB_PSIZE_SET_SHFT(_set))
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/*
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* Page size values (per tlbset)to be programmed into the KPS and UPS regs
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*/
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#define TLB_PSIZE_4k 0
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#define TLB_PSIZE_16k 1
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#define TLB_PSIZE_64k 2
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#define TLB_PSIZE_256k 3
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#define TLB_PSIZE_1m 4
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#define TLB_PSIZE_4m 5
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#define TLB_PSIZE_16m 6
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#define DEFAULT_PAGE_SIZE (TLB_PSIZE_SET_VAL(7, TLB_PSIZE_16k) | \
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TLB_PSIZE_SET_VAL(6, TLB_PSIZE_16k) | \
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TLB_PSIZE_SET_VAL(5, TLB_PSIZE_16k) | \
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TLB_PSIZE_SET_VAL(4, TLB_PSIZE_16k) | \
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TLB_PSIZE_SET_VAL(3, TLB_PSIZE_16k) | \
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TLB_PSIZE_SET_VAL(2, TLB_PSIZE_16k) | \
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TLB_PSIZE_SET_VAL(1, TLB_PSIZE_16k) | \
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TLB_PSIZE_SET_VAL(0, TLB_PSIZE_16k))
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/* target cache */
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#define CACH_PI 0x0 /* Primary instruction cache */
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#define CACH_PD 0x1 /* Primary data cache */
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#define CACH_S 0x3 /* Secondary cache */
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#define CACH_BARRIER 0x14 /* Cache barrier operation */
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/* Cache operations */
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#define C_IINV 0x00 /* index invalidate (i) */
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#define C_IWBINV 0x00 /* index writeback inval (s) */
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#define C_ILT 0x04 /* index load tag (all) */
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#define C_IST 0x08 /* index store tag (all) */
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#define C_HINV 0x10 /* hit invalidate (s) */
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#define C_HWBINV 0x14 /* hit writeback inv. (s) */
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#define C_HWB C_HWBINV /* hit writeback inv. (s) */
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#define PICACHE_SETS 8
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#define PICACH_SIZE_SHFT 3
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#define PDCACHE_SETS 8
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#define PDCACH_SIZE_SHFT 3
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#define SCACHE_SETS 2
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#define SCACH_SIZE_SHFT 1
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/*
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* BEAST Configuration - These define the values used
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* during the reset cycle.
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*/
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#define CONFIG_K0_SHFT 0
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#define CONFIG_K0_MASK (0x7 << CONFIG_K0_SHFT)
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#define CONFIG_K0(_B) ((_B) << CONFIG_K0_SHFT)
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#define CONFIG_DN_SHFT 3
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#define CONFIG_DN_MASK (0x1 << CONFIG_DN_SHFT)
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#define CONFIG_PD_SHFT 4
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#define CONFIG_PD_MASK (0x1 << CONFIG_PD_SHFT)
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#define CONFIG_PD(_B) ((_B) << CONFIG_PD_SHFT)
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#define CONFIG_CBM_SHFT 5
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#define CONFIG_CBM_MASK (0x1 << CONFIG_CBM_SHFT)
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#define CONFIG_CBM(_B) ((_B) << CONFIG_CBM_SHFT)
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#define CONFIG_DM_SHFT 6
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#define CONFIG_DM_MASK (0x1 << CONFIG_DM_SHFT)
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#define CONFIG_DM(_B) ((_B) << CONFIG_DM_SHFT)
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#define CONFIG_BE_SHFT 7
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#define CONFIG_BE_MASK (0x1 << CONFIG_BE_SHFT)
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#define CONFIG_BE(_B) ((_B) << CONFIG_BE_SHFT)
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#define CONFIG_EW_SHFT 8
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#define CONFIG_EW_MASK (0x1 << CONFIG_EW_SHFT)
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#define CONFIG_EW(_B) ((_B) << CONFIG_EW_SHFT)
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#define CONFIG_EP_SHFT 9
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#define CONFIG_EP_MASK (0x1 << CONFIG_EP_SHFT)
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#define CONFIG_EP(_B) ((_B) << CONFIG_EP_SHFT)
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#define CONFIG_ES_SHFT 10
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#define CONFIG_ES_MASK (0x7 << CONFIG_ES_SHFT)
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#define CONFIG_ES(_B) ((_B) << CONFIG_ES_SHFT)
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#define CONFIG_ER_SHFT 13
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#define CONFIG_ER_MASK (0x1 << CONFIG_ER_SHFT)
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#define CONFIG_ER(_B) ((_B) << CONFIG_ER_SHFT)
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#define CONFIG_ED_SHFT 14
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#define CONFIG_ED_MASK (0x1 << CONFIG_ED_SHFT)
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#define CONFIG_ED(_B) ((_B) << CONFIG_ED_SHFT)
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#define CONFIG_EL_SHFT 15
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#define CONFIG_EL_MASK (0xF << CONFIG_ES_SHFT)
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#define CONFIG_EL(_B) ((_B) << CONFIG_ES_SHFT)
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#define CONFIG_ET_SHFT 19
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#define CONFIG_ET_MASK (0x7 << CONFIG_ET_SHFT)
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#define CONFIG_ET(_B) ((_B) << CONFIG_ET_SHFT)
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#define CONFIG_EI_SHFT 21
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#define CONFIG_EI_MASK (0x1 << CONFIG_EI_SHFT)
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#define CONFIG_EI(_B) ((_B) << CONFIG_EI_SHFT)
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#define CONFIG_EWL_SHFT 22
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#define CONFIG_EWL_MASK (0x7 << CONFIG_EWL_SHFT)
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#define CONFIG_EWL(_B) ((_B) << CONFIG_EWL_SHFT)
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#define CONFIG_ECI_SHFT 25
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#define CONFIG_ECI_MASK (0x1 << CONFIG_ECI_SHFT)
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#define CONFIG_ECI(_B) ((_B) << CONFIG_ECI_SHFT)
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#define CONFIG_ESYNC_SHFT 26
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#define CONFIG_ESYNC_MASK (0x1 << CONFIG_ESYNC_SHFT)
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#define CONFIG_ESYNC(_B) ((_B) << CONFIG_ESYNC_SHFT)
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#define CONFIG_WM_SHFT 27
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#define CONFIG_WM_MASK (0x7 << CONFIG_WM_SHFT)
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#define CONFIG_WM(_B) ((_B) << CONFIG_WM_SHFT)
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#define CONFIG_EM_SHFT 30
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#define CONFIG_EM_MASK (0x3 << CONFIG_EM_SHFT)
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#define CONFIG_EM(_B) ((_B) << CONFIG_EM_SHFT)
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#define CONFIG_SI_SHFT 32
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#define CONFIG_SI_MASK (0x7 << CONFIG_SI_SHFT)
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#define CONFIG_SI(_B) ((_B) << CONFIG_SI_SHFT)
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#define CONFIG_SS_SHFT 35
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#define CONFIG_SS_MASK (0x3 << CONFIG_SS_SHFT)
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#define CONFIG_SS(_B) ((_B) << CONFIG_SS_SHFT)
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#define CONFIG_SM_SHFT 37
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#define CONFIG_SM_MASK (0x1F << CONFIG_SM_SHFT)
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#define CONFIG_SM(_B) ((_B) << CONFIG_SM_SHFT)
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#define CONFIG_SC_SHFT 42
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#define CONFIG_SC_MASK (0x1 << CONFIG_SC_SHFT)
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#define CONFIG_SC(_B) ((_B) << CONFIG_SC_SHFT)
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#define CONFIG_SR_SHFT 43
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#define CONFIG_SR_MASK (0x1 << CONFIG_SR_SHFT)
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#define CONFIG_SR(_B) ((_B) << CONFIG_SR_SHFT)
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#define CONFIG_SH_SHFT 44
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#define CONFIG_SH_MASK (0xF << CONFIG_SH_SHFT)
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#define CONFIG_SH(_B) ((_B) << CONFIG_SH_SHFT)
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#define CONFIG_VS_SHFT 48
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#define CONFIG_VS_MASK (0x3 << CONFIG_VS_SHFT)
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#define CONFIG_VS(_B) ((_B) << CONFIG_VS_SHFT)
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#define CONFIG_VR_SHFT 50
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#define CONFIG_VR_MASK (0x1 << CONFIG_VR_SHFT)
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|
#define CONFIG_VR(_B) ((_B) << CONFIG_VR_SHFT)
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|
#define CONFIG_DC_SHFT 58
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|
#define CONFIG_DC_MASK (0x7 << CONFIG_DC_SHFT)
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|
#define CONFIG_DC(_B) ((_B) << CONFIG_DC_SHFT)
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#define CONFIG_IC_SHFT 61
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#define CONFIG_IC_MASK (0x7 << CONFIG_IC_SHFT)
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|
#define CONFIG_IC(_B) ((_B) << CONFIG_IC_SHFT)
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|
|
|
#if _PAGESZ == 4096
|
|
#define SYS_PGSIZE_BITS TLB_PSIZE_4k
|
|
#elif _PAGESZ == 16384
|
|
#define SYS_PGSIZE_BITS TLB_PSIZE_16k
|
|
#else
|
|
#error <SYS_PGSIZE_BITS need to be set>
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|
#endif
|
|
|
|
/*
|
|
* software definitions and function declarations
|
|
*/
|
|
#if defined(_LANGUAGE_C)
|
|
|
|
typedef struct cacheop_s {
|
|
__uint64_t cop_address; /* address for operation */
|
|
__uint64_t cop_tag; /* tag hi value */
|
|
__uint32_t cop_operation; /* operation */
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|
} cacheop_t;
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|
|
|
#endif
|
|
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#endif /* __SYS_BEAST_H__ */
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