234 lines
10 KiB
C
234 lines
10 KiB
C
/**************************************************************************
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* *
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* Copyright (C) 1990, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ident "sys/ecpplpreg.h: $Revision: 1.12 $"
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/*
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* ecpplpreg.h - header for the IP30/IP27 parallel port driver
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*/
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#ifndef _ECPPLPREG_H_
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#define _ECPPLPREG_H_
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/* IOC3 Base Address */
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#define IOC3_BASE 0x1f500000
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/* PCI Conf. space base addr */
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#define PCI_CONF_ADDR 0x1f4c0000
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/* IOC3 Misc Registers */
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/* These are in config space */
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#define PCI_ADDR_OFFSET 0x10 /* IOC3 Base Address Register */
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#define PCI_SCR_OFFSET 0x04 /* IOC3 Status/Command Register */
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#define PCI_ADDR (PCI_CONF_ADDR+PCI_ADDR_OFFSET)
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#define PCI_SCR (PCI_CONF_ADDR+PCI_SCR_OFFSET)
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#define SIO_CR (IOC3_BASE+IOC3_SIO_CR)
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/* Reset bit in SIO_CR */
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#define SIO_RESET 0x1
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/* IOC3 PP DMA Register addresses */
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#define PPCR_COUNT_MASK 0x1ffff /* Bits 0:16 contain the count in PPCR_A and PPCR_B*/
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/* Bit positions in PPCR */
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#define PPCR_EN_A 0x1 /* Read only copy of PPCR_A<EN> */
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#define PPCR_LAST_A (0x1 << 1) /* Read only copy of PPCR_A<LAST> */
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#define PPCR_BUSY_A (0x1 << 2) /* DMA engine transferring context A */
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#define PPCR_EN_B (0x1 << 3) /* Read only copy of PPCR_B<EN> */
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#define PPCR_LAST_B (0x1 << 4) /* Read only copy of PPCR_B<LAST> */
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#define PPCR_BUSY_B (0x1 << 5) /* DMA engine transferring context B */
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#define PPCR_DIR_FROM_PP (0x1 << 29) /* Direction of DMA. 0 -> write to PP,
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* 1 -> read from PP */
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#define PPCR_DMA_RST (0x1 << 30) /* reset DMA state m/c in IOC3 */
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#define PPCR_DMA_EN (0x1 << 31) /* Enable DMA engine */
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/* Bit positions in PPCR_<A:B> */
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#define PPCR_EN (0x1 << 30) /* Indicates that context is ready */
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#define PPCR_LAST (0x1 << 31) /* Indicates that TC is to be asserted after
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* this context */
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/* Bit positions in DCR */
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#define DCR_NSTB 0x1 /* Strobe */
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#define DCR_NAFD (0x1 << 1) /* Auto feed */
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#define DCR_NINIT (0x1 << 2) /* Init */
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#define DCR_NSLCTIN (0x1 << 3) /* nSelectin */
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#define DCR_DIR (0x1 << 5) /* Direction: 1 -> Read from PP,
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* 0-> write to PP */
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/* Bit positions in ECR */
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#define ECR_EMPTY 0x1 /* Fifo Empty bit */
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#define ECR_FULL (0x1 << 1) /* FIFO full bit */
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#define ECR_SVCINTB (0x1 << 2) /* Enable service interrupt */
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#define ECR_DMA_EN (0x1 << 3) /* DMA enable */
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#define ECR_ENFLTINTB (0x1 << 4) /* Enable nFault Interrupt */
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#define ECR_MODE_MASK 0xe0 /* bits 5,6 & 7 of ECR */
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#define ECR_MODE1 0x20 /* 001 in bits 7-5 */
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#define ECR_MODE3 0x60 /* 011 in bits 7-5 */
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/* Bit positions in DSR */
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#define DSR_INTR (0x1 << 2) /* printer intr */
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#define DSR_NFAULT (0x1 << 3) /* nFault */
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#define DSR_SELECT (0x1 << 4) /* Select */
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#define DSR_PERROR (0x1 << 5) /* PE */
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#define DSR_NACK (0x1 << 6) /* NACK */
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#define DSR_BUSY (0x1 << 7) /* Busy */
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#define EXT_REQ_ECP 0x10 /* Extensibility value. Req. ECP Mode */
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/* Bit positions */
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#define ECR_TEST_PATTERN 0x34
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#define ECR_CFG_MODE 0xf4
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#define ECR_PIO_MODE 0x00 /* Parallel port non-FIFO mode */
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#define ECR_COMP_MODE 0x40 /* Parallel port FIFO mode */
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#define ECR_ECP_MODE 0x60 /* ECP mode */
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#ifdef _KERNEL
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typedef struct memd {
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union {
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caddr_t buf; /* buffer pointer */
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unsigned long long cbp; /* current byte pointer */
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} memun_w0;
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unsigned int bc; /* byte count */
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union {
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struct memd *forw; /* forward descriptor pointer */
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unsigned long long nbdp; /* next buffer descriptor ptr */
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} memun_w2;
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} memd_t;
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#define memd_bc bc
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#define memd_cbp memun_w0.cbp
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#define memd_buf memun_w0.buf
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#define memd_nbdp memun_w2.nbdp
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#define memd_forw memun_w2.forw
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/* DMA context */
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typedef struct context {
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unsigned cbp_h; /* Upper 32 bits of address */
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unsigned cbp_l; /* Lower 32 bits of address */
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unsigned int bc; /* byte count */
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} context_t;
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typedef struct ecp_s {
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vertex_hdl_t plp_conn_vhdl; /* vertex handle of connection point */
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vertex_hdl_t vhdl; /* my vertex handle */
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unsigned char state; /* software state of port */
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unsigned int mode; /* mode port is in - ECP, EPP, PPF */
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unsigned int phase; /* phase port is in */
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ioc3_mem_t *ecpregs; /* address of parallel port registers */
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sema_t dmasema; /* dma channel sync */
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sema_t wlock, rlock, dlock; /* write, read and dma locks */
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mutex_t rbufsmutex; /* lock for rbufs list */
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sv_t rbufssv; /* list sync */
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memd_t *rbufs; /* list of data buffers that have
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* been read on this channel.
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* Pointers are K0 addrs, buffers are K1
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*/
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__uint64_t rdl,wdl; /* descriptor list: PHYS addr */
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__uint64_t cwdp; /* current write desc. pointer */
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int rto, wto; /* read & write timeout in secs */
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int rtimeoutid; /* read timeoutid */
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int wtimeoutid; /* write timeoutid */
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struct buf *bp; /* buf pointer */
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context_t contexta, contextb; /* DMA contexts */
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#define CONTXT_A_INTR 1
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#define CONTXT_B_INTR 2
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int intr_next; /* next expected interrupt */
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int final; /* final context started */
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mutex_t ecpmutex; /* sleep lock for ecp access */
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mutex_t tmoutlock; /* timeout lock */
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sv_t sv_tmout; /* timeout sync var */
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int plpinitfail; /* initialization failed */
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int ecp_mode_supp; /* ECP mode supported */
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int timed_out; /* timed out */
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int flags; /* flags */
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void *ioc3_soft; /* back pointer to ioc3 soft area */
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int ctlr_num; /* for /hw/parallel/plp%d */
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} ecp_t;
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#define ECPPLP_HWG_OK 1 /* hwgraph alias created for this device */
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#define NPLP 32 /* maximum number of parallel ports */
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/* modify these parameters for best performance
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*/
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#if NBPP == 4096
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#define NRPPP 2 /* number of read pages per port */
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#define RDSHIFT 2 /* 4 descriptors per page */
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#elif NBPP == 16384
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#define NRPPP 1 /* number of read pages per port */
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#define RDSHIFT 2 /* 4 descriptors per page */
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#else
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#error "Unknown page size"
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#endif
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#define NRP (NPLP * NRPPP) /* number of initial read pages */
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#define NRDPP (1<<RDSHIFT) /* read descriptors per page */
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#define NBPRD (NBPP>>RDSHIFT) /* bytes per read descriptor */
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#define RDMASK ~(NBPRD-1) /* mask for read descriptor bytes */
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#define NRMD (NRP*NRDPP) /* number of receive memory descs */
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#define NXMD (NPLP * 6) /* number of transmit memory descs */
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#define NMD (NRMD + NXMD) /* number of memory descriptors */
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/* size of space for memory descriptor nodes, add one in case one of the
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* descriptors crosses a page boundary and needs to be thrown away.
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*/
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#define MDMEMSIZE ((NMD + 1) * sizeof(memd_t))
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#define plpunit(dev) (minor(dev)&PLPUNITMASK)
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#define PLPUNITMASK 0x1f /* First five bits are unit number */
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/* Parallel Port Phases */
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#define COMP_FWD_IDLE_PHASE 1 /* Compatibility fwd. idle mode */
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#define COMP_FWD_BUSY_PHASE 2 /* Compatibility fwd. busy mode */
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#define NEGOTIATION_PHASE 3 /* Negotiation to determine ECP compliance */
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#define SETUP_PHASE 4 /* Intermediate bet. negotiation and fwd_idle */
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#define ECP_FWD_IDLE_PHASE 5 /* ECP fwd idle mode */
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#define ECP_FWD_BUSY_PHASE 6 /* ECP fwd busy mode */
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#define ECP_FWD_TO_REV_PHASE 7 /* ECP fwd to rev mode */
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#define ECP_REV_TO_FWD_PHASE 8 /* ECP rev to fwd mode */
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#define ECP_REV_IDLE_PHASE 9 /* ECP rev idle mode */
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#define ECP_REV_BUSY_PHASE 10 /* ECP rev busy mode */
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#define TERMINATION_PHASE 11 /* Bring port back to known COMP_FWD_IDLE state */
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#define PLP_RTO (1 * HZ)
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/* Never time out on a write */
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#ifdef ECP_DEBUG
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#define PLP_WTO (0 * HZ)
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#else
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#define PLP_WTO (0 * HZ)
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#endif /* ECP_DEBUG */
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/* Parallel Port Modes (values used in master.d/ecpplp file) */
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#define PLP_ECP_MODE 6
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#define PLP_COMP_MODE 4
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#define PLP_BIDIR_MODE 2
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#define PLP_PIO_MODE 0
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/* Parallel Port States */
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#define ECPPLP_ALIVE 0x1 /* parallel port exists */
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#define ECPPLP_WROPEN 0x2 /* open for writing */
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#define ECPPLP_RDOPEN 0x4 /* open for reading */
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#define ECPPLP_NBIO 0x8 /* set for non-blocking reads */
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#define ECPPLP_INUSE 0x10 /* reference flag for unloads */
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#define ECPPLP_OCCUPIED 0x20 /* parallel port is busy */
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#endif /* _KERNEL */
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#endif /* _ECPPLPREG_H_ */
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