242 lines
6.0 KiB
C
242 lines
6.0 KiB
C
/* $Revision: 3.15 $ */
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/* ------------------------------------------------------------------ */
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/* | Copyright Unpublished, MIPS Computer Systems, Inc. All Rights | */
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/* | Reserved. This software contains proprietary and confidential | */
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/* | information of MIPS and its suppliers. Use, disclosure or | */
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/* | reproduction is prohibited without the prior express written | */
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/* | consent of MIPS. | */
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/* ------------------------------------------------------------------ */
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/*
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* softfp.h -- constants for software floating point emulation
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*/
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/*
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* The _MASK's are used to get a the specified field after it has been
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* shifted by _SHIFT and then bit patterns (like _COPN) can be used to test
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* the field.
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*/
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/* constants for the OPCODE field for some general instructions */
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#define OPCODE_SHIFT 26
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#define OPCODE_25_SHIFT 25
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#define OPCODE_MASK 0x3f
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#define OPCODE_SPECIAL 0x00
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#define OPCODE_BCOND 0x01
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#define OPCODE_J 0x02
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#define OPCODE_JAL 0x03
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#define OPCODE_BEQ 0x04
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#define OPCODE_C1 0x11
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#define OPCODE_C1X 0x13
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#define OPCODE_C1_25 0x23
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#define COP1 0x11
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#define COP1X 0x13
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/* constants for the emulating jump or jump and link instructions */
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#define TARGET_MASK 0x03ffffff
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/*
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* When masking PC addresses we need to preserve the upper 32 bits.
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*/
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#define PC_JMP_MASK 0xfffffffff0000000LL
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/* constants for the FUNC field for some general instructions */
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#define FUNC_MASK 0x3f
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#define FUNC_JR 0x08
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#define FUNC_JALR 0x09
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/*
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* constants for the OPCODE field for detecting all general branch
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* (beq,bne,blez,bgtz) instructions and all coprocessor instructions.
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*/
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#define BRANCH_MASK 0x3c
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#define OPCODE_BRANCHES 0x04
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#define COPN_MASK 0x3c
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#define OPCODE_COPN 0x10
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/* constants for load/store COPN instructions */
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#define OP_LSWCOPNMASK 0x37
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#define OP_LSWCOPN 0x31
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#define OP_LSBITMASK 0x8
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#define OP_LBIT 0x0
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/* constants for branch on COPN condition instructions */
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#define COPN_BCSHIFT 24
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#define COPN_BCMASK 0x3
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#define COPN_BC 0x1
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#define BC_TFBITSHIFT 16
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#define BC_TFBITMASK 0x1
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#define BC_FBIT 0x0
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/* constants for move to/from COPN instructions */
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#define COPN_MTFSHIFT 25
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#define COPN_MTFMASK 0x1
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#define COPN_MTF 0x0
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#define COPN_MTFBITSHIFT 23
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#define COPN_MTFBITMASK 0x1
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#define COPN_MFBIT 0x0
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/* constants for move control registers to/from CP1 instructions */
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#define M_CONBITSHIFT 22
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#define M_CONBITMASK 0x1
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#define FPR_REV 0
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#define FPR_EIR 30
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#define FPR_CSR 31
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#define SOFTFP_REVWORD 0x0
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/*
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* These constants refer to the fields of coprocessor instructions not
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* cpu instructions (ie the RS and RD fields are different).
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*/
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#define BASE_SHIFT 21
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#define BASE_MASK 0x1f
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#define RT_SHIFT 16
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#define RT_MASK 0x1f
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#define RT_FPRMASK 0x1f
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#define RS_SHIFT 11
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#define RS_MASK 0x1f
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#define RS_FPRMASK 0x1f
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#define RD_SHIFT 6
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#define RD_MASK 0x1f
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#define RD_FPRMASK 0x1f
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#define RR_SHIFT 21
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#define RR_FPRMASK 0x1f
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#define IMMED_SHIFT 16
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#define C1_FMT_SHIFT 21
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#define C1_FMT_MASK 0xf
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#define C1_FMT_SINGLE 0
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#define C1_FMT_DOUBLE 1
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#define C1_FMT_EXTENDED 2
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#define C1_FMT_QUAD 3
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#define C1_FMT_WORD 4
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#define C1_FMT_MAX 5
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#define C1_FUNC_MASK 0x3f
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#define C1_FUNC_DIV 3
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#define C1_FUNC_NEG 7
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#define C1_FUNC_ROUND 12
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#define C1_FUNC_ROUNDW 12
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#define C1_FUNC_FLOOR 15
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#define C1_FUNC_FLOORW 15
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#define C1_FUNC_ROUNDL 8
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#define C1_FUNC_FLOORL 11
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#define C1_FUNC_CVTS 32
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#define C1_FUNC_CVTW 36
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#define C1_FUNC_CVTL 37
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#define C1_FUNC_1stCMP 48
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#define C1_FUNC_RECIP 21
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#define C1_FUNC_RSQRT 22
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#define C1X_FMT_MASK 0x7
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#define C1X_FUNC_SHIFT 3
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#define C1X_FUNC_MASK 0x7
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#define CC_MASK 0x7
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#define CC_SHIFT 8
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#define COND_MASK 0xf
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#define COND_UN_MASK 0x1
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#define COND_EQ_MASK 0x2
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#define COND_LT_MASK 0x4
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#define COND_IN_MASK 0x8
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/*
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* These constants refer to fields in the floating-point status and control
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* register.
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*/
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#define CSR_CBITSHIFT 23
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#define CSR_CBITMASK 0x1
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#define CSR_CBITSET 0x00800000
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#define CSR_CBITCLEAR 0xff7fffff
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#define CSR_FSBITSET 0x01000000
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#define UNDERFLOW_CAUSE 0x00002000
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#define INEXACT_FLAG 0x00000004
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#define UNDERFLOW_FLAG 0x00000008
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#define OVERFLOW_FLAG 0x00000010
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#define DIVIDE0_FLAG 0x00000020
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#define INVALID_FLAG 0x00000040
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#define CSR_FLAGS 0x0000007c
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#define CSR_EXCEPT 0x0003f000
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#define UNIMP_EXC 0x00020000
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#define INVALID_EXC 0x00010040
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#define DIVIDE0_EXC 0x00008020
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#define OVERFLOW_EXC 0x00004010
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#define UNDERFLOW_EXC 0x00002008
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#define INEXACT_EXC 0x00001004
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#define CSR_ENABLE 0x00000f80
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#define INVALID_ENABLE 0x00000800
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#define DIVIDE0_ENABLE 0x00000400
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#define OVERFLOW_ENABLE 0x00000200
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#define UNDERFLOW_ENABLE 0x00000100
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#define INEXACT_ENABLE 0x00000080
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#define CSR_RM_MASK 0x3
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#define CSR_RM_RN 0
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#define CSR_RM_RZ 1
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#define CSR_RM_RPI 2
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#define CSR_RM_RMI 3
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/*
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* These constants refer to floating-point values for all formats
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*/
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#define SIGNBIT 0x80000000
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#define GUARDBIT 0x80000000
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#define STKBIT 0x20000000
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/*
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* These constants refer to word values
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*/
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#define WORD_MIN 0x80000000
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#define WORD_MAX 0x7fffffff
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#define WEXP_MIN -1
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#define WEXP_MAX 30
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#define WQUIETNAN_LEAST 0x7fffffff
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#define LWEXP_MAX 62
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/*
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* These constants refer to single format floating-point values
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*/
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#define SEXP_SHIFT 23
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#define SEXP_MASK 0xff
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#define SEXP_NAN 0xff
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#define SEXP_INF 0xff
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#define SEXP_BIAS 127
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#define SEXP_MAX 127
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#define SEXP_MIN -126
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#define SEXP_OU_ADJ 192
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#define SIMP_1BIT 0x00800000
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#define SFRAC_LEAD0S 8
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#define SFRAC_BITS 23
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#define SFRAC_MASK 0x007fffff
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#define SFRAC_LEAST_MAX 0x007fffff
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#define SSNANBIT_MASK 0x00400000
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#define SQUIETNAN_LEAST 0x7fbfffff
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/*
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* These constants refer to double format floating-point values
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*/
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#define DEXP_SHIFT 20
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#define DEXP_MASK 0x7ff
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#define DEXP_NAN 0x7ff
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#define DEXP_INF 0x7ff
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#define DEXP_BIAS 1023
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#define DEXP_MAX 1023
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#define DEXP_MIN -1022
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#define DEXP_OU_ADJ 1536
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#define DIMP_1BIT 0x00100000
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#define DFRAC_LEAD0S 11
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#define DFRAC_BITS 52
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#define DFRAC_MASK 0x000fffff
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#define DFRAC_LESS_MAX 0x000fffff
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#define DFRAC_LEAST_MAX 0xffffffff
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#define DSNANBIT_MASK 0x00080000
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#define DQUIETNAN_LESS 0x7ff7ffff
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#define DQUIETNAN_LEAST 0xffffffff
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