395 lines
14 KiB
C
395 lines
14 KiB
C
/**************************************************************************
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* *
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* Copyright (C) 1998, Silicon Graphics, Inc *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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/********************************************************************************
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* *
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* sys/tpucom.h - Mesa TPU common driver/library definitions. *
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* *
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********************************************************************************/
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#ifndef __SYS_TPUCOM_H__
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#define __SYS_TPUCOM_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ident "$Id: tpucom.h,v 1.4 1999/04/29 19:32:28 pww Exp $"
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#define TPU_DEVS_MAX 288 /* max TPUs in a system */
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#define TPU_PAGES_MAX 128 /* max translation table entries */
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#define TPU_NAME_MAX 32 /* max length of short device name */
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#define TPU_MAGIC (('T' << 24) | ('P' << 16) | ('U' << 8))
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#define TPUDBG_MAGIC (('T' << 24) | ('P' << 16) | ('D' << 8))
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#define TPUSIM_MAGIC (('T' << 24) | ('P' << 16) | ('S' << 8))
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#define LIBTPU_MAGIC (('T' << 24) | ('P' << 16) | ('L' << 8))
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/*
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* Structure magic numbers.
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*/
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#define TPU_M_SOFT (TPU_MAGIC | 's')
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#define TPU_M_TRACE (TPU_MAGIC | 'u')
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#define TPU_M_TRACEX (TPU_MAGIC | 'U')
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/*
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* tpusim ioctl() function codes.
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*/
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#define TPUSIM_ATTACH (TPUSIM_MAGIC | 1)
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/*
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* tpu ioctl() function codes.
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*/
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#define TPU_RUN (TPU_MAGIC | 8)
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#define TPU_RESUME (TPU_MAGIC | 3)
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#define TPU_HALT (TPU_MAGIC | 2)
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#define TPU_REGS (TPU_MAGIC | 4)
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#define TPU_INST (TPU_MAGIC | 6)
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#define TPU_STAT (TPU_MAGIC | 13)
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#define TPU_STAT_LIST (TPU_MAGIC | 14)
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#define TPU_STATS (TPU_MAGIC | 12)
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#define TPU_GSTATS (TPU_MAGIC | 22)
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#define TPU_CONFIG (TPU_MAGIC | 9)
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#define TPU_SET_FLAG (TPU_MAGIC | 10)
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#define TPU_GET_FLAG (TPU_MAGIC | 11)
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#define TPU_SET_FAULT (TPU_MAGIC | 15)
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#define TPU_GET_FAULT (TPU_MAGIC | 16)
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#define TPU_GET_SOFT (TPU_MAGIC | 17)
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#define TPU_GET_TRACE (TPU_MAGIC | 18)
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#define TPU_GET_GTRACE (TPU_MAGIC | 21)
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#define TPU_EXT_TEST (TPU_MAGIC | 20)
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/*
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* TPU_RUN ioctl argument structure.
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*/
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typedef struct tpud_run_s {
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__uint64_t tpu_status; /* driver error code */
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__uint64_t dmaStatusReg; /* Xtalk interrupt status register (0x100) */
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__uint64_t ldiStatusReg; /* LDI register 10: tStatusReg */
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__uint64_t ldiTimerReg; /* LDI register 19: tTimerReg */
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__uint64_t _reserved_0[2];
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__uint64_t dma0Status; /* DMA 0 status */
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__uint64_t dma0Count; /* DMA 0 words output */
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__uint64_t dma0Ticks; /* DMA 0 output time (10ns ticks) */
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__uint64_t dma1Status; /* DMA 1 status */
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__uint64_t dma1Count; /* DMA 1 words input */
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__uint64_t dma1Ticks; /* DMA 1 input time (10ns ticks) */
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__uint64_t sysStartClock; /* RTC at start of TPU_RUN ioctl */
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__uint64_t tpuStartClock; /* RTC when TPU starts */
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__uint64_t tpuEndClock; /* RTC when TPU completes */
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__uint64_t sysEndClock; /* RTC at end of TPU_RUN ioctl */
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__uint64_t device; /* Device number that processed request */
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__uint64_t _reserved_1[11];
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__uint64_t timeout; /* timeout in seconds */
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__uint64_t ldi_offset; /* byte offset to start of LDI coef */
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__uint64_t page_size; /* page size in bytes */
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__uint64_t page_count; /* number of active pages */
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__uint64_t page_addr[TPU_PAGES_MAX]; /* page table */
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} tpud_run_t;
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/*
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* Only the first TPU_RUN_HDR_LEN bytes of the tpud_run_s structure will be
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* updated by the driver after the ioctl() completes.
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*/
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#define TPU_RUN_HDR_LEN ((size_t) & (((tpud_run_t *) 0)->_reserved_1[0]))
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/*
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* TPU_STATS ioctl argument structure.
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*/
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typedef struct tpud_event_s {
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__uint64_t timestamp; /* time of most recent occurrence */
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__uint64_t count; /* number of occurrences */
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} tpud_event_t;
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typedef volatile struct tpud_stats_s {
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tpud_event_t open; /* open call */
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tpud_event_t close; /* close call */
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tpud_event_t mmap; /* mmap call */
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tpud_event_t munmap; /* munmap call */
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tpud_event_t ioctlRun; /* ioctl_run call */
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tpud_event_t ioctlResume; /* ioctl_resume call */
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tpud_event_t ioctlHalt; /* ioctl_halt call */
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tpud_event_t ioctlRegs; /* ioctl_regs call */
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tpud_event_t ioctlInst; /* ioctl_inst call */
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tpud_event_t ioctlStat; /* ioctl_stat call */
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tpud_event_t ioctlStatList; /* ioctl_stat_list call */
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tpud_event_t ioctlStats; /* ioctl_stats call */
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tpud_event_t ioctlConfig; /* ioctl_config call */
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tpud_event_t ioctlSetFlag; /* ioctl_set_flag call */
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tpud_event_t ioctlGetFlag; /* ioctl_get_flag call */
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tpud_event_t ioctlSetFault; /* ioctl_set_fault call */
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tpud_event_t ioctlGetFault; /* ioctl_get_fault call */
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tpud_event_t ioctlGetSoft; /* ioctl_get_soft call */
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tpud_event_t ioctlGetTrace; /* ioctl_get_trace call */
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tpud_event_t ioctlGetGTrace; /* ioctl_get_gtrace call */
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tpud_event_t ioctlGstats; /* ioctl_gstats call */
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tpud_event_t ioctlExtTest; /* ioctl_ext_test call */
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tpud_event_t _reserved1[26];
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tpud_event_t immediateFault; /* immediate fault generated */
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tpud_event_t deferredFault; /* deferred fault generated */
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tpud_event_t timeoutFault; /* timeout fault generated */
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tpud_event_t page[6]; /* Count of each page size loaded */
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tpud_event_t timeout; /* timeouts */
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tpud_event_t dmaError; /* widget error interrupts */
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tpud_event_t ldiBarrier; /* LDI barrier interrupts */
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tpud_event_t ldiError; /* LDI error interrupts */
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tpud_event_t ldiCError; /* LDI channel error interrupts */
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__uint64_t dma0Count; /* Words output (host -> TPU) */
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__uint64_t dma0Ticks; /* Output time (10ns ticks) */
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__uint64_t dma1Count; /* Words input (TPU -> host) */
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__uint64_t dma1Ticks; /* Input time (10ns ticks) */
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} tpud_stats_t;
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/*
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* TPU_GSTATS ioctl argument structure.
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*/
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typedef volatile struct tpud_gstats_s {
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tpud_event_t assign_spec; /* assignments to specific devices */
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tpud_event_t assign_any; /* assignments to "any" device */
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tpud_event_t assign_chk; /* devices checked */
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tpud_event_t assign_none; /* no devices available */
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} tpud_gstats_t;
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/*
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* TPU_STAT ioctl argument structure.
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*/
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typedef struct tpud_stat_s {
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char name[TPU_NAME_MAX]; /* device name */
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__uint32_t vhdl; /* tpu vhdl */
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__uint32_t admin; /* admin vhdl */
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__uint32_t online; /* online flag */
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__uint32_t state; /* device state */
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__uint32_t open; /* open count */
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__uint32_t exclusive; /* exclusive open flag */
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__uint32_t simulated; /* simulated device */
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__uint32_t module; /* physical module number */
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__uint32_t slot; /* physical io slot number */
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__uint32_t _reserved[5];
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__uint64_t flag; /* user flag */
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__uint64_t dma0Count; /* Words output (host -> TPU) */
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__uint64_t dma0Ticks; /* Output time (10ns ticks) */
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__uint64_t dma1Count; /* Words input (TPU -> host) */
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__uint64_t dma1Ticks; /* Input time (10ns ticks) */
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} tpud_stat_t;
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/*
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* TPU_STAT_LIST ioctl argument structure.
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*/
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typedef struct tpud_stat_list_s {
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__uint32_t max; /* max number of stat structures to return*/
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__uint32_t count; /* number of stat structures actually returned */
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tpud_stat_t stat[1]; /* array of stat blocks */
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} tpud_stat_list_t;
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#define TPU_STAT_LIST_HDR_LEN ((size_t) & (((tpud_stat_list_t *) 0)->stat[0]))
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/*
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* TPU_REGS ioctl argument structure.
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*/
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typedef struct tpud_regs_xtk_regs_s {
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__uint32_t id; /* 0x0_0004 Identification register */
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__uint32_t status; /* 0x0_000c Crosstalk Status register */
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__uint32_t err_upper_addr; /* 0x0_0014 Error Upper Address reg */
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__uint32_t err_lower_addr; /* 0x0_001c Error Address register */
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__uint32_t control; /* 0x0_0024 Crosstalk Control reg */
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__uint32_t req_timeout; /* 0x0_002c Request Time-out Value */
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__uint32_t intdest_upper_addr; /* 0x0_0034 Intrrupt Destin Addr Upper */
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__uint32_t intdest_lower_addr; /* 0x0_003c Interrupt Destination Addr */
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__uint32_t err_cmd_word; /* 0x0_0044 Error Command Word reg */
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__uint32_t llp_cfg; /* 0x0_004c LLP Configuration reg */
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__uint32_t ede; /* 0x0_0064 Error Data Enable reg */
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__uint32_t int_status; /* 0x0_0104 Interrupt Status register */
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__uint32_t int_enable; /* 0x0_010c Interrupt Enable register */
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__uint32_t int_addr0; /* 0x0_0134 Aux Interrupt 0 Addr reg */
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__uint32_t int_addr1; /* 0x0_013c Aux Interrupt 1 Addr reg */
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__uint32_t int_addr2; /* 0x0_0144 Aux Interrupt 2 Addr reg */
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__uint32_t int_addr3; /* 0x0_014c Aux Interrupt 3 Addr reg */
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__uint32_t int_addr4; /* 0x0_0154 Aux Interrupt 4 Addr reg */
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__uint32_t int_addr5; /* 0x0_015c Aux Interrupt 5 Addr reg */
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__uint32_t int_addr6; /* 0x0_0164 Aux Interrupt 6 Addr reg */
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__uint32_t sense; /* 0x0_0184 User Definable Sense reg */
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__uint32_t leds; /* 0x0_018c User Definable Enable reg */
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} tpud_regs_xtk_regs_t;
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#define TPU_ATT_SIZE 128
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typedef struct tpud_regs_att_regs_s {
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__uint32_t config; /* 0x8_0004 Address Translation Configuration reg */
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__uint32_t diag; /* 0x8_000c Address Translation Diagnostic reg */
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__uint64_t atte[TPU_ATT_SIZE]; /* 0x8_0400 Address Translation Table */
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} tpud_regs_att_regs_t;
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typedef struct tpud_regs_dma_regs_s {
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__uint64_t config0; /* 0x10_0000 Configuration Reg 0 */
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__uint64_t config1; /* 0x10_0008 Configuration Reg 1 */
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__uint64_t status; /* 0x10_0010 Status register */
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__uint64_t diag_mode; /* 0x10_0018 Diagnostic Mode register */
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__uint64_t perf_timer; /* 0x10_0020 Performance Timer reg */
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__uint64_t perf_count; /* 0x10_0028 Performance Counter reg */
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__uint64_t perf_config; /* 0x10_0030 Performance Config reg */
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} tpud_regs_dma_regs_t;
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typedef struct tpud_regs_ldi_regs_s {
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__uint64_t riscIOpcode; /* 0 0x30_02e0 Risc Loaded Op Instruction */
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__uint64_t riscMode; /* 1 0x30_02e8 using Risc to operate LSP */
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__uint64_t xRiscSadr; /* 2 0x30_02f0 Risc loaded starting addr */
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__uint64_t coefBs; /* 3 0x30_02f8 Coef Block Size */
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__uint64_t coefInc; /* 4 0x30_0300 Coef Incrementer */
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__uint64_t coefInit; /* 5 0x30_0308 Coef Initial data */
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__uint64_t dataBs; /* 6 0x30_0310 Data Block Size */
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__uint64_t saBlkInc; /* 7 0x30_0318 Start Addr Blk Incrementer */
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__uint64_t saBlkSize; /* 8 0x30_0320 Start Addr Blk Size */
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__uint64_t saBlkInit; /* 9 0x30_0328 Start Addr Blk Initial */
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__uint64_t statusReg; /* 10 0x30_0330 Status readback register */
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__uint64_t sampInit; /* 11 0x30_0338 Receive sample data initial */
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__uint64_t vectInitInc; /* 12 0x30_0340 Rec SA Vector init Incr */
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__uint64_t vectInit; /* 13 0x30_0348 Rec SA Vector initial */
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__uint64_t vectInc; /* 14 0x30_0350 Rec SA Vector incrementer */
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__uint64_t errorMask; /* 15 0x30_0358 Error interrupt mask */
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__uint64_t lbaBlkSize; /* 16 0x30_0360 LBA block size */
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__uint64_t loopCnt; /* 17 0x30_0368 Loop counter for i-que */
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__uint64_t diagReg; /* 18 0x30_0370 Diagnostic Readback register */
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__uint64_t iSource; /* 19 0x30_0378 Timer/barrier source reg */
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__uint64_t pipeInBus[8]; /* 20 0x30_0380 -> 27 0x30_03b8 xmit Load pipe In bus size */
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__uint64_t rRiscSadr; /* 28 0x30_03c0 */
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__uint64_t sampInc; /* 29 0x30_03c8 Receive sample increment */
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__uint64_t oLineSize; /* 30 0x30_03d0 Receive output line size */
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__uint64_t iMask; /* 31 0x30_03d8 */
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__uint64_t tFlag; /* 32 0x30_03e0 */
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__uint64_t bFlag; /* 33 0x30_03e8 */
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__uint64_t diagPart; /* 34 0x30_03f0 */
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__uint64_t jmpCnd; /* 35 0x30_03f8 */
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} tpud_regs_ldi_regs_t;
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typedef struct tpud_regs_s {
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tpud_regs_xtk_regs_t xtk_regs;
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tpud_regs_att_regs_t att_regs;
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tpud_regs_dma_regs_t dma0_regs;
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tpud_regs_dma_regs_t dma1_regs;
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tpud_regs_ldi_regs_t ldi_regs;
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} tpud_regs_t;
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/*
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* TPU_INST ioctl argument structure.
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*/
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#define TPU_LDI_I_SIZE 64
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#define TPU_LDI_I_UPPER 0
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#define TPU_LDI_I_LOWER 1
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typedef struct tpud_inst_s {
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__uint64_t inst[TPU_LDI_I_SIZE][2];/* 0x30_0400 Instruction memory*/
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} tpud_inst_t;
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/*
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* TPU_CONFIG argument values.
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*/
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#define TPU_CONFIG_DOWN 0
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#define TPU_CONFIG_UP 1
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/*
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* TPU_SET_FAULT/TPU_GET_FAULT ioctl argument structure.
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*/
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typedef enum {
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TPU_FAULT_NONE = 0,
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TPU_FAULT_IMMEDIATE,
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TPU_FAULT_DEFERRED,
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TPU_FAULT_TIMEOUT
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} tpud_fault_type_t;
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typedef struct tpud_fault_s {
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tpud_fault_type_t type; /* fault type */
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__int64_t cycles; /* total number of fault cycles */
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__int64_t interval; /* interval between faults */
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__int64_t duration; /* number of times to repeat fault */
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__uint64_t tpu_status; /* driver error code */
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__uint64_t _reserved_0[9];
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__uint64_t dmaStatusReg; /* DMA interrupt status register */
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__uint64_t dmaStatusReg_mask; /* mask for DMA interrupt status register */
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__uint64_t ldiStatusReg; /* LDI register 10: tStatusReg */
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__uint64_t ldiStatusReg_mask; /* mask for LDI register 10: tStatusReg */
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__uint64_t ldiTimerReg; /* LDI register 19: tTimerReg */
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__uint64_t ldiTimerReg_mask; /* mask for LDI register 19: tTimerReg */
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__uint64_t dma0Status; /* DMA 0 status */
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__uint64_t dma0Status_mask; /* mask for DMA 0 status */
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__uint64_t dma1Status; /* DMA 1 status */
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__uint64_t dma1Status_mask; /* mask for DMA 1 status */
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} tpud_fault_t;
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/*
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* TPU_GET_TRACE structures.
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*/
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#define TPU_TRACEB_LEN 1024 /* entries in a trace buffer (must be 2**N) */
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#define TPU_TRACEB_MAXP 5 /* max number of parameters in a trace entry */
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#define TPU_TRACEB_MAXF 256 /* max length of a format string */
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/*
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* Trace entry.
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*/
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typedef struct tpud_tracee_s {
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__int64_t timestamp; /* timestamp */
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__int32_t cpu; /* cpu */
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__int32_t _reserved;
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char * fmt; /* format string pointer */
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__uint64_t param[TPU_TRACEB_MAXP]; /* parameters */
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} tpud_tracee_t;
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/*
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* Trace buffer.
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*/
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typedef struct tpud_traceb_s {
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__uint32_t magic; /* magic number (TPU_M_TRACE) */
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__int32_t _reserved_0;
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__int64_t count; /* total number of trace entries made */
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__int64_t create_sec; /* system seconds at buffer creation */
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__int64_t create_rtc; /* RTC at buffer creation */
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__int32_t rtc_nsec; /* RTC clock period in nsec */
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__int32_t _reserved_1[7];
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tpud_tracee_t e[TPU_TRACEB_LEN]; /* trace entries */
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} tpud_traceb_t;
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/*
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* Exportable copy of trace buffer.
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*/
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typedef struct tpud_tracex_s {
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tpud_traceb_t t; /* trace buffer */
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char f[TPU_TRACEB_LEN][TPU_TRACEB_MAXF]; /* format strings */
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} tpud_tracex_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYS_TPUCOM_H__ */
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