321 lines
13 KiB
Plaintext
321 lines
13 KiB
Plaintext
#
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# $Id: hw.help,v 1.7 1999/05/11 19:26:03 kenmcd Exp $
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#
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@ hw.r10kevctr.state R10000 event counter state
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The values are
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-1 this system does not include R10000 CPUs, so no event counters
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0 this system has R10000 CPUs, but all of the global event counters
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are disabled ... see ecadmin(1) to enable global event counters
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other this system has R10000 CPUs, and this metric reports the number
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of the global event counters that have been enabled
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@ hw.r10kevctr.cpurev R10000 CPU revision
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R10000 CPU revision.
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Interpretation of the R1000 event counters is dependent in some
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cases on the CPU revision.
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@ hw.r10kevctr.cycles R10000 event counter - cycles
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R10000 event counter - cycles.
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This event counter is incremented once per clock cycle, and
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hw.r10kevctr.cycles is the sum over all CPUs.
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@ hw.r10kevctr.issue.instri R10000 event counter - instructions issued
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R10000 event counter - instructions issued.
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This event counter is incremented on each cycle by the sum of the three
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following events:
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- Integer operations marked as "done" in the active list
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- Floating point operations issued to an FPU
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- Load/store instructions issued to the address calculation unit on
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the previous cycle
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hw.r10kevctr.issue.instri is the sum over all CPUs.
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@ hw.r10kevctr.issue.loadi R10000 event counter - loads, etc. issued
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R10000 event counter - loads, etc. issued.
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This counter is incremented when a load instruction was issued to the
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address-calculation unit on the previous cycle. Unlike the combined
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"issued instructions" count, this counter counts each load instruction
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as being issued only once. Prefetches are counted as issued loads in
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rev 3.x but not 2.x
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hw.r10kevctr.issue.loadi is the sum over all CPUs.
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@ hw.r10kevctr.issue.storei R10000 event counter - stores issued
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R10000 event counter - stores issued.
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The counter is incremented on the cycle after a store instruction is
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issued to the address-calculation unit, and hw.r10kevctr.issue.storei
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is the sum over all CPUs.
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@ hw.r10kevctr.issue.scondi R10000 event counter - store conditionals issued
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R10000 event counter - store conditionals issued.
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This counter is incremented on the cycle after a store conditional
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instruction is issued to the address-calculation unit, and
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hw.r10kevctr.issue.scondi is the sum over all CPUs.
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@ hw.r10kevctr.fail.scondf R10000 event counter - store conditionals failed
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R10000 event counter - store conditionals failed.
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This counter is incremented when a store-conditional instruction fails.
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A failed store-conditional instruction will, in the normal course of
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events, graduate; so this event represents a subset of the
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store-conditional instructions counted as hw.r10kevctr.grad.scondg.
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hw.r10kevctr.fail.scondf is the sum over all CPUs.
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@ hw.r10kevctr.issue.brd R10000 event counter - branches decoded
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R10000 event counter - branches decoded.
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In rev 2.6 and earlier revisions, this counter is incremented when a
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branch (conditional or unconditional) instruction is decoded (include
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those aborted & resolved) and inserted into the active list; even
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though, it may still be killed due to an exception or a prior
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mispredicted branch.
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For rev 3.x, this counter is incremented when a conditional branch is
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determined to have been "resolved". Note that when multiple
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floating-point conditional branches are resolved in a single cycle,
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this counter is still only incremented by one. Although this is a rare
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event, in this case the count would be incorrect.
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hw.r10kevctr.issue.brd is the sum over all CPUs.
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@ hw.r10kevctr.scache.wb R10000 event counter - quadwords written back from secondary cache
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R10000 event counter - quadwords written back from secondary cache.
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This counter is incremented once each cycle that a quadword of data is
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written back from the secondary cache to the outgoing buffer located in
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the on-chip system-interface unit, and hw.r10kevctr.scache.wb is the
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sum over all CPUs.
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@ hw.r10kevctr.scache.ecc R10000 event counter - single-bit ECC errors on secondary cache data
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R10000 event counter - single-bit ECC errors on secondary cache data.
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This counter is incremented on the cycle after the correction of a
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single-bit error on a quadword read from the secondary cache data
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array, and hw.r10kevctr.scache.ecc is the sum over all CPUs.
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@ hw.r10kevctr.pcache.imiss R10000 event counter - primary cache instruction misses
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R10000 event counter - primary cache instruction misses.
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This counter is incremented one cycle after an instruction refill
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request is sent to the Secondary Cache Transaction Processing logic.
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hw.r10kevctr.pcache.imiss is the sum over all CPUs.
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@ hw.r10kevctr.scache.imiss R10000 event counter - secondary cache instruction misses
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R10000 event counter - secondary cache instruction misses.
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This counter is incremented the cycle after the last quadword of a
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primary instruction cache line is written from the main memory, while
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the secondary cache refill continues.
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hw.r10kevctr.scache.imiss is the sum over all CPUs.
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@ hw.r10kevctr.scache.iwaymp R10000 event counter - secondary cache instruction way misprediction
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R10000 event counter - secondary cache instruction way misprediction.
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This counter is incremented when the secondary cache controller begins
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to retry an access to the secondary cache after it hit in the
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non-predicted way, provided the secondary cache access was initiated by
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the primary instruction cache.
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hw.r10kevctr.scache.iwaymp is the sum over all CPUs.
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@ hw.r10kevctr.extint R10000 event counter - external intervention requests
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R10000 event counter - external intervention requests.
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This counter is incremented on the cycle after an external intervention
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request enters the Secondary Cache Transaction Processing logic.
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hw.r10kevctr.extint is the sum over all CPUs.
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@ hw.r10kevctr.extinv R10000 event counter - external invalidate requests
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R10000 event counter - external invalidate requests.
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This counter is incremented on the cycle after an external invalidate
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request enters the Secondary Cache Transaction Processing logic.
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hw.r10kevctr.extinv is the sum over all CPUs.
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@ hw.r10kevctr.vcc R10000 event counter - virtual coherency condition
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R10000 event counter - virtual coherency condition.
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This counter is incremented on the cycle after a virtual address
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coherence condition is detected, provided that the access was not
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flagged as a miss. This condition can only be realized for virtual
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page sizes of 4 Kbyte.
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hw.r10kevctr.vcc is the sum over all CPUs, but is not available for
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R10000 CPUs at rev 3.x or later, where this event is replaced by
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hw.r10kevctr.fucomp.
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@ hw.r10kevctr.fucomp R10000 event counter - ALU/FPU completion cycles
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R10000 event counter that accumulates the number ALU/FPU completion
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cycles.
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This counter is incremented on the cycle after either ALU1, ALU2, FPU1,
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or FPU2 marks an instruction as "done."
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hw.r10kevctr.fucomp is the sum over all CPUs, but is only available for
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R10000 CPUs at rev 3.x or later, where this event replaces
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hw.r10kevctr.vcc that was available on the earlier revisions of the
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R10000 CPUs.
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@ hw.r10kevctr.grad.instrg R10000 event counter - instructions graduated
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R10000 event counter - instructions graduated.
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This counter is incremented by the number of instructions that were
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graduated on the previous cycle. When an integer multiply or divide
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instruction graduates, it is counted as two graduated instructions.
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hw.r10kevctr.grad.instrg is the sum over all CPUs.
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@ hw.r10kevctr.grad.loadg R10000 event counter - loads graduated
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R10000 event counter - loads graduated.
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In rev 2.x, if a store graduates on a given cycle, all loads which
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graduate on that cycle do not increment this counter. Prefetch
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instructions are included in this count.
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In rev 3.x this behavior is changed so that all graduated loads (loads,
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prefetches, sync and cacheops) are counted as they graduated on the
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previous cycle. Up to four of these instructions can graduate in one
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cycle.
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hw.r10kevctr.grad.loadg is the sum over all CPUs.
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@ hw.r10kevctr.grad.storeg R10000 event counter - stores graduated
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R10000 event counter - stores graduated.
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Each graduating store (including store-conditionals) increments the
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counter. At most one store can graduate per cycle.
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hw.r10kevctr.grad.storeg is the sum over all CPUs.
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@ hw.r10kevctr.grad.scondg R10000 event counter - store conditionals graduated
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R10000 event counter - store conditionals graduated.
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At most, one store-conditional can graduate per cycle. This counter is
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incremented on the cycle following the graduation of a
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store-conditional instruction. Both failed and successful
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store-conditional instructions are included in this count; so
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successful store-conditionals can be determined as the difference
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between this metric and hw.r10kevctr.fail.scondf.
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hw.r10kevctr.grad.scondg is the sum over all CPUs.
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@ hw.r10kevctr.grad.fp R10000 event counter - floating point instructions graduated
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R10000 event counter - floating point instructions graduated.
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This counter is incremented by the number of FP instructions which
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graduated on the previous cycle. Any instruction that sets the FP
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Status register bits (EVZOUI) is counted as a graduated floating point
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instruction. There can be 0 to 4 such instructions each cycle.
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Note that conditional-branches based on FP condition codes and
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Floating-point load and store instructions are not included in this
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count.
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hw.r10kevctr.grad.fp is the sum over all CPUs.
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@ hw.r10kevctr.pcache.wb R10000 event counter - quadwords written back from primary cache
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R10000 event counter - quadwords written back from primary cache.
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This counter is incremented once each cycle that a quadword of data is
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valid and being written from primary data cache to secondary cache, and
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hw.r10kevctr.pcache.wb is the sum over all CPUs.
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@ hw.r10kevctr.tlb R10000 event counter - TLB refill exceptions
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R10000 event counter - TLB refill exceptions.
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This counter is incremented on the cycle after the TLB miss handler is
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invoked. All TLB misses are counted, whether they occur in the native
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code or within the TLB handler.
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hw.r10kevctr.tlb is the sum over all CPUs.
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@ hw.r10kevctr.fail.brmp R10000 event counter - branches mispredicted
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R10000 event counter - branches mispredicted.
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This counter is incremented on the cycle after a branch is restored
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because of misprediction. The misprediction is determined on the same
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cycle that the conditional branch is resolved.
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For rev 3.x, the misprediction rate is the ratio of the branch
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mispredicted count to the conditional branch resolved.
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For rev 2.x, the misprediction rate cannot be precisely determined,
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because the decoded branches count includes unconditional branches as
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well as conditional branches which are never resolved (due to prior
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mispredictions or later interrupts).
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hw.r10kevctr.fail.brmp is the sum over all CPUs.
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@ hw.r10kevctr.pcache.dmiss R10000 event counter - primary cache data misses
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R10000 event counter - primary cache data misses.
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This counter is incremented one cycle after a request to refill a line
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of the primary data cache is entered into the Secondary Cache
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Transaction Processing logic.
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hw.r10kevctr.pcache.dmiss is the sum over all CPUs.
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@ hw.r10kevctr.scache.dmiss R10000 event counter - secondary cache data misses
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R10000 event counter - secondary cache data misses.
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This counter is incremented the cycle after the second quadword of a
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data cache line is written from the main memory, while the secondary
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cache refill continues.
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hw.r10kevctr.scache.dmiss is the sum over all CPUs.
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@ hw.r10kevctr.scache.dwaymp R10000 event counter - secondary cache data way misprediction
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R10000 event counter - secondary cache data way misprediction.
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This counter is incremented when the secondary cache controller begins
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to retry an access to the secondary cache because it hit in the
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non-predicted way, provided the secondary cache access was initiated by
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the primary data cache.
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hw.r10kevctr.scache.dwaymp is the sum over all CPUs.
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@ hw.r10kevctr.scache.extinthit R10000 event counter - external intervention hits in secondary cache
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R10000 event counter - external intervention hits in secondary cache.
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This counter is incremented on the cycle after an external intervention
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request is determined to have hit in the secondary cache, and
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hw.r10kevctr.scache.extinthit is the sum over all CPUs.
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@ hw.r10kevctr.scache.extinvhit R10000 event counter - external invalidate hits in secondary cache
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R10000 event counter - external invalidate hits in secondary cache.
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This counter is incremented on the cycle after an external invalidate
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request is determined to have hit in the secondary cache, amd
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hw.r10kevctr.scache.extinvhit is the sum over all CPUs.
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@ hw.r10kevctr.scache.upclean R10000 event counter - upgrade requests on clean secondary cache lines
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R10000 event counter - upgrade requests on clean secondary cache lines.
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This counter is incremented on the cycle after a request to change the
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Clean Exclusive state of the targeted secondary cache line to Dirty
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Exclusive is sent to the Secondary Cache Transaction Processing logic.
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hw.r10kevctr.scache.upclean is the sum over all CPUs.
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@ hw.r10kevctr.scache.upshare R10000 event counter - upgrade requests on shared secondary cache lines
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R10000 event counter - upgrade requests on shared
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secondary cache lines.
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This counter is incremented on the cycle after a request to change the
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Shared state of the targeted secondary cache line to Dirty Exclusive is
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sent to the Secondary Cache Transaction Processing logic.
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hw.r10kevctr.scache.upshare is the sum over all CPUs.
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