159 lines
3.6 KiB
C
159 lines
3.6 KiB
C
/***********************************************************************\
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* File: pod_proc2.c *
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* *
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* Contains the code run on the second processor in 2 cpu/2f/2vme *
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* configuration. *
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* *
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\***********************************************************************/
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#ident "arcs/IO4prom/pod_proc2.c $Revision: 1.3 $"
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#include "pod_fvdefs.h"
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unsigned proc2_data[SLAVE_DATA];
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unsigned p2Dma_rd[SLAVE_DATA], p2Dma_wr[SLAVE_DATA];
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int p2Dma_state;
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volatile unsigned Proc2_start=0;
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extern int svmecc_piolpbk(unsigned, int, int);
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caddr_t Mapram2=0;
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int
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proc2_op(int window, int anum)
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{
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/* Define the operations to be carried out by the slave processor
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* Planning to use this facility to stress the VMECC.
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*/
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__psunsigned_t chip_base, i;
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pod_initialize();
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/* Wait till you are asked to start */
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while(Proc2_start != VMECC_SETUP);
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print_hex(0xfed);
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chip_base = SWIN_BASE(window, anum);
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p2Dma_state = 0;
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if ((Mapram2 == 0) && ((Mapram2 = tlbentry(window, 0, 0)) == (caddr_t)0)){
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Return(0xbeefed);
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}
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fchip_init(window, anum);
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WR_REG(chip_base+VMECC_CONFIG, VMECC_CONFIG_VALUE);
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setup_lpbk(chip_base, window, anum, Mapram2);
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p2vmecc_lpbk(chip_base, window, anum);
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p2vmecc_lpbk(chip_base, window, anum); /* Do it again possibly */
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p2vmecc_lpbk(chip_base, window, anum); /* Do it again possibly */
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tlbrmentry(Mapram2); Mapram2 = 0;
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}
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int
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p2vmecc_lpbk(__psunsigned_t chip_base, int window, int ioa_num)
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{
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unsigned value, error=0, slave_offset;
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caddr_t vaddr;
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volatile unsigned *vvaddr;
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jmp_buf jbuf, *obuf;
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int i;
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#ifdef DEBUG_POD
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print_hex(0xbece);
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#endif
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vaddr = tlbentry(window, ioa_num, 0x02000000);
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slave_offset = (K0_TO_PHYS(proc2_data) & (LW_VPAGESIZE - 1));
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/* Slave would just do a lot of 1 level rd/write to A32 space */
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/* Pump the writes first */
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vvaddr = (unsigned *) (vaddr + slave_offset);
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for (i=0; i < SLAVE_DATA; i++, vvaddr++ ){
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*(vvaddr) = (unsigned) (&proc2_data[i]);
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if ((i % 8) == 0)
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vmep2_sl_dmaop(chip_base);
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}
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vvaddr = (unsigned *) (vaddr + slave_offset);
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for (i=0; i < 4 ; i++, vvaddr++){
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value = *(vvaddr );
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#ifdef DEBUG_POD
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print_hex(value);
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#endif
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if (value != (unsigned)(&proc2_data[i])){
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error++;
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}
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vmep2_sl_dmaop(chip_base);
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}
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tlbrmentry(vaddr);
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Return (error);
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}
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/* DMA initalization and management for a second processor */
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int
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vmep2_sl_dmaop(__psunsigned_t chip_base)
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{
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/* Do a DMA Write to the Slave Memory, Poll for it completion
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* and then, do a DMA read from the same address, compare the
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* data
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*/
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unsigned status;
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again:
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switch(p2Dma_state){
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case 0 : vmecc_sl_dmawr(chip_base, p2Dma_rd, Mapram2);
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p2Dma_state++; break;
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case 1 :
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case 3 :
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/* Check if DMA has completed */
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status = RD_REG(chip_base+VMECC_DMAPARMS);
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if (status & (unsigned)0x80000000)
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break; /* Not over yet */
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if (status & (unsigned)0x60000000){
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p2Dma_state = DMA_DONE;
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print_hex(status);
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break; /* Error Case */
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}
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p2Dma_state++;
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goto again; /* Why not take further action here ?? */
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case 2 : vmecc_sl_dmard(chip_base, p2Dma_wr, Mapram2);
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p2Dma_state++; break;
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/* Successfull state */
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case 4 : print_hex(0xeeeeeeee);
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p2Dma_state = 0; goto again; /* Do it again */
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/* p2Dma_state = DMA_DONE; break; */
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case DMA_DONE : break;
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default: print_hex((0xaaaaaa<<4) | p2Dma_state); break;
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}
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Return(0xcac0 | p2Dma_state);
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}
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