calmsacibis995
608 lines
24 KiB
Plaintext
608 lines
24 KiB
Plaintext
IF IN MANUFACTURE MODE
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======================
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*** G-cache parity error: CAUSE 00030000
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Reason for entering POD mode: POD mode switch set or POD key pressed.
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POD 0b/00> Gcache TAG ADDR test for sets 0, 1, 2 PASSED
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Gcache TAG DATA test for sets 0, 1, 2 PASSED
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Gcache RAM DATA test for sets 0, 1, 2 PASSED
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Gcache TAG ADDR test for set 3 PASSED
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Gcache TAG DATA test for set 3 PASSED
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Gcache RAM DATA test for set 3 PASSED
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Dcache tag test pass
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Welcome to Everest manufacturing mode.
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Initializing master IO4...
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Testing master IA chip registers (slot 0c)...
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Testing map RAM in master IO4's IA chip (slot 0c)...
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Testing master EPC (slot 0c, adap 01)...
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Initializing EPC UART...
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IP21 PROM (BE) SGI Version 5 built 04:22:15 PM Jul 20, 1994
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-- USING SYS. CTLR. UART --
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-- POD MODE ENABLED --
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Initializing hardware inventory... ...done.
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CPU 11/00 is bootmaster
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Testing and clearing bus tags... ...passed.
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Configuring memory...
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Using standard interleave algorithm.
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Running built-in memory test... 10
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...passed.
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Writing cfginfo to memory
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Initializing MPCONF blocks
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Checking CC Join... ...passed.
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Checking CC Write Gatherer... ...passed.
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Checking EAROM... ...passed.
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Checking slave processor diag results...
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Checking FPU... ... passed.
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Enabled 64 Megabytes of main memory
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Enabled 2 processors
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Entering POD mode.
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Reason for entering POD mode: POD mode switch set or POD key pressed.
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.......
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IP21 PROM (BE) SGI Version 5 built 10:47:48 AM Jul 21, 1994
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Initializing hardware inventory... ...done.
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CPU 11/00 is bootmaster
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Testing and clearing bus tags... ...passed.
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Configuring memory...
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Using standard interleave algorithm.
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Running built-in memory test... 10
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...passed.
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Writing cfginfo to memory
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Initializing MPCONF blocks
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Checking CC Join... ...passed.
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Checking CC Write Gatherer... ...passed.
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Checking EAROM... ...passed.
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Checking slave processor diag results...
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Checking FPU... ... passed.
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Enabled 64 Megabytes of main memory
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Enabled 2 processors
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Downloading PROM header information...
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Downloading PROM code...
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Jumping into IO4 PROM.
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PROM Segment Loader SGI Version 1.0 Rev A MIPS3, Jun 6, 1994
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Loading and executing R8000 boot prom image...
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IO4 PROM Monitor SGI Version 3.01 Rev A IP21, Jun 6, 1994 (BE64)
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Sizing caches...
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Initializing exception vectors.
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Initializing IO4 subsystems.
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Fixing vpids...
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Initializing environment
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Initializing software and devices.
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Initializing write-gatherer...
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Initializing write-gatherer...
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Initializing write-gatherer...
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All initialization and diagnostics completed.
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Bootmaster processor already started.
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Starting processor #1
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Comparing EAROM checksums...
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Checking hardware inventory...
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System Maintenance Menu
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1) Start System
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2) Install System Software
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3) Run Diagnostics
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4) Recover System
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5) Enter Command Monitor
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Option?
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During POD MODE:
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POD 0b/00> help
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All numerical inputs should be in hex with or without 0x preceding them.
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Commands may be separated by semicolons, and loops may be nested.
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Write byte: wb ADDRESS NUMBER
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Write halfword: wh ADDRESS NUMBER
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Write word: ww ADDRESS NUMBER
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Write double: wd ADDRESS NUMBER
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Display byte: db ADDRESS
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Display halfword: dh ADDRESS
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Display word: dw ADDRESS
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Display double: dd ADDRESS
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Display niblet master debug buffer: dm NUMBER
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Display niblet slave debug buffer: ds NUMBER
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Display register: dr <sr || sp || all>
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Write register: wr < sr >
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'scope loop: sloop (COMMAND)
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Finite loop: loop TIMES (COMMAND)
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Slot contents: info
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Mem diagnostic: mem LOADDR HIADDR
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Jump to address: j ADDRESS
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Jump to address: j1 ADDRESS PARAM1
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Jump to address: j2 ADDRESS PARAM1 PARAM2
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Disp. config reg: dc SLOT REGNUM
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Write config reg: wc SLOT REGNUM VALUE
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Disp mem bd regs: dmc SLOT
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Disp io brd regs: dio SLOT
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Reset the system: reset
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Run Niblet: niblet <0 - 9>
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Send interrupt: si SLOT CPU LEVEL
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Clear TLB: flusht
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Dump TLB: td <index | all>
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Clear State: clear
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Decode Address: decode PHYSADDR
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Walk a bit: walk <loaddr> <hiaddr> <cont on fails>
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Dump dcache tag: dtag addr
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Dump scache tag: stag PHYSADDR
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Dump scache tags: staga state_mask
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Dump dcache tags: dtaga state_mask
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Goto slave mode: slave
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Set Page Size: setpg PAGESIZE
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Show Page Size: showpg
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Download IO PROM: io
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Why are we here?: why
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Disable unit: disable SLOT UNIT
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Enable unit: enable SLOT UNIT
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Force disable: fdisable SLOT UNIT
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Force enable: fenable SLOT UNIT
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Display config: devc SLOT | all
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Reinit inventory: zap
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Display MPCONF: dmpc VPID
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Fix EAROM cksum: fixcksum
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Show EAROM cksum: cksum
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G$ Parity Range: gparity_r LOADDR HIADDR
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G$ Parity: gparity
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D 0b/00> info
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System physical configuration:
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Slot 01: Empty
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Slot 02: Empty
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Slot 03: Empty
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Slot 04: Empty
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Slot 05: Empty
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Slot 06: Empty
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Slot 07: Empty
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Slot 08: Empty
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Slot 09: Empty
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Slot 0a: Memory board
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Slot 0b: CPU board
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Slot 0c: I/O board
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This processor is slot 0b, cpu 00.
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POD 0b/00> devc all
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Memory size: 64 M
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Bus clock frequency: 47 MHz
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Virtual dip switches: 0x00001400
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Slot 0x01: Type = 0x00, Name = EMPTY
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Rev: 0 Inventory: 0x00000000 Diag Value: 0x00000000, Enabled
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Slot 0x02: Type = 0x00, Name = EMPTY
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Rev: 0 Inventory: 0x00000000 Diag Value: 0x00000000, Enabled
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Slot 0x03: Type = 0x00, Name = EMPTY
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Rev: 0 Inventory: 0x00000000 Diag Value: 0x00000000, Enabled
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Slot 0x04: Type = 0x00, Name = EMPTY
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Rev: 0 Inventory: 0x00000000 Diag Value: 0x00000000, Enabled
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Slot 0x05: Type = 0x00, Name = EMPTY
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Rev: 0 Inventory: 0x00000000 Diag Value: 0x00000000, Enabled
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Slot 0x06: Type = 0x00, Name = EMPTY
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Rev: 0 Inventory: 0x00000000 Diag Value: 0x00000000, Enabled
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Slot 0x07: Type = 0x00, Name = EMPTY
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Rev: 0 Inventory: 0x00000000 Diag Value: 0x00000000, Enabled
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Slot 0x08: Type = 0x00, Name = EMPTY
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Rev: 0 Inventory: 0x00000000 Diag Value: 0x00000000, Enabled
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Slot 0x09: Type = 0x00, Name = EMPTY
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Rev: 0 Inventory: 0x00000000 Diag Value: 0x00000000, Enabled
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Slot 0x0a: Type = 0x31, Name = MC3
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Rev: 16 Inventory: 0x00000031 Diag Value: 0x00000000, Enabled
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Bank 0: IP 0, IF 0, SIMM type 1, Bloc 0x00000000
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Inventory 0x01, DiagVal 0x00, Enabled
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Bank 1: Not populated.
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Bank 2: Not populated.
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Bank 3: Not populated.
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Bank 4: Not populated.
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Bank 5: Not populated.
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Bank 6: Not populated.
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Bank 7: Not populated.
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Slot 0x0b: Type = 0x12, Name = IP21
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Rev: 3 Inventory: 0x00000012 Diag Value: 0x00000000, Enabled
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CPU 0: Inventory 0x00, DiagVal 0x00, Info 0x00
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Virt. #0, Speed 75 MHz, Cache Size 4096 kB, Prom rev 5, Enabled
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CPU 1: Inventory 0x00, DiagVal 0x00, Info 0x00
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Virt. #1, Speed 75 MHz, Cache Size 4096 kB, Prom rev 5, Enabled
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Slot 0x0c: Type = 0x21, Name = IO4
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Rev: 2 Inventory: 0x00000021 Diag Value: 0x00000000, Enabled
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Window Number: 1
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PADAP 1: EPC (0x0e), Inventory 0x0e, DiagVal 0x00, VirtID 0, Enabled
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PADAP 2: F (0x0f), Inventory 0x0f, DiagVal 0x00, VirtID 0, Enabled
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PADAP 3: F (0x0f), Inventory 0x0f, DiagVal 0x00, VirtID 0, Enabled
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PADAP 4: S1 (0x0d), Inventory 0x0d, DiagVal 0x00, VirtID 0, Enabled
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PADAP 5: Not populated.
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(0x00), Inventory 0x00, DiagVal 0x00, VirtID 0, Enabled
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PADAP 6: Not populated.
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(0x00), Inventory 0x00, DiagVal 0x00, VirtID 0, Enabled
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PADAP 7: Not populated.
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(0x00), Inventory 0x00, DiagVal 0x00, VirtID 0, Enabled
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POD 0b/00> dr all
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r00: 0000000000000000 r01: 0000000008000000 r02: 0000000000000000
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r03: 0000000000000000 r04: 00000000000000dc r05: 0000000000000000
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r06: 0000000000000000 r07: 800000041fc2f940 r08: ffffffffffff8008
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r09: a80000000186efa5 r10: a80000000181eb20 r11: a80000000186e8e8
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r12: a800000001802470 r13: 0000000000000000 r14: 0000000000000146
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r15: 0000000000000000 r16: a800000001800998 r17: 0000000000000000
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r18: a8000000018bd6a8 r19: a8000000018bd688 r20: a800000001967be0
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r21: a800000001967ed0 r22: 128889416c4318d4 r23: a8000000018d1d98
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r24: a80000000186efb4 r25: 0000000000000054 r26: 9000000000000400
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r27: 0000000000000000 r28: 0000000000000008 r29: a800000001967a30
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r30: a8000000018d1dc0 r31: a800000001812140 BVA: a8000000000ffff0
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EPC: a800000001812190 SR: 0000002224077c00
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Cause: 0000000008030800 ( INT:----4--- )
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POD 0b/00> dr sr
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SR: 0000002224077c00
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POD 0b/00> dr sp
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SP: a8000000000ff928
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POD 0b/00> sloop (dr sp)
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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SP: a8000000000ff698
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POD 0b/00> wb 9000000000090000 1
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9000000000090000: 01
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9000000000090001: 2
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9000000000090001: 02
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9000000000090002: 3
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9000000000090002: 03
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9000000000090003: 4
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9000000000090003: 04
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9000000000090004: n
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POD 0b/00> db 9000000000090000 1
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9000000000090000: 01
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9000000000090001: 02
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9000000000090002: 03
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9000000000090003: 04
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9000000000090004: 00 n
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*** Invalid POD command: '1'
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POD 0b/00> wh 9000000000700000 2
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9000000000700000: 0002
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9000000000700002: 4
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9000000000700002: 0004
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9000000000700004: 6
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9000000000700004: 0006
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9000000000700006: 8
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9000000000700006: 0008
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9000000000700008: n
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POD 0b/00> dh 0x9000000000700000
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9000000000700000: 0002
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9000000000700002: 0004
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9000000000700004: 0006
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9000000000700006: 0008
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9000000000700008: 0000 n
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POD 0b/00> ww 9000000000700080 10
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9000000000700080: 00000010
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9000000000700084: 20
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9000000000700084: 00000020
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9000000000700088: 100
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9000000000700088: 00000100
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900000000070008c: 1000
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900000000070008c: 00001000
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9000000000700090: n
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POD 0b/00> dw 9000000000700080
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9000000000700080: 00000010
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9000000000700084: 00000020 n
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D 0b/00> wr sr 0
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POD 0b/00> dr sr
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SR: 0000000000000000
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POD 0b/00> loop 2 (dr sr)
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SR: 0000000000000000
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SR: 0000000000000000
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POD 0b/00> mem 9000000000600000 900000000060f000
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Walking address... Passed!
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Read/Write Test...... Passed!
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Addr Pattern Test... Passed!
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POD 0b/00> dc b 0
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Slot 0b, Reg 00: 000000000000000f
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POD 0b/00> dc b 1
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Slot 0b, Reg 01: 0000000000000001
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POD 0b/00> dc b 2
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Slot 0b, Reg 02: 0000000000000003
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POD 0b/00> dmc a
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Configuration of the memory board in slot 0a
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EBus Error: 00000000
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Leaf Enable: 0000000f
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Bank Enable: 00000001
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BIST Result: 00000000
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Leaf 0:
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BIST = 00014000, Error = 00000000, ErrAddrHi = 00000000, ErrAddrLo = 00000000
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Syndrome 0: 0000, Syndrome 1: 0000, Syndrome 2: 0000, Syndrome 3: 0000
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Bank 0: Size = 00000001, Base = 00000000, IF = 00000000, IP = 00000000
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Bank 1: Size = 00000007, Base = 00000000, IF = 00000000, IP = 00000000
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Bank 2: Size = 00000007, Base = 00000000, IF = 00000000, IP = 00000000
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Bank 3: Size = 00000007, Base = 00000000, IF = 00000000, IP = 00000000
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Leaf 1:
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BIST = 00000000, Error = 00000000, ErrAddrHi = 00000000, ErrAddrLo = 00000000
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Syndrome 0: 0000, Syndrome 1: 0000, Syndrome 2: 0000, Syndrome 3: 0000
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Bank 0: Size = 00000007, Base = 00000000, IF = 00000000, IP = 00000000
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Bank 1: Size = 00000007, Base = 00000000, IF = 00000000, IP = 00000000
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Bank 2: Size = 00000007, Base = 00000000, IF = 00000000, IP = 00000000
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Bank 3: Size = 00000007, Base = 00000000, IF = 00000000, IP = 00000000
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POD 0b/00> reset
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IP21 PROM (BE) SGI Version 5 built 10:47:48 AM Jul 21, 1994
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-- POD MODE ENABLED --
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Initializing hardware inventory... ...done.
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CPU 11/00 is bootmaster
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Testing and clearing bus tags... ...passed.
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Configuring memory...
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Using standard interleave algorithm.
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Running built-in memory test... 10
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...passed.
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Writing cfginfo to memory
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Initializing MPCONF blocks
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Checking CC Join... ...passed.
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Checking CC Write Gatherer... ...passed.
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Checking EAROM... ...passed.
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Checking slave processor diag results...
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Checking FPU... ... passed.
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Enabled 64 Megabytes of main memory
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Enabled 2 processors
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Entering POD mode.
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Reason for entering POD mode: POD mode switch set or POD key pressed.
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POD 0b/00> si 2 1 1
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POD 0b/00> td 1
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01/00: hi c000000000400000 lo 00000000 <PID 00000000 V c000000000404000 P 00000000 Uncached CPU>
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01/01: hi c000000000200000 lo 00000000 <PID 00000000 V c000000000204000 P 00000000 Uncached CPU>
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01/02: hi c000000000000000 lo 00000000 <PID 00000000 V c000000000004000 P 00000000 Uncached CPU>
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POD 0b/00> clear
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Cleared CPU error state.
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Cleared memory board 0a's error registers
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Cleared memory error state.
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Cleared IO board 0c's error registers
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Cleared IO error state.
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POD 0b/00> decode 0x7ffffffff000
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7ffffffff000 decodes to slot 0x0a, leaf 0, bank 0 (A)
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POD 0b/00> decode 8
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00000008 decodes to slot 0x0a, leaf 0, bank 0 (A)
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POD 0b/00> decode 0x99800
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00099800 decodes to slot 0x0a, leaf 0, bank 0 (A)
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POD 0b/00> walk 0x100 0x3ff0 1
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Converting to uncached, unmapped addresses (9000000000000100 to 9000000000003ff0)
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Test Passed.
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POD 0b/00> dtag 9000000001880000
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virtual addr at == 9000000001880000
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Tag == 000000fc
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Valid bits == 00000000
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POD 0b/00> walk 0x100 0x3ff0 1
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Converting to uncached, unmapped addresses (9000000000000100 to 9000000000003ff0)
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Test Passed.
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POD 0b/00> dtag 9000000001880000
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virtual addr at == 9000000001880000
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Tag == 000000fc
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Valid bits == 00000000
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POD 0b/00> slave
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Invalidating I and D Caches
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Jumping to 800000041fc03748
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slave
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Invalidating I and D Caches
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Jumping to 800000041fc03748
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POD 0b/00> showpg
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Page size: 00004000 bytes
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POD 0b/00> why
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Reason for entering POD mode: POD mode switch set or POD key pressed.
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POD 0b/00> disable b 1
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CPU 0b/01 disabled.
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POD 0b/00> devc b
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Slot 0x0b: Type = 0x12, Name = IP21
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Rev: 3 Inventory: 0x00000012 Diag Value: 0x00000000, Enabled
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CPU 0: Inventory 0x00, DiagVal 0x00, Info 0x00
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Virt. #0, Speed 75 MHz, Cache Size 4096 kB, Prom rev 5, Enabled
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CPU 1: Inventory 0x00, DiagVal 0x00, Info 0x00
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Virt. #1, Speed 75 MHz, Cache Size 4096 kB, Prom rev 5, Disabled
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POD 0b/00> enable b 1
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CPU 0b/01 enabled.
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POD 0b/00> devc b
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Slot 0x0b: Type = 0x12, Name = IP21
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Rev: 3 Inventory: 0x00000012 Diag Value: 0x00000000, Enabled
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CPU 0: Inventory 0x00, DiagVal 0x00, Info 0x00
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Virt. #0, Speed 75 MHz, Cache Size 4096 kB, Prom rev 5, Enabled
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CPU 1: Inventory 0x00, DiagVal 0x00, Info 0x00
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Virt. #1, Speed 75 MHz, Cache Size 4096 kB, Prom rev 5, Enabled
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POD 0b/00> dmpc 1
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MPCONF entry for VPID 01 (0x9000000000003040):
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Magic: ffffffffbaddeed2
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EAROM cksum: 22e5
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Saved cksum: 22e5
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Phys ID: 0b/01
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Virt ID: 01
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Launch: 00000000
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Launch parm: 00000000
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CPU Rev: 00001021
|
|
POD 0b/00> fixcksum
|
|
EAROM checksum is 22e5
|
|
POD 0b/00> gparity_r a800000001000000 a800000001800000
|
|
Starting G-cache parity test... Starting Address = a800000001000000... Ending Address = a800000001800000...
|
|
...Memory Initialized...
|
|
...Memory verified...
|
|
...done
|
|
POD 0b/00> gparity
|
|
Starting G-cache parity test... Starting Address = a800000001000000... Ending Address = a800000001800000...
|
|
...Memory Initialized...
|
|
...Memory verified...
|
|
POD 0b/00> gparity_r a800000001000000 a800000001800000
|
|
Starting G-cache parity test... Starting Address = a800000001000000... Ending Address = a800000001800000...
|
|
...Memory Initialized...
|
|
...Memory verified...
|
|
...done
|
|
POD 0b/00> gparity
|
|
Starting G-cache parity test... Starting Address = a800000001000000... Ending Address = a800000001800000...
|
|
...Memory Initialized...
|
|
...Memory verified...
|
|
...done
|
|
POD 0b/00> zap
|
|
POD 0b/00> gm
|
|
Reason for entering POD mode: POD mode switch set or POD key pressed.�AlCԨ
|
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Mem 0b/00> niblet 0
|
|
nib_kern: *(a800000000100000) == nib_exc_start
|
|
nib_kern: *(a800000000100c30) == nib_text_start
|
|
nib_kern: *(a800000000105cc8) == nib_text_entry
|
|
nib_kern: *(a800000000107240) == nib_data_start
|
|
nib_kern: *(00000000) == nib_bss_start
|
|
nib_kern: *(00000000) == nib_bss_end
|
|
prg_code: p1 *(a80000000010c000) == section .text, 0x00000014 words
|
|
prg_code: Padding text section from 0 to code start point 0x00000120
|
|
shrd_mem: *(a80000000010d000) == SHMEM start (size = 00008000)
|
|
shrd_mem: *(a800000000114fff) == SHMEM end
|
|
page_tbl: p1 *(a800000000115000) == 0010cb80 (.text VPN 0x00000000 PFN 0x0000010c)
|
|
page_tbl: p1 *(a800000000116800) == 0010db80 (SHARED VPN 0x00000300 PFN 0x0000010d)
|
|
page_tbl: p1 *(a800000000116808) == 0010eb80 (SHARED VPN 0x00000301 PFN 0x0000010e)
|
|
page_tbl: p1 *(a800000000116810) == 0010fb80 (SHARED VPN 0x00000302 PFN 0x0000010f)
|
|
page_tbl: p1 *(a800000000116818) == 00110b80 (SHARED VPN 0x00000303 PFN 0x00000110)
|
|
page_tbl: p1 *(a800000000116820) == 00111b80 (SHARED VPN 0x00000304 PFN 0x00000111)
|
|
page_tbl: p1 *(a800000000116828) == 00112b80 (SHARED VPN 0x00000305 PFN 0x00000112)
|
|
page_tbl: p1 *(a800000000116830) == 00113b80 (SHARED VPN 0x00000306 PFN 0x00000113)
|
|
page_tbl: p1 *(a800000000116838) == 00114b80 (SHARED VPN 0x00000307 PFN 0x00000114)
|
|
proc_tbl: p1 *(a800000000117000) == tests/LONG/invalid PROC. Entry = 00000120
|
|
Slot 0b CPU 00
|
|
Slot 0b CPU 01
|
|
--> Niblet (a800000000105cc8)
|
|
******************************************************************
|
|
|
|
9000000000700084: 00000020 n
|
|
|
|
Mem 0b/00> niblet 0
|
|
nib_kern: *(a800000000100000) == nib_exc_start
|
|
nib_kern: *(a800000000100c30) == nib_text_start
|
|
nib_kern: *(a800000000105cc8) == nib_text_entry
|
|
nib_kern: *(a800000000107240) == nib_data_start
|
|
nib_kern: *(00000000) == nib_bss_start
|
|
nib_kern: *(00000000) == nib_bss_end
|
|
prg_code: p1 *(a80000000010c000) == section .text, 0x00000014 words
|
|
prg_code: Padding text section from 0 to code start point 0x00000120
|
|
shrd_mem: *(a80000000010d000) == SHMEM start (size = 00008000)
|
|
shrd_mem: *(a800000000114fff) == SHMEM end
|
|
page_tbl: p1 *(a800000000115000) == 0010cb80 (.text VPN 0x00000000 PFN 0x0000010c)
|
|
page_tbl: p1 *(a800000000116800) == 0010db80 (SHARED VPN 0x00000300 PFN 0x0000010d)
|
|
page_tbl: p1 *(a800000000116808) == 0010eb80 (SHARED VPN 0x00000301 PFN 0x0000010e)
|
|
page_tbl: p1 *(a800000000116810) == 0010fb80 (SHARED VPN 0x00000302 PFN 0x0000010f)
|
|
page_tbl: p1 *(a800000000116818) == 00110b80 (SHARED VPN 0x00000303 PFN 0x00000110)
|
|
page_tbl: p1 *(a800000000116820) == 00111b80 (SHARED VPN 0x00000304 PFN 0x00000111)
|
|
page_tbl: p1 *(a800000000116828) == 00112b80 (SHARED VPN 0x00000305 PFN 0x00000112)
|
|
page_tbl: p1 *(a800000000116830) == 00113b80 (SHARED VPN 0x00000306 PFN 0x00000113)
|
|
page_tbl: p1 *(a800000000116838) == 00114b80 (SHARED VPN 0x00000307 PFN 0x00000114)
|
|
proc_tbl: p1 *(a800000000117000) == tests/LONG/invalid PROC. Entry = 00000120
|
|
Slot 0b CPU 00
|
|
Slot 0b CPU 01
|
|
--> Niblet (a800000000105cc8)
|
|
******************************************************************
|
|
0000000000005656
|
|
0000000000000000
|
|
Master CPU: 0000000000000000
|
|
a800000000117000
|
|
a800000000107850
|
|
Number of processes active:
|
|
0000000000000001
|
|
0000000000000120
|
|
0000000000000001> 0000000010101001
|
|
0000000000000001> 0000000000000190
|
|
Test passed
|
|
Process number:
|
|
0000000000000001
|
|
Supertest PASSED.
|
|
|
|
Niblet Complete.
|
|
Mem 0b/00> niblet 9
|
|
nib_kern: *(a800000000100000) == nib_exc_start
|
|
nib_kern: *(a800000000100c30) == nib_text_start
|
|
nib_kern: *(a800000000105cc8) == nib_text_entry
|
|
nib_kern: *(a800000000107240) == nib_data_start
|
|
nib_kern: *(00000000) == nib_bss_start
|
|
nib_kern: *(00000000) == nib_bss_end
|
|
prg_code: p1 *(a80000000010c000) == section .text, 0x00000056 words
|
|
prg_code: Padding text section from 0 to code start point 0x00000120
|
|
prg_code: p2 *(a80000000010d000) == section .text, 0x00000056 words
|
|
prg_code: Padding text section from 0 to code start point 0x00000120
|
|
shrd_mem: *(a80000000010e000) == SHMEM start (size = 00008000)
|
|
shrd_mem: *(a800000000115fff) == SHMEM end
|
|
page_tbl: p1 *(a800000000116000) == 0010cb80 (.text VPN 0x00000000 PFN 0x0000010c)
|
|
page_tbl: p1 *(a800000000117800) == 0010eb80 (SHARED VPN 0x00000300 PFN 0x0000010e)
|
|
page_tbl: p1 *(a800000000117808) == 0010fb80 (SHARED VPN 0x00000301 PFN 0x0000010f)
|
|
page_tbl: p1 *(a800000000117810) == 00110b80 (SHARED VPN 0x00000302 PFN 0x00000110)
|
|
page_tbl: p1 *(a800000000117818) == 00111b80 (SHARED VPN 0x00000303 PFN 0x00000111)
|
|
page_tbl: p1 *(a800000000117820) == 00112b80 (SHARED VPN 0x00000304 PFN 0x00000112)
|
|
page_tbl: p1 *(a800000000117828) == 00113b80 (SHARED VPN 0x00000305 PFN 0x00000113)
|
|
page_tbl: p1 *(a800000000117830) == 00114b80 (SHARED VPN 0x00000306 PFN 0x00000114)
|
|
page_tbl: p1 *(a800000000117838) == 00115b80 (SHARED VPN 0x00000307 PFN 0x00000115)
|
|
page_tbl: p2 *(a800000000118000) == 0010db80 (.text VPN 0x00000000 PFN 0x0000010d)
|
|
page_tbl: p2 *(a800000000119800) == 0010eb80 (SHARED VPN 0x00000300 PFN 0x0000010e)
|
|
page_tbl: p2 *(a800000000119808) == 0010fb80 (SHARED VPN 0x00000301 PFN 0x0000010f)
|
|
page_tbl: p2 *(a800000000119810) == 00110b80 (SHARED VPN 0x00000302 PFN 0x00000110)
|
|
page_tbl: p2 *(a800000000119818) == 00111b80 (SHARED VPN 0x00000303 PFN 0x00000111)
|
|
page_tbl: p2 *(a800000000119820) == 00112b80 (SHARED VPN 0x00000304 PFN 0x00000112)
|
|
page_tbl: p2 *(a800000000119828) == 00113b80 (SHARED VPN 0x00000305 PFN 0x00000113)
|
|
page_tbl: p2 *(a800000000119830) == 00114b80 (SHARED VPN 0x00000306 PFN 0x00000114)
|
|
page_tbl: p2 *(a800000000119838) == 00115b80 (SHARED VPN 0x00000307 PFN 0x00000115)
|
|
proc_tbl: p1 *(a80000000011a000) == tests/LONG/mpintadd PROC. Entry = 00000120
|
|
proc_tbl: p2 *(a80000000011a4e0) == tests/LONG/mpintadd PROC. Entry = 00000120
|
|
Slot 0b CPU 00
|
|
Slot 0b CPU 01
|
|
--> Niblet (a800000000105cc8)
|
|
******************************************************************
|
|
0000000000005656
|
|
0000000000000000
|
|
Master CPU: 0000000000000000
|
|
a80000000011a000
|
|
a800000000107850
|
|
Number of processes active:
|
|
0000000000000002
|
|
0000000000000120
|
|
0000000000000001> 0000000010101006
|
|
0000000000000001> 0000000000000004
|
|
0000000000000001> 0000000000000100
|
|
0000000000000001> 00000000000000c0
|
|
0000000000000001> 0000000000000080
|
|
0000000000000001> 0000000000000040
|
|
Test passed
|
|
Process number:
|
|
0000000000000001
|
|
No processes left to run - twiddling.
|
|
Niblet passed on an interrupt.
|
|
Supertest PASSED.
|
|
|
|
Niblet Complete.
|
|
|