222 lines
4.4 KiB
ArmAsm
222 lines
4.4 KiB
ArmAsm
/***********************************************************************\
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* File: master.s *
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* *
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* This file contains the code which is executed exclusively *
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* by the Boot Master processor. It completes the power-on *
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* boot sequence by configuring the IO4 NVRAM and serial port, *
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* running additional diagnostics, configuring memory, and *
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* downloading the IO4 prom. *
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* *
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\***********************************************************************/
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#ident "$Revision: 1.37 $"
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#include "ml.h"
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#include <sys/regdef.h>
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#include <asm.h>
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#include <sys/sbd.h>
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#include <sys/cpu.h>
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#include "ip21prom.h"
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#include "prom_leds.h"
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#include <sys/EVEREST/evintr.h>
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#include "prom_intr.h"
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#include "pod.h"
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#include <sys/EVEREST/evconfig.h>
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#include <sys/EVEREST/sysctlr.h>
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.text
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.set noreorder
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.set noat
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/*
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* Routine prom_master
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* Executed by the Boot Master processor.
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* Performs rest of power-on startup.
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*
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* Arguments:
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* None.
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* Returns:
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* Never returns.
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*/
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LEAF(prom_master)
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/*
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* Announce our presence as the boot master
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*/
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jal set_cc_leds #
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ori a0, zero, PLED_BMASTER # (BD)
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DPRINT("I am the Boot Master\r\n")
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jal delay
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li a0, 10000
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dla a0, everest_mesg
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jal sysctlr_message
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nop
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li a0, 50000
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jal delay
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nop
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jal sysctlr_getdebug
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nop
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andi v0, VDS_NO_DIAGS
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beqz v0, 1f
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nop # (BD)
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GET_BSR(a1)
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ori a1, BS_NO_DIAGS # Turn on no diags bit
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SET_BSR(a1)
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dla a0, no_diags_mesg
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jal sysctlr_message
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nop # (BD)
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j 3f # Skip dcache diags
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nop # (BD)
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1:
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GET_BSR(a1)
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andi a1, BS_NO_DIAGS
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bnez a1, 3f # Skip diags if bit's set
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nop
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jal set_cc_leds
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ori a0, zero, PLED_CKSCACHE1
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SCPRINT("Secondary Cache test..")
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jal pon_invalidate_dcache
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nop
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jal gcache_invalidate
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nop
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jal gcache_check
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nop
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move s0, v0
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jal gcache_invalidate
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nop
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beqz v0, 3f
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nop
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b prom_abdicate
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move a0, v0
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/*
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* Do preliminary primary data cache testing before we
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* use it as a stack.
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*/
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3:
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jal set_cc_leds
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ori a0, zero, PLED_CKPDCACHE1
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SCPRINT("PD Cache test..")
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/* additional dcache test */
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jal dcache_tag
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nop
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beqz v0, 4f
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nop
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/* Abdicate bootmastership. Send the diagnostic code as the
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* reason for abdicatoing.
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*/
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b prom_abdicate
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move a0, v0
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4:
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jal pon_invalidate_dcache
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nop
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jal gcache_invalidate
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nop
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/*
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* Set up a stack in the primary dcache so that we can
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* execute C code, we set set 1 low 16KB as stack regrion.
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*/
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jal set_cc_leds # Set up the LEDS
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ori a0,zero, PLED_MAKESTACK # (BD)
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SCPRINT("Building stack..")
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jal pon_fix_dcache_parity #
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nop # of it.
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#dli a0, PROM_SR | SR_IE
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dli a0, PROM_SR
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DMTC0(a0, C0_SR) # Set up the status register
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jal get_dcachesize # Get the primary dcache size
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nop
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/* Force set 3 OFF and Writeback Disable OFF */
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dli t0, BB_STARTUP_CTRL
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li t1, 0 # WriteBackInhibit
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sd t1, 0(t0) # clear both ForceSet3 and WriteBackInhibit
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dli t1, BB_SET_ALLOW
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li a0, 0x0f
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sd a0, 0(t1) # set all 4 SetAllow bits to 1
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/* stack is created at the last 16 kbytes of First MB of set1 */
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dli sp, POD_STACKADDR # Load the base stack address
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subu v0,8
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daddu sp,v0 # The stack grows down, so inc sp
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SCPRINT("Jumping to MAIN")
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jal set_cc_leds # Set the LEDS
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ori a0, zero, PLED_MAIN
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j main # Now call the main C routine.
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nop
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END(prom_master)
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LEAF(prom_abdicate)
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# Load diagval reg with the reason we're abdicating
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DMTC1(a0, DIAGVAL_REG)
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# Set BM "I've been master" bit
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GET_BSR(t0)
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ori t0, BS_ABDICATED
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ori t1, zero, BS_USE_EPCUART
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not t1
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and t0, t1 # Turn off EPC UART bit.
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SET_BSR(t0)
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# Flush characters out of the CC UART
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jal ccuart_flush
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nop
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# Get out of the master group
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dli t0, EV_IGRMASK
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sd zero, 0(t0)
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# Send rearb character to sysctlr
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jal ccuart_putc
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li a0, SC_ESCAPE # (BD)
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jal ccuart_putc
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li a0, SC_BMRESTART # (BD)
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jal pod_clear_ints # Clear the interrupts the other
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nop # (BD) CPUs sent us
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# Send interrupt to slaves
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SENDINT_SLAVES(REARB_LEVEL)
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# Jump to slave loop
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j rearb_bootmaster # Join the rearbitartion fun!
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nop # (BD)
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END(prom_abdicate)
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.data
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everest_mesg: .asciiz "Starting System.."
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no_diags_mesg: .asciiz "* DIAGS DISABLED *"
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