264 lines
6.4 KiB
ArmAsm
264 lines
6.4 KiB
ArmAsm
/*
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* IP26prom/cache.s -- prom cache initialization.
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*
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*/
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#ident "$Revision: 1.14 $"
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#include <sys/cpu.h>
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#include <sys/sbd.h>
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#include <sys/regdef.h>
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#include <asm.h>
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/*
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* check_scachesize
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* return the size of the secondary cache
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*
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* Assume the gcache tag ram size options are 1,2,4,8,& 16 MB.
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* By loading the following data in the order shown:
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*
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* Write Read Read Read Read Read
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* Addr: Data: 16MB 8MB 4MB 2MB 1MB
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* index
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* 0 f f 7 3 1 0
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* 512 e e 6 2 0 0
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* 1024 d d 5 1 1 0
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* 1536 c c 4 0 0 0
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* 2048 b b 3 3 1 0
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* 2560 a a 2 2 0 0
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* 3072 9 9 1 1 1 0
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* 3584 8 8 0 0 0 0
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* 4096 7 7 7 3 1 0
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* 4608 6 6 6 2 0 0
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* 5120 5 5 5 1 1 0
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* 5632 4 4 4 0 0 0
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* 6144 3 3 3 3 1 0
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* 6656 2 2 2 2 0 0
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* 7168 1 1 1 1 1 0
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* 7680 0 0 0 0 0 0
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*
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* If the data is then read back (after all data has been written) it
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* should match one of the patterns in the five read columns. The
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* column it matches gives the size of the cache.
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* we need to check the bus tag ram, odd tag ram and even tag ram
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* and make sure they are consistent.
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*
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* v0: return scache size
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*/
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LEAF(check_scachesize)
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#define HARDCODE_GSIZE /* XXX -- try realsizing later */
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#ifdef HARDCODE_GSIZE
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li v0,2 # 2MB teton GCache
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j ra
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#else
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.set noreorder
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/* Read from a uncached addr -- The IP21 prom does this, presumably
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* to work around some bug?
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*/
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dli t0,PHYS_TO_K1(TCC_FIFO)
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ld t1,0(t0)
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ld t1,0(t0)
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/* Max GCache tag ram size is 16MB.
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*/
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li t0,0x1fff # 8192 entries (16MB)
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li t1,0 # t1 indicates which index
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li t2,512 # 512 entries for one value
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li t3,16 # 16 possible values
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1:
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/* Set-up addresses
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*/
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dli v0,TCC_ETAG_DA # tag data base
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dli v1,TCC_ETAG_ST # tag state base
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/* Default tag state -- set dirty enable, virtual synonym, and state
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* to valid.
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*/
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dli s2,GCACHE_VSYN_E | GCACHE_STATE_EN | \
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(GCACHE_VALID << GCACHE_STATE_SHIFT)
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/* Load tag value. Mask tag to ensure we use tag 0.
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*/
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dla s0,tag_value
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lw s1,0(s0)
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2:
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/* Calculate address for set 0 -- shift index and combine it with
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* the base address.
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*/
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sll ta2,t1, TAGADDR_INDEX_SHIFT
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or ta1,v0,ta2 # address of proc tag addr.
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or ta3,v1,ta2 # address of proc tag state
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/* Write data and state
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*/
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sd s1,0(ta1) # write into proc tag addr.
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sd s2,0(ta3) # write into proc tag state
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/* Bump index value and loop.
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*/
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subu t2,1
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daddu t1,1
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bnez t2,2b
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nop
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/* Re-load tag value with next word.
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*/
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daddiu s0,4
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lw s1,0(s0)
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/* Re-init loop control and load next value.
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*/
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li t2,512
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subu t3,1
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bnez t3,2b
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nop
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/* Now read back the data and compare the value for addr index 0
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* if read back 0xf, report 16mb
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* if read back 0x7, report 8mb
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* if read back 0x3, report 4mb
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* if read back 0x1, report 2mb
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* if read back 0x0, report 1mb
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*/
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dli t0,TCC_ETAG_DA # read back from even tag ram
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ld a0,0(t0)
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srl a0,20
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daddiu a0,1 # gcache even tag ram size
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dli t0,TCC_OTAG_DA # read back from odd tag ram
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ld a1,0(t0)
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srl a1,20
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daddiu a1,1 # gcache odd tag ram size
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/* Compare tag ram sizes. They must be the same, if not report
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* an error by blinking the led.
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*/
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bne a0,a1,error
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nop
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/* Check scache tag size is 1,2,4,8, or 16 only -- if we do not
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* get a match, report an error by blinking the led.
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*/
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dla t0,scache_tag_size
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li t2,5
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20:
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lw t1,0(t0)
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bne a1,t1,30f
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nop
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move v0,a0 # return cache size in MB
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j ra # hit -> return to caller
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nop
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30:
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daddiu t0,4 # get next value
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subu t2,1
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bnez t2,20b # try again
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nop
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/* no match falls through to error
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*/
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error:
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j memflash
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li a0,1 # very fast flash
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#endif
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END(check_scachesize)
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#if 0
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.data
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tag_value:
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.word 0xf00000,0xe00000,0xd00000,0xc00000,0xb00000,0xa00000,0x900000
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.word 0x800000,0x700000,0x600000,0x500000,0x400000, 0x300000,0x200000
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.word 0x100000,0
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scache_tag_size:
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.word 1,2,4,8,16
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.text
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#endif
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/* Initialize Store Address Queue by issuing (SAQ_DEPTH) Even and
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* (SAQ_DEPTH) Odd uncached-writes to two even and odd aligned
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* local registers - two undefined TCC registers are used.
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*/
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LEAF(flush_SAQueue)
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.set noreorder
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dli t0,PHYS_TO_K1(SAQ_INIT_ADDRESS)
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li t1,SAQ_DEPTH # number of entries in the queue
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1:
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sd zero,0(t0) # write (even) 8 bytes
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sd zero,8(t0) # write (odd) 8 bytes
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addi t1,-1
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bnez t1,1b
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nop
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j ra
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nop
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.set reorder
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END(flush_SAQueue)
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/* Invalidate I and D caches by running code that invalidates the I cache
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* and invalidate D cache by writing tags.
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*
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* Initialize DCache by invalidating it. DCache is 16KB, with 32Byte line,
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* 28 bits Tag + 1 bit Exclusive + 8 bits Valid + 32 Bytes Data
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* Need two consecutive writes to half-line boundaries to clear Valid bits
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* for each line.
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*/
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LEAF(pon_invalidate_IDcaches)
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.set noreorder
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dmfc0 t9,C0_CONFIG
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.set reorder
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and t0,t9, CONFIG_DC # calc DCache size
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srl t0,CONFIG_DC_SHFT
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addi t0,12
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li s0,1
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sll s0,t0
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and t0,t9, CONFIG_IC # calc ICache size
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srl t0,CONFIG_IC_SHFT
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addi t0,11
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li a1,1
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sll a1,t0
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and t1,t9,CONFIG_IB # convert to lines for flush
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beq t1,zero,1f
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srl a1,4 # 16 byte line size
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b 2f
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1:
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srl a1, 5 # 32 byte line size
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2:
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# Saved registers before __tfp_icache_flush_text call (only touches a1)
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# s0 - dcache size
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# s1 - ra
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move s1,ra # save ra
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jal __tfp_icache_flush_text # flush icache by running code
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move ra,s1 # restore ra
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dli t1,PHYS_TO_K0(0x19000000) # Starting address for init
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daddu t2,t1,s0 # t2 is loop terminator
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# Now mark each 1/2 cache line invalid.
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1:
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.align 3 # 1/2 quad align the loop
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.set noreorder
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dmtc0 t1,C0_BADVADDR
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ssnop
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dmtc0 zero,C0_DCACHE # clear all (4) Valid bits
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ssnop
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ssnop
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ssnop
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dctw # write to the Dcache Tag
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ssnop
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ssnop
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.set reorder
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daddiu t1,16 # increment to next half-line
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bltu t1,t2,1b # loop till thru whole cache
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j ra
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END(pon_invalidate_IDcaches)
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