163 lines
3.5 KiB
ArmAsm
163 lines
3.5 KiB
ArmAsm
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#ident "$Revision: 1.4 $"
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#include <sys/cpu.h>
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#include <sys/sbd.h>
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#include <asm.h>
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#include <regdef.h>
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/* init from prom as T5 sometimes seems to turn these into cache misses,
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* and memory may not be initalized yet. This is good for larger caches
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* even though the prom is only 512K. It alias the prom for 2MB.
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*/
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#define CACHE_INIT_BASE PHYS_TO_K0(0x1fc00000)
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LEAF(init_icache)
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move v1,a0
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dsrl v1,1 # 2 ways
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dli v0,CACHE_INIT_BASE
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PTR_ADDU v1,v0
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.set noreorder
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mtc0 zero,C0_TAGLO
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mtc0 zero,C0_TAGHI
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mtc0 zero,C0_ECC
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1:
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PTR_ADDU v0,CACHE_ILINE_SIZE
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cache CACH_PI|C_ISD,-64(v0) # initialize data array
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cache CACH_PI|C_ISD,-63(v0)
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cache CACH_PI|C_ISD,-60(v0)
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cache CACH_PI|C_ISD,-59(v0)
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cache CACH_PI|C_ISD,-56(v0)
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cache CACH_PI|C_ISD,-55(v0)
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cache CACH_PI|C_ISD,-52(v0)
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cache CACH_PI|C_ISD,-51(v0)
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cache CACH_PI|C_ISD,-48(v0)
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cache CACH_PI|C_ISD,-47(v0)
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cache CACH_PI|C_ISD,-44(v0)
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cache CACH_PI|C_ISD,-43(v0)
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cache CACH_PI|C_ISD,-40(v0)
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cache CACH_PI|C_ISD,-39(v0)
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cache CACH_PI|C_ISD,-36(v0)
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cache CACH_PI|C_ISD,-35(v0)
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cache CACH_PI|C_ISD,-32(v0)
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cache CACH_PI|C_ISD,-31(v0)
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cache CACH_PI|C_ISD,-28(v0)
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cache CACH_PI|C_ISD,-27(v0)
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cache CACH_PI|C_ISD,-24(v0)
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cache CACH_PI|C_ISD,-23(v0)
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cache CACH_PI|C_ISD,-20(v0)
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cache CACH_PI|C_ISD,-19(v0)
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cache CACH_PI|C_ISD,-16(v0)
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cache CACH_PI|C_ISD,-15(v0)
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cache CACH_PI|C_ISD,-12(v0)
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cache CACH_PI|C_ISD,-11(v0)
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cache CACH_PI|C_ISD,-8(v0)
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cache CACH_PI|C_ISD,-7(v0)
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cache CACH_PI|C_ISD,-4(v0)
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bltu v0,v1,1b
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cache CACH_PI|C_ISD,-3(v0) # BDSLOT
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.set reorder
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j ra
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END(init_icache)
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LEAF(init_dcache)
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move v1,a0
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dsrl v1,1 # 2 ways
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dli v0,CACHE_INIT_BASE
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PTR_ADDU v1,v0
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.set noreorder
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mtc0 zero,C0_TAGLO
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mtc0 zero,C0_TAGHI
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mtc0 zero,C0_ECC
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1:
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PTR_ADDU v0,CACHE_DLINE_SIZE
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cache CACH_PD|C_ISD,-32(v0) # initialize data array
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cache CACH_PD|C_ISD,-31(v0)
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cache CACH_PD|C_ISD,-28(v0)
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cache CACH_PD|C_ISD,-27(v0)
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cache CACH_PD|C_ISD,-24(v0)
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cache CACH_PD|C_ISD,-23(v0)
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cache CACH_PD|C_ISD,-20(v0)
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cache CACH_PD|C_ISD,-19(v0)
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cache CACH_PD|C_ISD,-16(v0)
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cache CACH_PD|C_ISD,-15(v0)
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cache CACH_PD|C_ISD,-12(v0)
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cache CACH_PD|C_ISD,-11(v0)
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cache CACH_PD|C_ISD,-8(v0)
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cache CACH_PD|C_ISD,-7(v0)
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cache CACH_PD|C_ISD,-4(v0)
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bltu v0,v1,1b
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cache CACH_PD|C_ISD,-3(v0) # BDSLOT
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.set reorder
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j ra
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END(init_dcache)
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LEAF(init_scache)
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move v1,a0
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dsrl v1,1 # 2 ways
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dli v0,CACHE_INIT_BASE
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PTR_ADDU v1,v0
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.set noreorder
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mtc0 zero,C0_TAGLO
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mtc0 zero,C0_TAGHI
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mtc0 zero,C0_ECC
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1:
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PTR_ADDU v0,CACHE_SLINE_SIZE
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#if (CACHE_SLINE_SIZE == 128)
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cache CACH_SD|C_ISD,-128(v0) # inialize data array
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cache CACH_SD|C_ISD,-127(v0)
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cache CACH_SD|C_ISD,-112(v0)
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cache CACH_SD|C_ISD,-111(v0)
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cache CACH_SD|C_ISD,-96(v0)
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cache CACH_SD|C_ISD,-95(v0)
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cache CACH_SD|C_ISD,-80(v0)
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cache CACH_SD|C_ISD,-79(v0)
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#endif /* CACHE_SLINE_SIZE == 128 */
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cache CACH_SD|C_ISD,-64(v0)
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cache CACH_SD|C_ISD,-63(v0)
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cache CACH_SD|C_ISD,-48(v0)
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cache CACH_SD|C_ISD,-47(v0)
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cache CACH_SD|C_ISD,-32(v0)
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cache CACH_SD|C_ISD,-31(v0)
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cache CACH_SD|C_ISD,-16(v0)
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bltu v0,v1,1b
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cache CACH_SD|C_ISD,-15(v0) # BDSLOT
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.set reorder
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j ra
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END(init_scache)
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/* Invalidate all tlb entries */
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LEAF(init_tlb)
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.set noreorder
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dmtc0 zero,C0_TLBLO_0
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dmtc0 zero,C0_TLBLO_1
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move v1,zero # C0_TLBHI
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li v0,TLBPGMASK_MASK
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mtc0 v0,C0_PGMASK
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mtc0 zero,C0_FMMASK
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li a0,_PAGESZ*2 # VPN increment
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li v0,NTLBENTRIES-1
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1:
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dmtc0 v1,C0_TLBHI
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mtc0 v0,C0_INX
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nop
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c0 C0_WRITEI
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daddu v1,a0 # next VPN
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bne v0,zero,1b
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sub v0,1
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j ra
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nop # BDSLOT
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.set reorder
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END(init_tlb)
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