246 lines
11 KiB
C
246 lines
11 KiB
C
/*
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* =========================================================
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* $Revision: 1.1 $
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* $Date: 1997/08/18 20:41:24 $
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* $Author: philw $
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* =========================================================
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* Crime register address map and more....
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*/
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/*
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* The base address for Crime
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*/
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#define CrimeBASE 0xb4000000 /* Crime base address. */
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#define MEMcntlBASE 0xb4000200 /* MEM base address. */
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#define MEMoffset 0x00000200 /* MEM base offset. */
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/*
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* ID and Revision Register.
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*/
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#define CrimeID 0x00000000 /* ID register. */
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#define IDMASK 0x000000f0 /* Crime ID mask. */
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#define REVMASK 0x0000000f /* Crime revision mask. */
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/*
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* Crime control register.
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*/
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#define CrimeCNTL 0x00000008 /* Control register. */
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#define SysADcTriton 0x00002000 /* Triton check SysADC */
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#define SysADcCrime 0x00001000 /* Crime check SysADC */
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#define Softreset 0x00000800 /* Softreset */
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#define WARMRESET 0x00000400 /* Triton warm reset. */
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#define WATCHDOG 0x00000200 /* Watchdog timer enable*/
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#define ENDIAN 0x00000100 /* big/little 1/0 */
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#define WBMARK 0x000000f0 /* high water mark mask.*/
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#define CMDQMARK 0x0000000f /* command Q high wmask.*/
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/*
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* Interrupt status register, interrupt enable register,
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* Software interrupt register, and Hardware interrupt register.
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*/
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#define CrimeIntrStatus 0x00000010 /* Interrupt Status. */
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#define CrimeIntrEnable 0x00000018 /* Interrupt Enable. */
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#define CrimeSoftIntr 0x00000020 /* Software Interrupt. */
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#define CrimeHardIntr 0x00000028 /* Hardware Interrupt. */
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#define VICE_INT 0x80000000 /* VICE interrupt. */
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#define SOFT_INT1 0x20000000 /* Software interrupt1 */
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#define SOFT_INT0 0x10000000 /* Software interrupt0 */
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#define RE_INT1 0x00800000 /* RE interrupt1 */
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#define RE_INT0 0x00400000 /* RE interrupt0 */
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#define MEMerr_INT 0x00200000 /* Memory Err interrupt.*/
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#define CRIMEerr_INT 0x00100000 /* Crime Err interrupt.*/
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#define GBEerr_INT 0x000f0000 /* GBE interrupt mask. */
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#define MACEerr_INT 0x0000ffff /* MACE interrupt mask. */
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#define NORM_INT_STAT 0x0B400000
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/*
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* WatchDog Timer register.
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*/
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#define CrimeWatchDog 0x00000030 /* Watch Dog timer. */
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#define WATCHDOG_ALARM 0x00100000 /* WatchDog time out. */
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#define WATCHDOG_MASK 0x000fffff /* WatchDog value mask. */
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/*
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* Crime timer register.
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*/
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#define CrimeTimer 0x00000038 /* Crime Timer. */
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/*
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* CPU Error Address register, and CPU Error status register.
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*/
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#define CPUErrADDR 0x00000040 /* CPU Error Address. */
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#define CPUErrSTATUS 0x00000048 /* CPU Error Status. */
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#define SYSCMD_INVALID 0x00000010 /* SysCMD Invalid cmd. */
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#define SYSAD_PARITY 0x00000008 /* SysAD parity error. */
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#define SYSCMD_PARITY 0x00000004 /* SysCMD parity error. */
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#define CPUinvalidADDR 0x00000002 /* CPU invalid address.*/
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#define CPUinvalidREG 0x00000001 /* Triton invalid reg. */
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#define CPUErrENABLE 0x00000050 /* CPU Error ENABLE. */
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#define CPUinvalidADDr 0x00000200 /* CPU invalid read. */
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#define CPUillegalINST 0x00000010 /* CPU Illegal inst. */
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#define CPUSysADC 0x00000008 /* CPU SysAD parity. */
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#define CPUSysCMDC 0x00000004 /* CPU SysCMD parity */
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#define CPUinvalidADDP 0x00000002 /* CPU Illegal addr. */
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#define CPUinvalidREGP 0x00000001 /* CPU Illegal reg. */
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#define CPUallIllegal 0x0000001F /* everything except CMDC */
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#define VICEerrADDR 0x00000058 /* VICE Error Addr. */
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/*
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* Memory controller Status/control register.
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*/
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#define MEMCntl 0x00000200 /* Memory control reg. */
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#define ECCREPL 0x00000002 /* Use ECC replacement */
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/* check bits. */
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#define ECCENABLE 0x00000001 /* Enable ECC checking. */
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/*
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* Bank 0 - 7 control register.
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*/
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#define MEMBank0CNTL 0x00000208 /* Bank0 control reg. */
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#define MEMBank1CNTL 0x00000210 /* Bank1 control reg. */
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#define MEMBank2CNTL 0x00000218 /* Bank2 control reg. */
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#define MEMBank3CNTL 0x00000220 /* Bank3 control reg. */
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#define MEMBank4CNTL 0x00000228 /* Bank4 control reg. */
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#define MEMBank5CNTL 0x00000230 /* Bank5 control reg. */
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#define MEMBank6CNTL 0x00000238 /* Bank6 control reg. */
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#define MEMBank7CNTL 0x00000240 /* Bank7 control reg. */
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/*
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* Refresh Counter Register.
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*/
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#define MEMRefshCNTR 0x00000248 /* Refresh counter. */
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#define REFRESH_MASK 0x000007ff /* Refresh counter mask */
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/*
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* Memory Error status register and memory error address register.
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*/
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#define MEMErrSTATUS 0x00000250 /* Memory error status. */
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#define MEMErrADDR 0x00000258 /* Memory error address.*/
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#define INVDADDR 0x02000000 /* Invalid mem address. */
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#define ECCWRERR 0x01000000 /* Ecc read error. */
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#define ECCRDERR 0x00800000 /* Ecc read error. */
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#define MHARDERR 0x00400000 /* Multiple hard error. */
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#define HARDERR 0x00200000 /* First hard error. */
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#define SOFTERR 0x00100000 /* First soft error. */
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#define CPUECC 0x00040000 /* CPU cause ecc error. */
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#define VICEECC 0x00020000 /* VICE cause ecc err. */
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#define GBEECC 0x00010000 /* GBE cause ecc error. */
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#define REECC 0x00008000 /* RE cause ecc error. */
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#define REIDMASK 0x00007f00 /* RE source id mask. */
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#define MACEECC 0x00000080 /* MACE cause ecc err. */
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#define MACEMASK 0x0000007f /* MACE source id mask. */
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/*
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* ECC Syndrome register, ECC Check bits register, and
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* ECC replacement check bits register.
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*/
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#define EccSyndrome 0x00000260 /* ECC syndrome bits. */
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#define EccCheckbits 0x00000268 /* ECC check bits. */
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#define EccReplchkbits 0x00000270 /* ECC cehck bit replace*/
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#if defined(_LANGUAGE_C)
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#ifndef uint64_t
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#include <inttypes.h>
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#endif
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struct CRIMEREG {
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uint64_t id ; /* Crime id register. 00*/
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uint64_t cntl ; /* Crime control register. 08*/
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uint64_t intrpt_status ; /* Crime interrupt status. 10*/
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uint64_t intrpt_enable ; /* Crime interrupt enable. 18*/
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uint64_t soft_intrpt ; /* Crime software interrupt. 20*/
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uint64_t hard_intrpt ; /* Crime hardware interrupt. 28*/
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uint64_t watch_dog ; /* Crime watchdog timer. 30*/
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uint64_t crime_timer ; /* Crime timer. 38*/
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uint64_t cpu_error_addr ; /* Crime cpu error address. 40*/
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uint64_t cpu_error_status; /* Crime cpu error status. 48*/
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uint64_t cpu_error_enable; /* Crime cpu error enable. 50*/
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uint64_t vice_err_address; /* Crime vice err address. 58*/
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} ;
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struct MEMREG {
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uint64_t status ; /* MEMcntl status register. 00*/
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uint64_t bank0_cntl ; /* MEMcntl bank0 control reg. 08*/
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uint64_t bank1_cntl ; /* MEMcntl bank1 control reg. 10*/
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uint64_t bank2_cntl ; /* MEMcntl bank2 control reg. 18*/
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uint64_t bank3_cntl ; /* MEMcntl bank3 control reg. 20*/
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uint64_t bank4_cntl ; /* MEMcntl bank4 control reg. 28*/
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uint64_t bank5_cntl ; /* MEMcntl bank5 control reg. 30*/
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uint64_t bank6_cntl ; /* MEMcntl bank6 control reg. 38*/
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uint64_t bank7_cntl ; /* MEMcntl bank7 control reg. 40*/
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uint64_t refresh_cntr ; /* MEMcntl refresh counter. 48*/
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uint64_t mem_error_status; /* MEMcntl error status. 50*/
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uint64_t mem_error_addr ; /* MEMcntl error address. 58*/
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uint64_t ecc_syndrome ; /* MEMcntl ecc syndrome. 60*/
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uint64_t ecc_check_bits ; /* MEMcntl generated ecc. 68*/
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uint64_t ecc_repl ; /* MEMcntl ecc replacement 70*/
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} ;
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typedef struct CRIMEREG *crime_reg ;
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typedef struct MEMREG *mem_reg ;
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#endif
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/*
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* ========================================
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*
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* $Log: crimereg.h,v $
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* Revision 1.1 1997/08/18 20:41:24 philw
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* updated file from bonsai/patch2039 tree
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*
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* Revision 1.3 1996/10/31 21:51:12 kuang
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* Bring Bonsai IP32 debugcard up to the level of IP32 debugcard v2.4 on Pulpwood
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*
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* Revision 1.3 1996/10/04 20:42:10 kuang
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* Added NORM_INT_STAT define
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*
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* Revision 1.2 1996/04/04 23:11:01 kuang
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* Added more diagnostic supports
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*
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* Revision 1.1 1996/03/25 22:17:24 kuang
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* These should fix the PHYS_TO_K1 problem
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*
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* Revision 1.9 1995/08/07 19:55:02 kuang
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* Added cpu read invalid address (enable) bit in CPU/VICE error status
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* register.
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*
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* Revision 1.10 1995/08/07 19:50:11 kuang
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* Added CPU invalid read address
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* bit.
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*
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* Revision 1.9 1995/07/11 18:03:55 kuang
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* *** empty log message ***
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*
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* Revision 1.8 1995/07/05 20:12:54 gardner
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* removed mem row register hit/miss status bits
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*
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* Revision 1.7 1995/06/29 02:46:41 kuang
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* Defined kseg1 address for memory controller registers.
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*
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* Revision 1.8 1995/06/29 02:44:53 kuang
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* Added memory controller base address for kseg1 address space.
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*
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* Revision 1.7 1995/06/08 01:38:06 kuang
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* fixed the memcontroll register.
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*
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* Revision 1.6 1995/05/19 01:53:50 kuang
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* Fixed the CrimeBASE problem for triton model
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*
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* Revision 1.5 1995/05/18 01:22:20 kuang
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* Fixed the missing Softreset problem.
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*
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* Revision 1.4 1995/05/18 01:19:11 kuang
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* Changed several crime register defines to reflect
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* the crime register changes.
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*
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* Revision 1.3 1995/04/21 22:08:07 kuang
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* Changed to the new CRIME register map.
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*
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*
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* ========================================
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*/
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/* END OF FILE */
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