44 lines
1.3 KiB
C
44 lines
1.3 KiB
C
/*
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* -------------------------------------------------------------
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* $Revision: 1.1 $
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* $Date: 1997/08/18 20:45:43 $
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* -------------------------------------------------------------
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* Debug card specific addresses and error codes.
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*/
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#ifndef DBCSIM_H
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#define DBCSIM_H
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/*
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* Define the phony LA address, where we can write data to
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* it.
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*/
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#define UARTaddr _uartaddr
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#define FLASH_ALIAS 0xbfc00000 /* FIXED */
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#define PROM_BASE 0xbfe00000 /* FIXED */
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#define ENLOW 0xbff00000 /* FIXED */
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/*
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* Define error codes, which will be used in conjuction with a
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* LA in the lab.
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*/
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#define ERR_AFTER_RESET 0x0000001f /* Error after reset. */
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#define ERR_NMI_SF_RESET 0x0000002f /* NMI/soft reset error.*/
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#define TLB_ERROR1 0x0000003f /* TLB miss */
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#define TLB_ERROR2 0x0000004f /* xTLB miss. */
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#define CACHE_ERROR 0x0000005f /* Cache error. */
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#define UNEXPECTED_ERROR 0x0000006f /* 0x380 error. */
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/*
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* Define the flash accress control register.
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*/
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#define FLASH_CNTL 0xbf310008 /* ISA flash controlreg.*/
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/*
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* Prototypes
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*/
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extern void DPRINTF(char *, ...);
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#endif /* DBCSIM_H */
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