227 lines
7.6 KiB
C
227 lines
7.6 KiB
C
#ifndef __CACHES_H__
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#define __CAHCES_H__ 1
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#endif
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/**************************************************************************
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* *
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* Copyright (C) 1996, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#define PIlcops 10 /* 10 entries in picache lcoptab */
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#define PDlcops 10 /* 10 entries in picache lcoptab */
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#define SIDlcops 10 /* 10 entries in sidcache lcoptab */
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#define S512K 0x80000 /* 512K base size for 2nd cache */
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#define R4600_SCACHE_LINESIZE (8*4)
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#define R4600_DCACHE_LINESIZE (8*4)
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#define R4600_ICACHE_LINESIZE (8*4)
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#define R4600_DCACHE_LINEMASK ((8*4)-1)
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#define R4600_ICACHE_LINEMASK ((8*4)-1)
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#define CACHSZ_REG 0x11
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#define R4600_SCACHE_LINESIZE (8*4)
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#define R4600_SCACHE_LINEMASK ((8*4)-1)
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#define XKPHYS_UNCACHED_BASE 0x9000
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#define XKPHYS_UNCACHED_SHIFT 0x20
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/*
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* FAKE2ND : both r5k and r4600 family use a faked 2nd write through
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* 2nd cache which do not support regular cache ops.
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* UNIFYWB2ND : unify write back 2nd cache.
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* TWOSETWB2ND : two set associated write back 2nd cache.
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* UNIFYWT2ND : unify write through 2nd cache.
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* TWOSETWT2ND : two set associated write through 2nd cache.
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*/
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#define FAKE2ND 0
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#define UNIFYWB2ND 1
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#define UF2SETWB2ND 2
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#define UNIFYWT2ND 3
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#define UF2SETWT2ND 4
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#if defined(_LANGUAGE_ASSEMBLY)
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/*
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* Constant used for stack frames.
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*/
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#define framesize 176
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#define inargs 176
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#define frameoffset 32 /* allow 4 doubleword. */
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#define localargs 168 /* sp+framesize-0x08, max 4 dwords */
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#define regsave 136 /* sp+framesize-(4*8)-0x8, 16 regs */
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#define outargs 8 /* sp+framesize-(4*8)-(16*8)-0x8 */
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/*
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* Cache ops index.
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*/
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/* PRIMARY INSTRUCTION CACHE. */
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#define pi_iinval 0 /* primary icache index invalidate. */
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#define pi_ildtag 1 /* primary icache index load tag. */
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#define pi_isttag 2 /* primary icache index store tag. */
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#define pi_hinval 4 /* primary icache hit invalidate. */
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#define pi_fill 5 /* primary icache fill. */
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#define pi_hwb 6 /* primary icache hit write back. */
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/* Following are R10000 only. */
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#define pi_barrier 3 /* primary icache barrier.(r10k) */
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#define pi_nop1 7 /* primary icache index store data. */
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#define pi_ilddata 8 /* primary icache index load data. */
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#define pi_istdata 9 /* primary icache index store data. */
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/* PRIMARY DATA CACHE. */
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#define pd_iwbinval 10 /* primary dcache index wb inval. */
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#define pd_ildtag 11 /* primary dcache index load tag. */
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#define pd_isttag 12 /* primary dcache index store tag. */
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#define pd_cdx 13 /* primary dcache create dirty excl */
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#define pd_hinval 14 /* primary dcache hit invalidate. */
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#define pd_hwbinval 15 /* primary dcache hit wb inval. */
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#define pd_hwb 16 /* primary dcache hit write back. */
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/* Following are R10000 only. */
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#define pd_nop1 17 /* primary dcache index store data. */
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#define pd_ilddata 18 /* primary dcache index load data. */
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#define pd_istdata 19 /* primary dcache index store data. */
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/* SECONDARY INSTRUCTION/DATA CACHE */
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#define sd_iwbinval 20 /* 2nd dcache index wb inval. */
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#define sd_ildtag 21 /* 2nd dcache index load tag. */
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#define sd_isttag 22 /* 2nd dcache index store tag. */
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#define sd_cdx 23 /* 2nd dcache create dirty excl */
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#define sd_hinval 24 /* 2nd dcache hit invalidate. */
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#define sd_hwbinval 25 /* 2nd dcache hit wb inval. */
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#define sd_hwb 26 /* 2nd dcache hit write back. */
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#define sd_hsvil 27 /* 2nd dcache hit set virtual. */
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/* Following are R10000 only. */
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#define sd_ilddata 28 /* 2nd dcache index load data. */
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#define sd_istdata 29 /* 2nd dcache index store data. */
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/*
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* Cache configuration data
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*
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* The following public cache configuation data is used/maintained by this
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* module:
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*
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* _icache_size Size of L1 I cache in bytes
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* _dcache_size Size of L1 D cache in bytes
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* _sidcache_size Size of L2 I/D cache in bytes
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* _icache_linesize Block size of L1 I cache in bytes
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* _dcache_linesize Block size of L1 D cache in bytes
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* _icache_linemask _icache_linesize-1
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* _dcache_linemask _dcache_linesize-1
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* _scache_linesize Block size of L2 I/D cache in bytes
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* _scache_linemask _scache_linesize-1
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* _r4600sc_sidcache_size Size of add-on external cache ala' Indy 4600SC.
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* _two_set_pcaches Non-zero if 2way primary, value == dcache_size/2.
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*/
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/* Caches size */
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.extern _icache_size
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.extern _dcache_size
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.extern _sidcache_size
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.extern _r4600sc_sidcache_size
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/* Cache line size. */
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.extern _icache_linesize
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.extern _dcache_linesize
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.extern _scache_linesize
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/* Cache line mask. */
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.extern _icache_linemask
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.extern _dcache_linemask
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.extern _scache_linemask
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/* Sets in cache. */
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.extern _two_set_pcaches
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.extern _two_set_icaches
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.extern _two_set_scaches
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/* Type of secondary cache. */
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.extern _scache_type
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/* Run time cache op table. */
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.extern lcoptab
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.extern _flushAllCache
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.extern _validCacheAddr
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/* Function prototype */
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.extern __dcache_inval
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.extern __dcache_wb
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.extern __dcache_wb_inval
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.extern __icache_inval
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.extern __cache_wb_inval
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/* Logical cache ops macro */
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#define CacheOP(OPS,ADDR,R1,R2) \
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la R2, lcoptab; \
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lw R2, (OPS<<2)(R2); \
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la R1, ADDR; \
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jalr R2
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#endif /* end of _LANGUAGE_ASSEMBLY */
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#if defined(_LANGUAGE_C)
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/*
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* Cache ops index.
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*/
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/* Caches */
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#define PICACHE 0x0
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#define PDCACHE 0x1
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#define SIDCACHE 0x2
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/* Codes */
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#define IDX_WB_INVAL 0x0
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#define IDX_INVAL 0x0
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#define IDX_LOAD_TAG 0x1
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#define IDX_STORE_TAG 0x2
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#define CR_DIRTY_EXCL 0x3
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#define I_BARRIER 0x3
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#define HIT_INVAL 0x4
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#define I_FILL 0x5
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#define HIT_WB_INVAL 0x5
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#define HIT_WRITEBACK 0x6
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#define HIT_SET_VIRTUAL 0x7
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/* R10000 only. */
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#define IDX_LOAD_DATA 0x8
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#define IDX_STORE_DATA 0x9
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/*
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* Some funny typedef
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*/
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typedef long ADDR_t;
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typedef int SIZE_t;
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typedef int CACH_t;
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typedef int (*cop)(ADDR_t);
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/*
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* function defines
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*/
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extern void r10000_cache_config(void);
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extern void r5000_cache_config(void);
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extern void r4600_cache_config(void);
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extern void r4700_cache_config(void);
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extern void r4400_cache_config(void);
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/*
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* Function prototype.
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*/
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extern void __dcache_inval(char*,int);
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extern void __dcache_wb(char*,int);
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extern void __dcache_wb_inval(char*,int);
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extern void __icache_inval(char*,int);
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extern void __cache_wb_inval(char*,int);
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/*
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* macro for access low level logical cache ops through
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* lcoptab.
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*/
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#define CacheOP(CACHE,CODE,ADDR) (lcoptab[CACHE][CODE])(ADDR);
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#endif /* END of _LANGUAGE_C */
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