210 lines
7.6 KiB
C
210 lines
7.6 KiB
C
/*
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* Moosehead internal fast ethernet interface
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*/
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#ifndef _mace_ec_h_
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#define _mace_ec_h_
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/*
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* mac110
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*/
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typedef volatile struct _mac110 {
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long long macControl; /* 00 Control an config */
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long long interruptStatus; /* 08 Interrupt status */
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long long dmaCtrl; /* 10 Tx and rx DMA control */
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long long rxIntrTimerCtrl; /* 18 Rx interrupt delay timer */
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long long txIntrAlias; /* 20 Alias of tx interrupt bits */
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long long rxIntrAlias; /* 28 Alias of rx interrupt bits */
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struct {
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long reserved;
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long rptr:16; /* ...ring buffer read pointer */
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long wptr:16; /* ...ring buffer write pointer */
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} _txInfo; /* 30 Tx DMA ring buffer ptrs */
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#define txRingBufReadPtr _txInfo.rptr
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#define txRingBufWritePtr _txInfo.wptr
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long long txIalias; /* 38 ...alias of above register */
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struct {
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long r1;
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long r2:8;
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long wptr:8, /* MCL fifo write pointer */
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rptr:8, /* MCL fifo read pointer */
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depth:8; /* MCL fifo depth */
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} _rxInfo; /* 40 Rx DMA ring buffer ptrs */
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#define rxMclFIFOReadPtr _rxInfo.rptr
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#define rxMclFIFOWritePtr _rxInfo.wptr
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#define rxMclFIFODepth _rxInfo.depth
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long long rxIalias1; /* 48 ...alias of above register */
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long long rxIalias2; /* 50 ...alias of above register */
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long long intReq_lastTxVec; /* 58 diag */
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long long phyDataInOut; /* 60 PHY data in/out register */
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long long phyAddress; /* 68 PHY address register */
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long long phyReadStart; /* 70 PHY read initiate */
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long long backoff; /* 78 Random number seed for backoff */
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long long imh1; /* 80 diag */
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long long imd1; /* 88 diag */
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long long imh2; /* 90 diag */
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long long imd2; /* 98 diag */
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long long physicalAddress; /* a0 Ethernet physical address */
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long long secphysicalAddress; /* a8 Secondary ethernet physical address */
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long long multicastFilter; /* b0 Multicast logical address mask */
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long long txRingBase; /* b8 Transmit ring base addr (phys) */
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long long txPkt1CmdHdr; /* c0 diag */
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long long txPkt1CatBuf1; /* c8 diag */
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long long txPkt1CatBuf2; /* d0 diag */
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long long txPkt1CatBuf3; /* d8 diag */
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long long txPkt2CmdHdr; /* e0 diag */
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long long txPkt2CatBuf1; /* e8 diag */
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long long txPkt2CatBuf2; /* f0 diag */
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long long txPkt2CatBuf3; /* f8 diag */
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long long mclRxFifo; /* 100 */
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} Mac110;
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/* Definitions for Mac110.macControl */
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#define MAC_RESET (0x0001) /* 1=> Reset MAC */
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#define MAC_DUPLEX (0x0002) /* 1=> Full duplex */
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#define MAC_LOOPBACK (0x0004) /* 1=> Internal loopback */
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#define MAC_100MB (0x0008) /* 1=> 100 Mb, 0=> 10 Mb */
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#define MAC_MII (0x0010) /* 1=> MII bus selected */
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#define MAC_FILTER (0x0060) /* Filter bits */
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#define MAC_PHYS (0x0000) /* Accept phy. packets only */
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#define MAC_NORMAL (0x0020) /* Accept phy., bcast., mcast packets */
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#define MAC_ALL_MCAST (0x0040) /* Accept phy., bcast., all mcast packets */
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#define MAC_PROMISCOUS (0x0060) /* Accept all packets */
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#define MAC_IPGT (0x3F80) /* Inter packet gap ctr */
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#define MAC_IPGR1 (0x1fc000) /* Inter packet gap ctr */
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#define MAC_IPGR2 (0x7e00000) /* Inter packet gap ctr */
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#define MAC_MASK (0x006F) /* Mask of all of non-counter bits */
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/* Definitions for Mac110.interruptStatus */
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#define INTR_TX_THRSHD (0x0001) /* 1=> TX threshold intr set */
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#define INTR_TX_PKTREQ (0x0002) /* 1=> TX packet intr request set */
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#define INTR_TX_DMAFIFO (0x0004) /* 1=> TX dma fifo overflow intr set */
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#define INTR_TX_MEMERR (0x0008) /* 1=> Memory error during tx intr set*/
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#define INTR_TX_ABORT (0x0010) /* 1=> TX abort intr set */
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#define INTR_RX_THRSHD (0x0020) /* 1=> RX threshold intr set */
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#define INTR_RX_MCLFIFO (0x0040) /* 1=> RX mcl fifo overflow intr set */
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#define INTR_RX_DMAFIFO (0x0080) /* 1=> RX dma fifo overflow intr set */
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#define INTR_RX_MCLRPTR (0xff00) /* Alias of rx mcl fifo read ptr */
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#define INTR_TX_RPTR (0x1ff0000) /* Alias of tx ring buffer read ptr */
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#define INTR_RX_SEQ (0x3e000000) /* Receive sequence number */
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/* Definitions for Mac110.dmaCtrl */
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#define DMA_TX_INTENAB (0x0001) /* 1=> TX empty interrupt enable */
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#define DMA_TX_DMAENAB (0x0002) /* 1=> TX DMA enable */
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#define DMA_TX_RINGMSK (0x000c) /* TX ring size mask */
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#define DMA_TX_8K (0x0000) /* 8KB ring */
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#define DMA_TX_16K (0x0004) /* 16KB ring */
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#define DMA_TX_32K (0x0008) /* 32KB ring */
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#define DMA_TX_64K (0x000c) /* 64KB ring */
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#define DMA_RX_THRSHD (0x01f0) /* Receive interrupt threshold */
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#define DMA_RX_INTENAB (0x0200) /* 1=> RX Threshold intr enable */
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#define DMA_RX_RUNTENAB (0x0400) /* 1=> RX receive runt packets enable */
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#define DMA_RX_GATHENAB (0x0800) /* 1=> RX gather timer enable */
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#define DMA_RX_OFFSET (0x7000) /* RX DMA starting offset */
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#define DMA_RX_OFFSET_SHF (12) /* Shift amount of offset */
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#define DMA_RX_DMAENAB (0x8000) /* 1=> RX DMA enable */
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/*
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* MAC110 Transmit fifo entry
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*
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* Each entry is 128 bytes:
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*
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* +-----------------+
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* | tx command |
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* +-----------------+
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* | concat. buf. ptr| -> [optional] buffer for longer packets
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* +-----------------+
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* | concat. buf. ptr| -> [optional] buffer for longer packets
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* +-----------------+
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* | concat. buf. ptr| -> [optional] buffer for longer packets
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* +-----------------+
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* data
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* :
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* | |
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* +-----------------+
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*
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* Following transmission, the tx-command is overwritten by transmit
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* status data.
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*/
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typedef volatile union{
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struct{
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union{
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struct{
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unsigned long r1; /* TX control data */
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unsigned long r2: 4,
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concatPtr2 : 1, /* Concatenated buffer ptr is valid */
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concatPtr1 : 1,
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concatPtr0 : 1,
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genTxIntr : 1, /* Generate TX intr when pkt sent */
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termOnAbrt : 1, /* Terminate TX on abort */
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byteOffset : 7, /* Byte offset of start of data */
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requestLength : 16; /* Number of data bytes minus 1 */
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}cmd;
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struct{
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unsigned long /* TX status data */
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finished : 1, /* Transmit finished */
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r1 : 31,
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r2 : 2,
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lateCollisions: 1, /* Transmit dropped due to late collision */
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excessDeferral: 1, /* Transmit canceled due to excess deferrals */
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excessCollisions: 1, /* Transmit dropped due to excess collisions */
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underrun : 1, /* Transmit aborted due to underrun */
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excessLength : 1, /* Transmit aborted due to excess length */
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deferred : 1, /* Packet deferred at least once */
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broadcast : 1, /* Broadcast packet */
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multicast : 1, /* Multicast packet */
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CRC : 1, /* CRC error seen on at least one tx attempt */
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lateCollision : 1, /* At least one late collision seen */
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collisions : 4, /* Collision retry count */
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transmitLength : 16; /* Number of data bytes sent */
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}sts;
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unsigned long long ll; /* Simple access to first long long */
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} hdr;
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}x;
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unsigned long long ptr[4]; /* Concatenated buffer ptr */
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char fifoBuf[128];
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} TXfifo;
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/*
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* MAC110 receive status
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*/
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typedef struct _rxBuf{
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unsigned long long
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finished : 1,
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_mbz0 : 15,
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ipChecksum : 16,
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seqNumber : 5,
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physaddrMatch : 1,
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multicastMatch : 1,
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carrierEventSeen : 1,
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receivedBadPacket : 1,
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longEventSeen : 1,
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invalidPreamble : 1,
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broadcastPkt : 1,
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multicastPkt : 1,
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CRCerror : 1,
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dribbleNibble : 1,
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codeViolation : 1,
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receiveLength : 16; /* # of bytes received */
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} RXbuf;
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/*
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* Define the FIFO size
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*
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* The TX FIFO can be 64, 128, 256, or 512 entries.
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* The RX FIFO is 32 entries.
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*/
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#define TXFIFOSMALL 64
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#define TXFIFOMEDIUM 128
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#define TXFIFOLARGE 512
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#define RXFIFOSIZE 32
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#endif
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