195 lines
3.9 KiB
ArmAsm
195 lines
3.9 KiB
ArmAsm
#ident "arcstests/utlbasm.s: $Revision: 1.2 $"
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/*
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* utlbasm.s -- exception handling and assembler for utlb test
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*/
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#include <sys/regdef.h>
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#include <sys/asm.h>
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#include <sys/sbd.h>
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#include <fault.h>
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#include "ml.h"
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.text
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LEAF(set_ctxt)
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.set noreorder
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mtc0 a0,C0_CTXT
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.set reorder
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j ra
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END(set_ctxt)
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LEAF(set_tlblo)
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.set noreorder
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TLBLO_FIX_250MHz(C0_TLBLO) # 250MHz R4K workaround
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mtc0 a0,C0_TLBLO
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nop
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c0 C0_WRITER
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j ra
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.set reorder
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END(set_tlblo)
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/*
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* UTLB Miss exception vector entrypoint - this address gets put
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* in the SPB as the UTLBMissVector. It is called from the firmware
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* UTLB miss exception vector handler that has been copied to 0x80000000.
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*
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* On entry:
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* k0 contains the address of this entrypoint
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* k1 contains the link (ra) to the firmware vector
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*/
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LEAF(local_utlb_vec)
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.set noat
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move k0,AT
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.set at
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sw k0,_at_save
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sw v0,_v0_save
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li v0,EXCEPT_UTLB
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/*
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* common exception handling code
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*/
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XLEAF(exception)
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/*
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* Save various registers so we can print informative messages
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* for faults (whether on normal stack or fault stack)
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*/
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sw v0,_exc_save
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.set noreorder
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mfc0 v0,C0_EPC
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nop
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sw v0,_epc_save
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mfc0 v0,C0_SR
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nop
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sw v0,_sr_save
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mfc0 v0,C0_BADVADDR
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nop
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sw v0,_badvaddr_save
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mfc0 v0,C0_CAUSE
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nop
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.set reorder
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sw v0,_cause_save
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sw sp,_sp_save
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lw sp,_fault_sp # use "fault" stack
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/*
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* Only save registers if on regular stack
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* then change mode to fault mode
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*/
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lw v0,_stack_mode
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sw v0,_mode_save
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beq v0,MODE_FAULT,nosave # was in fault mode
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li v0,MODE_FAULT
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sw v0,_stack_mode # now in fault mode
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lw v0,_epc_save
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sw v0,_regs+R_EPC*4
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lw v0,_sr_save
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sw v0,_regs+R_SR*4
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lw v0,_at_save
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sw v0,_regs+R_AT*4
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lw v0,_v0_save
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sw v0,_regs+R_V0*4
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lw v0,_exc_save
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sw v0,_regs+R_EXCTYPE*4
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lw v0,_badvaddr_save
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sw v0,_regs+R_BADVADDR*4
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lw v0,_cause_save
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sw v0,_regs+R_CAUSE*4
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lw v0,_sp_save
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sw v0,_regs+R_SP*4
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sw zero,_regs+R_ZERO*4 # we don't trust anything
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sw v1,_regs+R_V1*4
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sw a0,_regs+R_A0*4
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sw a1,_regs+R_A1*4
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sw a2,_regs+R_A2*4
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sw a3,_regs+R_A3*4
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sw t0,_regs+R_T0*4
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sw t1,_regs+R_T1*4
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sw t2,_regs+R_T2*4
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sw t3,_regs+R_T3*4
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sw t4,_regs+R_T4*4
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sw t5,_regs+R_T5*4
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sw t6,_regs+R_T6*4
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sw t7,_regs+R_T7*4
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sw s0,_regs+R_S0*4
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sw s1,_regs+R_S1*4
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sw s2,_regs+R_S2*4
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sw s3,_regs+R_S3*4
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sw s4,_regs+R_S4*4
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sw s5,_regs+R_S5*4
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sw s6,_regs+R_S6*4
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sw s7,_regs+R_S7*4
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sw t8,_regs+R_T8*4
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sw t9,_regs+R_T9*4
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li k0,0xbad00bad # make it obvious we can't save this
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sw k0,_regs+R_K0*4
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sw k1,_regs+R_K1*4
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sw fp,_regs+R_FP*4
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sw gp,_regs+R_GP*4
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sw ra,_regs+R_RA*4
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mflo v0
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sw v0,_regs+R_MDLO*4
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mfhi v0
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sw v0,_regs+R_MDHI*4
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.set noreorder
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mfc0 v0,C0_INX
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nop
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sw v0,_regs+R_INX*4
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mfc0 v0,C0_RAND # save just to see it change
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nop
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sw v0,_regs+R_RAND*4
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mfc0 v0,C0_TLBLO
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nop
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sw v0,_regs+R_TLBLO*4
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mfc0 v0,C0_TLBHI
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nop
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sw v0,_regs+R_TLBHI*4
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mfc0 v0,C0_CTXT
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nop
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.set reorder
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sw v0,_regs+R_CTXT*4
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lw v0,_sr_save
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and v0,SR_CU1
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beq v0,zero,nosave
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swc1 $f0,_regs+R_F0*4
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swc1 $f1,_regs+R_F1*4
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swc1 $f2,_regs+R_F2*4
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swc1 $f3,_regs+R_F3*4
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swc1 $f4,_regs+R_F4*4
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swc1 $f5,_regs+R_F5*4
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swc1 $f6,_regs+R_F6*4
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swc1 $f7,_regs+R_F7*4
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swc1 $f8,_regs+R_F8*4
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swc1 $f9,_regs+R_F9*4
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swc1 $f10,_regs+R_F10*4
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swc1 $f11,_regs+R_F11*4
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swc1 $f12,_regs+R_F12*4
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swc1 $f13,_regs+R_F13*4
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swc1 $f14,_regs+R_F14*4
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swc1 $f15,_regs+R_F15*4
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swc1 $f16,_regs+R_F16*4
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swc1 $f17,_regs+R_F17*4
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swc1 $f18,_regs+R_F18*4
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swc1 $f19,_regs+R_F19*4
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swc1 $f20,_regs+R_F20*4
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swc1 $f21,_regs+R_F21*4
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swc1 $f22,_regs+R_F22*4
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swc1 $f23,_regs+R_F23*4
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swc1 $f24,_regs+R_F24*4
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swc1 $f25,_regs+R_F25*4
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swc1 $f26,_regs+R_F26*4
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swc1 $f27,_regs+R_F27*4
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swc1 $f28,_regs+R_F28*4
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swc1 $f29,_regs+R_F29*4
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swc1 $f30,_regs+R_F30*4
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swc1 $f31,_regs+R_F31*4
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cfc1 v0,$30
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sw v0,_regs+R_C1_EIR*4
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cfc1 v0,$31
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sw v0,_regs+R_C1_SR*4
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nosave:
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/* finally call the alternate exception handler
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*/
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jal local_exception_handler
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j _resume
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END(exception)
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