231 lines
7.7 KiB
C
231 lines
7.7 KiB
C
#ident "$Id: mem_test.h,v 1.1 1994/07/20 23:48:52 davidl Exp $"
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/**************************************************************************
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* *
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* Copyright (C) 1993, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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#ifndef LOCORE
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#include "sys/types.h"
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#endif !LOCORE
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/*------------------------------------------------------------------------+
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| register usage |
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+------------------------------------------------------------------------*/
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#define RetAdr s7
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/*------------------------------------------------------------------------+
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| MISC. |
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+------------------------------------------------------------------------*/
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#define MemSize 0x02000000
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#define BANK_INC 4
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#define NUM_OF_BANKS 8
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#define LAST_BANK 0x1C
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#define BANK_SIZE 0x20
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#define BLOCK_SIZE scacheLineSize /* defined in pdiag.h */
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#define LINE_SIZE scacheLineSize
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#define CACHE_SIZE scacheSetSize /* use for hashing funct */
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#define PAGE_SIZE pageSize
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#define ECC_MASK 0x7F
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#define PASS 0
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#define FAIL 1
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/*------------------------------------------------------------------------+
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| failure code. |
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+------------------------------------------------------------------------*/
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#define CONST_ERR 1 /* stuck at one or zero fault */
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#define AINA_ERR 2 /* addressing fault */
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#define FILL_ERR 5 /* line fill error. */
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#define FLUSH_ERR 6 /* line flush error. */
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#define K0MOD_ERR 7 /* cache data error. */
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#define K1MOD_ERR 8 /* mem changed from writing to K0*/
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#define ECC_ERR 9 /* bad data from ecc array. */
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#define EGEN_ERR 10 /* bad generated ecc. */
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#define SYND_ERR 11 /* bad generated syndrom. */
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#define SBEDET_ERR 12 /* single-bit error detection err*/
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#define MBEDET_ERR 13 /* multi-bit error detection err*/
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#define SBC_MEMERR_MASK 0xF /* least-signif 4 bits */
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#define CPU_IMASK (SR_IEC|SR_IBIT3) /* IP2 (sbc interrupt) only */
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/*------------------------------------------------------------------------+
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| define constant |
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+------------------------------------------------------------------------*/
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#define ABLES 0xAAAAAAAA
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#define FIVES 0x55555555
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#define END_PAT 0xDEADBEEF
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/*------------------------------------------------------------------------+
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| CPU INTERRUPT PENDING DEF |
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+------------------------------------------------------------------------*/
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#define SR_EXTINT 0x00000400 /* SR external interrupt pending */
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#define SR_FPUINT 0x00000800 /* SR fpu interrupt pending */
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#define SR_TMRINT 0x00001000 /* SR timer interrupt pending */
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/*------------------------------------------------------------------------+
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| define address space |
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+------------------------------------------------------------------------*/
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#define CPU_BRDADDR 0x3 /* do nt respend to any address */
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#define MEM_BRDADDR 0xAAAAA800 /* respond to 0x002xxxxxxx */
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#define BASE_ADDR 0xA0000000 /* base address for memory test */
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#define BRD_SLOT_1 0x00010000 /* board slot 1 */
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#define BRD_SLOT_2 0x00020000 /* board slot 2 */
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#define BRD_SLOT_3 0x00030000 /* board slot 3 */
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#define BRD_SLOT_4 0x00040000 /* board slot 4 */
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#define BRD_SLOT_5 0x00050000 /* board slot 5 */
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#define BRD_SLOT_6 0x00060000 /* board slot 6 */
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#define CPU_SLOT_NO ((BRD_SLOT_1) >> 16)
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#define MEM_SLOT_NO ((BRD_SLOT_3) >> 16)
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/*------------------------------------------------------------------------+
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| Define macros |
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+------------------------------------------------------------------------*/
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#define MAP_ADDRESS(exec_mode, first_addr, last_addr) \
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sll first_addr, 3; \
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srl first_addr, 5; \
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sll first_addr, 2; /* align to word address */ \
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sll last_addr, 3; \
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srl last_addr, 5; \
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sll last_addr, 2; /* align to word address */ \
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li v0, K0BASE; \
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and v1, exec_mode, D_MASK; \
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beq v1, D_CACHED, 1f; \
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nop; \
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li v0, K1BASE; \
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1: \
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or first_addr, v0; \
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or last_addr, v0;
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#define MemIBit 3 /* use bit3 interrupt for ecc error */
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#define MemIMask (1 << MemIBit) /* cpu's bc interrupt vector mask */
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#define EccIntr ((MemIBit << 5)| MemIntEna | EnaSErrInt | EnaMErrDet)
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#define EccOn (EnaSErrLocCmp | EnaSErrCorrect | EccIntr)
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/*------------------------------------------------------------------------+
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| |
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+------------------------------------------------------------------------*/
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#define DisableEcc(mslot) \
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and v0, mslot, 0x0f; \
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sll v0, 16; \
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sw zero, CSR_MEMCTL(v0);
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#define GetCpuSlot(Reg) \
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lw Reg, CSR_CTLMISC; \
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srl Reg, 24
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#define EnableExternIntr \
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mfc0 v0, C0_SR; \
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nop; \
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or v0, CPU_IMASK; \
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mtc0 v0, C0_SR; \
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nop
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#define EnableEcc(mslot) \
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/* lw v0, CSR_CTLMISC; */ \
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sll v1, mslot, 16; \
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/* sll v0, 4; */ \
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/* srl v0, 28; */ \
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li v0, 1; /* presume cpu brd in slot 1 */ \
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sll v0, 7; \
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or v0, EccOn; \
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sw v0, CSR_MEMCTL(v1);
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#define SetBankMask(mslot) \
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sll v1, mslot, 16; \
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li v0, 0x80; \
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sw v0, CSR_MEMECC(v1);
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#define ClrIVect \
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not v0, zero; \
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sw v0, (CSR_IVECTCLR)|(1<<16);
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#define SetIVectMask(bmask) \
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li v0, bmask; \
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sw v0, (CSR_IVECTMASK)|(1<<16);
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/*------------------------------------------------------------------------+
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| macro to print number of passes. |
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+------------------------------------------------------------------------*/
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#define PrintPasses(pmsg, count) \
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la a0, pmsg; \
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jal puts; \
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nop; \
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and a0, count, 0x7fff; \
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jal putdec; \
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move a1, zero
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/*------------------------------------------------------------------------+
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| print memory test's title. |
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+------------------------------------------------------------------------*/
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#define PrintTitle(tmsg,tmode,brdmsg,slotreg) \
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la a0, tmsg; \
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jal puts; \
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nop; \
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jal date; \
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nop; \
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la a0, tmode; \
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jal puts; \
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nop; \
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la a0, brdmsg; \
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jal puts; \
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nop; \
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and a0, slotreg, 0x0f; \
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jal putdec; \
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li a1, 2
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/*------------------------------------------------------------------------+
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| load cache. |
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+------------------------------------------------------------------------*/
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#define CacheLoad(start, end) \
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la a0, start; \
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la a1, end; \
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jal cache_load; \
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nop
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#ifndef LOCORE
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/*------------------------------------------------------------------------+
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| Define tests tables: |
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+------------------------------------------------------------------------*/
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typedef struct test_table {
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int run_flag;
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int (*test_rtn)();
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char *test_desc;
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} TestTable;
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typedef struct status { /* diagnostic's status struct */
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u_int verb; /* verbose flag */
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u_int act; /* action flag */
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u_int err; /* error flag */
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} DFlag;
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#endif !LOCORE
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