calmsacibis995
146 lines
4.1 KiB
C
146 lines
4.1 KiB
C
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/**************************************************************************
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* *
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* Copyright (C) 1993, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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/************************************************************************
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* *
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* intr_timer.c - Verify IP19 RTSC/interval timer interrupt *
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* *
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************************************************************************/
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#ident "$Revision: 1.5 $"
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#include <sys/types.h>
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#include <sys/sbd.h>
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#include <sys/EVEREST/everest.h>
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#include <sys/EVEREST/IP19.h>
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#include <setjmp.h>
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#include <fault.h>
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#include "pattern.h"
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#include "everr_hints.h"
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#include "ide_msg.h"
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#include "intr.h"
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#include "ip19.h"
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#include "prototypes.h"
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static __psunsigned_t cpu_loc[2];
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static jmp_buf fault_buf;
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#define ONESECNS 0x3b9aca00 /* one second in nanoseconds */
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#define CPERIOD 0x14 /* default CPERIOD */
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/*
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* Simple synchronous test. R4000 interrupts off
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*/
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intr_timer()
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{
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uint retval;
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__psunsigned_t osr, slot, proc, oile, ocompare, nsperiod, tmp;
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retval=0;
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getcpu_loc(cpu_loc);
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msg_printf(INFO, " (intr_timer) \n");
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slot = cpu_loc[0];
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proc = cpu_loc[1];
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msg_printf(VRB, "Running CPU %d on IP19 in slot %d\n", cpu_loc[1], cpu_loc[0]);
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osr = get_sr();
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ocompare = EV_GET_LOCAL(EV_RO_COMPARE);
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nsperiod = EV_GETCONFIG_REG(slot, proc, EV_CPERIOD);
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set_sr(osr & ~SR_IE); /* R4000 interrupts off */
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tmp = EV_GET_LOCAL(EV_RTC);
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msg_printf(DBG, "nsperiod : 0x%llx\n", nsperiod);
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msg_printf(DBG, "EV_RTC : 0x%llx\n", tmp);
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if (tmp == EV_GET_LOCAL(EV_RTC)) {
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msg_printf(ERR, "RTC not running - test aborted\n");
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set_sr(osr);
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return (1);
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}
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if (setjmp(fault_buf))
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{
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if (get_cause() & CAUSE_IP4)
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{
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msg_printf(DBG, "Received timer interrupt: cause 0x%x\n", get_cause());
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/* Clear pending interrupt. */
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EV_SET_LOCAL(EV_CIPL124, 0x2);
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tmp = EV_GET_LOCAL(EV_RO_COMPARE);
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/* Verify R4000 cause -- IP4 bit should now be zero. */
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if (get_cause() & CAUSE_IP4) {
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err_msg(TIMER_CAUSECLR, cpu_loc);
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retval = 1;
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}
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}
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else
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{
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err_msg(TIMER_INV_INT, cpu_loc);
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retval = 1;
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}
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if (retval)
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show_fault();
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}
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else
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{
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nofault = fault_buf;
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/* Enable level 1 intrs. */
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oile = EV_GET_LOCAL(EV_ILE);
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EV_SET_LOCAL(EV_ILE, oile | EV_CMPINT_MASK);
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msg_printf(DBG, "EV_ILE contents set to 0x%llx\n", EV_GET_LOCAL(EV_ILE));
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/* enable interrupt for level 1 */
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set_sr(osr | SR_IBIT4 | SR_IE);
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msg_printf(DBG, "Status register set to 0x%x\n", get_sr());
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/*
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* set up timer interrupt
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*/
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tmp = EV_GET_LOCAL(EV_RTC) + 0x100000 * CPERIOD;
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msg_printf(DBG, "Compare value is 0x%llx\n", tmp);
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EV_SETCONFIG_REG(slot, proc, EV_CMPREG0, tmp);
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EV_SETCONFIG_REG(slot, proc, EV_CMPREG1, tmp >> 8);
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EV_SETCONFIG_REG(slot, proc, EV_CMPREG2, tmp >> 16);
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EV_SETCONFIG_REG(slot, proc, EV_CMPREG3, tmp >> 24);
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/*
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* make sure the intr happened
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* While we're waiting check that (ns) clock is ticking
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*/
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while ((uint) tmp > (uint)(EV_GET_LOCAL(EV_RTC)))
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msg_printf(DBG, "EV_RTC : 0x%llx EV_RO_COMPARE : 0x%llx\n", EV_GET_LOCAL(EV_RTC), EV_GET_LOCAL(EV_RO_COMPARE));
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clear_nofault();
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err_msg(TIMER_NOINT, cpu_loc);
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retval = 1;
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show_fault();
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}
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/* Leave things tidy */
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set_sr(osr);
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/* Disable level 1 intrs. */
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EV_SET_LOCAL(EV_ILE, oile);
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/* Restore original RTSC compare register */
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EV_SETCONFIG_REG(slot, proc, EV_CMPREG0, tmp);
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EV_SETCONFIG_REG(slot, proc, EV_CMPREG1, tmp >> 8);
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EV_SETCONFIG_REG(slot, proc, EV_CMPREG2, tmp >> 16);
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EV_SETCONFIG_REG(slot, proc, EV_CMPREG3, tmp >> 24);
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msg_printf(INFO, "Completed timer interrupt test\n");
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return(retval);
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}
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