51 lines
916 B
ArmAsm
51 lines
916 B
ArmAsm
/*
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* bb_cacheasm.s -- blackbird(tfp) Cache manipulation primitives
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*/
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#include <regdef.h>
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#include <sys/cpu.h>
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#include <sys/sbd.h>
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#include <asm.h>
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#include "ip21.h"
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LEAF(read_tag)
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### just stubbed in for now!!
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j ra
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END(read_tag)
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/*
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* unsigned GetCacheErr()
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*
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* Returns the cp0 Cache_Err register (read only).
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*/
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LEAF(GetCacheErr)
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.set noreorder
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#ifndef TFP
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mfc0 v0, C0_CACHEERR
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nop
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#endif
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j ra
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nop
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.set reorder
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END(GetCacheErr)
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/* pd_hwbinv(caddr): Primary Data cache Hit Writeback Invalidate.
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* a0: K0-seg virtual address */
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LEAF(pd_hwbinv)
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#ifndef TFP
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li t0, WD_ALIGN_MASK # cacheops must be wd aligned
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not t0
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and a0, a0, t0
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.set noreorder
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cache CACH_PD|C_HWBINV, 0(a0)
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nop
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nop
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nop
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.set reorder
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#endif
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j ra
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END(pd_hwbinv)
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