449 lines
17 KiB
C
449 lines
17 KiB
C
/*
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* everr_hints.h
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*
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* Copyright 1991, Silicon Graphics, Inc.
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* All Rights Reserved.
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*
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* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
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* the contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of Silicon Graphics, Inc.
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*
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* RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
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* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
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* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
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* rights reserved under the Copyright Laws of the United States.
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*/
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#ident "arcs/ide/EVEREST/include/everr_hints.h $Revision: 1.36 $"
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/* EVEREST subsystem specific error hints to be used in the EVEREST IDE */
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#include <sys/types.h>
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#include <err_hints.h>
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#define TLBR_HI (IP19_TLB | 1)
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#define TLBR_EVENLO (IP19_TLB | 2)
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#define TLBR_ODDLO (IP19_TLB | 3)
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#define TLBM_CUWEXCP (IP19_TLB | 4)
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#define TLBM_CUW (IP19_TLB | 5)
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#define TLBM_UCWEXCP (IP19_TLB | 6)
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#define TLBM_UCW (IP19_TLB | 7)
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#define TLBM_UCWREXCP (IP19_TLB | 8)
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#define TLBM_UCWR (IP19_TLB | 9)
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#define TLBM_UCRWR (IP19_TLB | 10)
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#define TLBMOD_BVADDR (IP19_TLB | 11)
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#define TLBMOD_NOEXCP (IP19_TLB | 12)
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#define TLBMOD_UNEXP (IP19_TLB | 13)
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#define TLBMOD_MOD (IP19_TLB | 14)
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#define TLBC_PERR (IP19_TLB | 15)
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#define TLBC_WR (IP19_TLB | 16)
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#define TLBC_CEXCP (IP19_TLB | 17)
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#define TLBC_CRW (IP19_TLB | 18)
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#define TLBC_UEXCP (IP19_TLB | 19)
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#define TLBC_URW (IP19_TLB | 20)
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#define TLBP_UNEXP (IP19_TLB | 21)
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#define TLBP_BVADDR (IP19_TLB | 22)
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#define TLBP_NOEXCP (IP19_TLB | 23)
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#define TLBPR_ERR (IP19_TLB | 24)
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#define TLBV_BVADDR (IP19_TLB | 25)
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#define TLBV_NOEXCP (IP19_TLB | 26)
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#define TLBX_UNEXP (IP19_TLB | 27)
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#define TLBX_ERR (IP19_TLB | 28)
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#define TLBG_UNEXP (IP19_TLB | 29)
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#define FADDSUBD_RES (IP19_FPU | 1)
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#define FADDSUBD_STS (IP19_FPU | 2)
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#define FADDSUBD_FIX (IP19_FPU | 3)
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#define FADDSUBS_RES (IP19_FPU | 4)
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#define FADDSUBS_STS (IP19_FPU | 5)
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#define FADDSUBS_FIX (IP19_FPU | 6)
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#define FDIVZRO_STS (IP19_FPU | 7)
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#define FDIVZRO_DIVD (IP19_FPU | 8)
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#define FDIVZRO_DIVS (IP19_FPU | 9)
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#define FINEX_STS (IP19_FPU | 10)
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#define FINV_NOEXCP (IP19_FPU | 11)
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#define FINV_STS (IP19_FPU | 12)
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#define FINV_FIX (IP19_FPU | 13)
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#define FCMPUT_UNEXP (IP19_FPU | 14)
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#define FMULDIVD_DIV (IP19_FPU | 15)
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#define FMULDIVD_MUL (IP19_FPU | 16)
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#define FMULDIVS_DIV (IP19_FPU | 17)
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#define FMULDIVS_MUL (IP19_FPU | 18)
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#define FMULSUBD_RES (IP19_FPU | 19)
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#define FMULSUBD_FIX (IP19_FPU | 20)
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#define FMULSUBD_STS (IP19_FPU | 21)
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#define FMULSUBS_RES (IP19_FPU | 22)
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#define FMULSUBS_FIX (IP19_FPU | 23)
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#define FMULSUBS_STS (IP19_FPU | 24)
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#define FOVER_STS (IP19_FPU | 25)
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#define FCOMPUTE_S (IP19_FPU | 26)
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#define FCOMPUTE_D (IP19_FPU | 27)
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#define FPMEM_DATA (IP19_FPU | 28)
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#define FPMEM_INVD (IP19_FPU | 29)
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#define FPREG_DATA (IP19_FPU | 30)
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#define FPREG_INVD (IP19_FPU | 31)
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#define FUNDER_EXCP (IP19_FPU | 32)
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#define FUNDER_NOEXCP (IP19_FPU | 33)
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/* IO4 Mapram related message numbers */
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#define MAPR_GENR (IO4_MAPRAM | 1)
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#define MAPR_RDWR (IO4_MAPRAM | 2)
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#define MAPR_ADDR (IO4_MAPRAM | 3)
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#define MAPR_WALK1 (IO4_MAPRAM | 4)
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#define MAPR_ERR (IO4_MAPRAM | 5)
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/* IO4 SCSI numbers */
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#define S1_REG_RW (IO4_SCIP | 1)
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#define S1_ADAP (IO4_SCIP | 2)
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#define WD95_REG_RW (IO4_SCSI | 1)
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#define WD95_REG_RW2 (IO4_SCSI | 2)
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#define WD95_PRESNT1 (IO4_SCSI | 3)
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#define WD95_PRESNT2 (IO4_SCSI | 4)
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#define WD95_PRESNT3 (IO4_SCSI | 5)
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#define WD95_INTR_LEV (IO4_SCSI | 6)
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#define WD95_INTR_HP (IO4_SCSI | 7)
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#define WD95_INTR_NOCAUSE (IO4_SCSI | 8)
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#define WD95_INTR_IPNZ (IO4_SCSI | 9)
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#define WD95_INTR_HPNZ (IO4_SCSI | 0xa)
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#define WD95_INTR_CANZ (IO4_SCSI | 0xb)
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#define WD95_INTR_NOINT (IO4_SCSI | 0xc)
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#define WD95_INTR_NOEBUS (IO4_SCSI | 0xd)
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#define WD95_INTR_ENOCPU (IO4_SCSI | 0xe)
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#define WD95_TALK (IO4_SCSI | 0xf)
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#define WD95_SC_TIMEOUT (IO4_SCSI | 0x10)
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#define WD95_SC_HARDERR (IO4_SCSI | 0x11)
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#define WD95_SC_PARITY (IO4_SCSI | 0x12)
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#define WD95_SC_MEMERR (IO4_SCSI | 0x13)
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#define WD95_SC_CMDTIME (IO4_SCSI | 0x14)
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#define WD95_SC_ALIGN (IO4_SCSI | 0x15)
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#define WD95_SC_ATTN (IO4_SCSI | 0x16)
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#define WD95_SC_REQ (IO4_SCSI | 0x17)
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#define WD95_SC_UNKNOWN (IO4_SCSI | 0x18)
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#define WD95_DMA_RD (IO4_SCSI | 0x19)
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#define WD95_DMA_RDCNT (IO4_SCSI | 0x1a)
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#define WD95_DMA_WRCNT (IO4_SCSI | 0x1b)
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#define WD95_DMA_WR (IO4_SCSI | 0x1c)
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#define WD95_DMA_SK (IO4_SCSI | 0x1d)
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#define WD95_DMA_WRDATA (IO4_SCSI | 0x1e)
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#define WD95_INTR_NOCACHE (IO4_SCSI | 0x1f)
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#define WD95_INTR_IAEBUSREG (IO4_SCSI | 0x20)
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#define WD95_INTR_IOAORIG (IO4_SCSI | 0x21)
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#define WD95_INTR_IOADDR (IO4_SCSI | 0x22)
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/* Fchip related message numbers */
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#define F_GENRIC (IO4_FCHIP | 1)
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#define F_BADVER (IO4_FCHIP | 2)
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#define F_INVMID (IO4_FCHIP | 3)
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#define F_BADREG (IO4_FCHIP | 4)
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#define F_LWREG (IO4_FCHIP | 5)
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#define F_INTSET (IO4_FCHIP | 6)
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#define F_INTRST (IO4_FCHIP | 7)
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#define F_ERRCLR (IO4_FCHIP | 8)
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#define F_BADRADR (IO4_FCHIP | 9)
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#define F_SWERR (IO4_FCHIP | 10)
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#define F_BADGVER (IO4_FCHIP | 11)
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/* VMEcc related message numbers */
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#define VMEINT_TO (IO4_VMECC | 1)
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#define VMEINT_ERR (IO4_VMECC | 2)
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#define VME_REGR (IO4_VMECC | 3)
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#define VME_BADMID (IO4_VMECC | 4)
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#define VME_BADREG (IO4_VMECC | 5)
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#define VME_BADRADR (IO4_VMECC | 6)
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#define VME_BADCLR (IO4_VMECC | 7)
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#define VME_BADCAU (IO4_VMECC | 8)
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#define VME_INTSET (IO4_VMECC | 9)
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#define VME_INTCLR (IO4_VMECC | 10)
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#define VME_BUSERR (IO4_VMECC | 11)
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#define VME_BUSUNE (IO4_VMECC | 12)
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#define VME_DMAERR (IO4_VMECC | 13)
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#define VME_DMARD (IO4_VMECC | 14)
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#define VME_DMAWR (IO4_VMECC | 15)
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#define VME_DMAXFER (IO4_VMECC | 16)
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#define VME_IGENR (IO4_VMECC | 17)
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/* Messages numbers used by the Loopback read operation */
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#define VME_A32L1 (IO4_VMECC | 18)
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#define VME_A32L2 (IO4_VMECC | 19)
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#define VME_A24L1 (IO4_VMECC | 20)
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#define VME_A24L2 (IO4_VMECC | 21)
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#define VME_LPBKB (IO4_VMECC | 22) /* Loopback byte operation failed */
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#define VME_LPBKH (IO4_VMECC | 23) /* Loopback half operation failed */
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#define VME_LPBKW (IO4_VMECC | 24) /* Loopback word operation failed */
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#define VME_LPWRB (IO4_VMECC | 25) /* byte write operation failed */
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#define VME_LPWRH (IO4_VMECC | 26) /* half write operation failed */
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#define VME_LPWRW (IO4_VMECC | 27) /* word write operation failed */
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#define VME_LPCOB (IO4_VMECC | 28) /* byte read in coh space failed */
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#define VME_LPCOH (IO4_VMECC | 29) /* half read in coh space failed */
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#define VME_LPCOW (IO4_VMECC | 30) /* word read in coh space failed */
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#define VME_XINTR (IO4_VMECC | 31) /* got exception in vme_xintr */
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#define VME_XNOINT (IO4_VMECC | 31) /* Got no external intr */
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#define VME_XIACK (IO4_VMECC | 32) /* IACK from external board is bad */
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#define VME_XCPUINT (IO4_VMECC | 33) /* CPU did not get xternal intr */
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#define VME_ENGERR (IO4_VMECC | 34) /* DMA engine reported error!! */
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#define VME_SWERR (IO4_VMECC | 39)
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/* VMEcc CDSIO test related numbers */
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#define CDSIO_GEN (IO4_VMECC | 40)
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#define CDSIO_RDY (IO4_VMECC | 41)
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#define CDSIO_ERR (IO4_VMECC | 42)
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#define CDSIO_ERR1 (IO4_VMECC | 43)
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#define CDSIO_DERR (IO4_VMECC | 44)
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#define CDSIO_IGEN (IO4_VMECC | 45)
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#define CDSIO_BINT (IO4_VMECC | 46)
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#define CDSIO_VECT (IO4_VMECC | 47)
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#define CDSIO_SINT (IO4_VMECC | 48)
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/* DANG Chip related messages */
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#define DANG_GENRIC (IO4_DANG | 0)
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/* used by dang pio register test */
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#define DANG_BADREG (IO4_DANG | 1)
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#define DANG_INTSET (IO4_DANG | 2)
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#define DANG_ERRCLR (IO4_DANG | 3)
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#define DANG_BADRADR (IO4_DANG | 4)
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#define DANG_SWERR (IO4_DANG | 5)
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/* used by gio shared ram test */
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#define DANG_BADSHRAM (IO4_DANG | 6)
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/* used by master dma test */
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#define DANG_BADDMA (IO4_DANG | 7)
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#define DANG_BADDDATA (IO4_DANG | 8)
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#define DANG_DMAVECT (IO4_DANG | 9)
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#define DANG_DMACOMP (IO4_DANG | 10)
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/* IO4 Ethernet messages */
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#define ENET_XMIT (IO4_EPC | 0x1)
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#define ENET_RCV (IO4_EPC | 0X2)
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#define ENET_DATA (IO4_EPC | 0X3)
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#define ENET_TSTAT (IO4_EPC | 0X4)
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#define ENET_RSTAT (IO4_EPC | 0X5)
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#define FECC_IBIT (MC3_MD_HINT | 0x1)
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#define FECC_CACHEWR (MC3_MD_HINT | 0x2)
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#define FECC_SET_ECC (MC3_MD_HINT | 0x3)
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#define FECC_NOIP6ERR (MC3_MD_HINT | 0x4)
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#define FECC_ERTOIP (MC3_MD_HINT | 0x5)
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#define FECC_IBITOFF (MC3_MD_HINT | 0x6)
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#define FECC_CERTOIP (MC3_MD_HINT | 0x7)
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#define ADDRU_ERR (MC3_BANK_HINT | 0x1)
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#define CACHEMEM_ERR (MC3_BANK_HINT | 0x2)
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#define CONNECT_ERR (MC3_BANK_HINT | 0x3)
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#define MARCHX_ERR (MC3_BANK_HINT | 0x4)
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#define MARCHY_ERR (MC3_BANK_HINT | 0x5)
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#define MEM_ECC_ERR (MC3_BANK_HINT | 0x6)
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#define MEM_PAT_ERR (MC3_BANK_HINT | 0x7)
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#define MEMWLK_ERR (MC3_BANK_HINT | 0x8)
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#define MEMWRRD_ERR (MC3_BANK_HINT | 0x9)
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#define MEMADDR_ERR (MC3_BANK_HINT | 0xa)
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#define MEMADDR_HINT (MC3_BANK_HINT | 0xb)
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#define DECODE_ERR (MC3_BANK_HINT | 0xc)
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#define DECODE_Y_ERR (MC3_BANK_HINT | 0xd)
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#define DECODE_RANGE_ERR (MC3_BANK_HINT | 0xe)
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#define MEMBWRRD_ERR (MC3_BANK_HINT | 0xf)
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#define DBLMARCHY_ERR (MC3_BANK_HINT | 0x10)
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#define MEM_KH_ERR (MC3_BANK_HINT | 0x11)
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#define MEMERR_REG (MC3_BANK_HINT | 0x12)
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#define MC3INTR_IP6 (MC3_BANK_HINT | 0x13)
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#define MC3INTR_IP6NC (MC3_BANK_HINT | 0x14)
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#define MC3INTR_ERTOIP (MC3_BANK_HINT | 0x15)
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#define MC3INTR_CERTOIP (MC3_BANK_HINT | 0x16)
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#define MC3_REG_ERR (MC3_MA_HINT | 0x1)
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#define MC3_INTR_ERR (MC3_MA_HINT | 0x2)
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/* C A C H E M O D U L E E R R O R C O D E S */
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#define TAGHI_ERR1 (IP19_PCACHE | 0x1)
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#define TAGHI_ERR2 (IP19_PCACHE | 0x2)
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#define TAGLO_ERR1 (IP19_PCACHE | 0x3)
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#define TAGLO_ERR2 (IP19_PCACHE | 0x4)
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#define DTAGWLK_ERR1 (IP19_PCACHE | 0x5)
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#define DTAGADR_ERR1 (IP19_PCACHE | 0x6)
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#define DTAGKH_ERR1 (IP19_PCACHE | 0x7)
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#define DTAGKH_ERR2 (IP19_PCACHE | 0x8)
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#define DTAGKH_ERR3 (IP19_PCACHE | 0x9)
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#define DTAGKH_ERR4 (IP19_PCACHE | 0xa)
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#define DTAGKH_ERR5 (IP19_PCACHE | 0xb)
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#define DTAGKH_ERR6 (IP19_PCACHE | 0xc)
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#define ITAGWLK_ERR1 (IP19_PCACHE | 0xd)
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#define ITAGADR_ERR1 (IP19_PCACHE | 0xe)
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#define ITAGKH_ERR1 (IP19_PCACHE | 0xf)
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#define ITAGKH_ERR2 (IP19_PCACHE | 0x10)
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#define ITAGKH_ERR3 (IP19_PCACHE | 0x11)
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#define ITAGKH_ERR4 (IP19_PCACHE | 0x12)
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#define ITAGKH_ERR5 (IP19_PCACHE | 0x13)
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#define ITAGKH_ERR6 (IP19_PCACHE | 0x14)
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#define SDTAGWLK_ERR1 (IP19_SCACHE | 0x15)
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#define SDTAGADR_ERR1 (IP19_SCACHE | 0x16)
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#define SDTAGKH_ERR1 (IP19_SCACHE | 0x17)
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#define DTAGPAR_ERR1 (IP19_PCACHE | 0x18)
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#define DTAGCMP_ERR1 (IP19_PCACHE | 0x19)
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#define DTAGCMP_ERR2 (IP19_PCACHE | 0x20)
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#define DTAGFUNCT_ERR1 (IP19_PCACHE | 0x21)
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#define DTAGFUNCT_ERR2 (IP19_PCACHE | 0x22)
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#define DSLIDEDATA_ERR1 (IP19_CACHE | 0x23)
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#define DSLIDEDATA_ERR2 (IP19_CACHE | 0x24)
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#define DSLIDEADR_ERR1 (IP19_CACHE | 0x25)
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#define DSLIDEADR_ERR2 (IP19_CACHE | 0x26)
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#define DKH_ERR1 (IP19_CACHE | 0x27)
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#define DKH_ERR2 (IP19_CACHE | 0x28)
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#define DKH_ERR3 (IP19_CACHE | 0x29)
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#define DKH_ERR4 (IP19_CACHE | 0x2a)
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#define DKH_ERR5 (IP19_CACHE | 0x2b)
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#define DKH_ERR6 (IP19_CACHE | 0x2c)
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#define DSDWLK_ERR1 (IP19_CACHE | 0x2d)
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#define DSDWLK_ERR2 (IP19_CACHE | 0x2e)
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#define SDAINA_ERR1 (IP19_SCACHE | 0x2f)
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#define SDAINA_ERR2 (IP19_SCACHE | 0x30)
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#define DFUNCT_ERR1 (IP19_PCACHE | 0x31)
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#define DFUNCT_ERR2 (IP19_PCACHE | 0x32)
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#define DFUNCT_ERR3 (IP19_PCACHE | 0x33)
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#define DFUNCT_ERR4 (IP19_PCACHE | 0x34)
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#define DFUNCT_ERR5 (IP19_PCACHE | 0x35)
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#define DPAR_ERR1 (IP19_PCACHE | 0x36)
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#define ITAGPAR_ERR1 (IP19_PCACHE | 0x37)
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#define ITAGCMP_ERR1 (IP19_PCACHE | 0x38)
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#define ITAGCMP_ERR2 (IP19_PCACHE | 0x39)
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#define ITAGCMP_ERR3 (IP19_PCACHE | 0x3a)
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#define ITAGFUNC_ERR1 (IP19_PCACHE | 0x3b)
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#define ITAGFUNC_ERR2 (IP19_PCACHE | 0x3c)
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#define ITAGCMP_ERR4 (IP19_PCACHE | 0x3d)
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#define ISLIDED_ERR1 (IP19_PCACHE | 0x3f)
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#define ISLIDED_ERR2 (IP19_PCACHE | 0x40)
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#define IAINA_ERR1 (IP19_CACHE | 0x41)
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#define IFUNCT_ERR1 (IP19_CACHE | 0x42)
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#define IPAR_ERR1 (IP19_PCACHE | 0x43)
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#define IHITINV_ERR1 (IP19_PCACHE | 0x44)
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#define IHITINV_ERR2 (IP19_PCACHE | 0x45)
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#define IHITINV_ERR3 (IP19_PCACHE | 0x46)
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#define IHITWB_ERR1 (IP19_PCACHE | 0x47)
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#define IHITWB_ERR2 (IP19_PCACHE | 0x48)
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#define IHITWB_ERR3 (IP19_PCACHE | 0x49)
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#define ECCREG_ERR1 (IP19_PCACHE | 0x4a)
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#define ECCREG_ERR2 (IP19_PCACHE | 0x4b)
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#define DHITINV_ERR1 (IP19_PCACHE | 0x4c)
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#define DHITINV_ERR2 (IP19_PCACHE | 0x4d)
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#define DHITINV_ERR3 (IP19_PCACHE | 0x4e)
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#define DHITWB_ERR1 (IP19_PCACHE | 0x4f)
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#define DHITWB_ERR2 (IP19_PCACHE | 0x50)
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#define DHITWB_ERR3 (IP19_PCACHE | 0x51)
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#define DHITWB_ERR4 (IP19_PCACHE | 0x52)
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#define DHITWB_ERR5 (IP19_PCACHE | 0x53)
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#define DIRTYWBW_ERR1 (IP19_PCACHE | 0x54)
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#define DIRTYWBW_ERR2 (IP19_PCACHE | 0x55)
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#define DREFILL_ERR1 (IP19_PCACHE | 0x56)
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#define DREFILL_ERR2 (IP19_PCACHE | 0x57)
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#define SDIRTYWBW_ERR1 (IP19_SCACHE | 0x58)
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#define SDIRTYWBW_ERR2 (IP19_SCACHE | 0x59)
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#define SDIRTYWBH_ERR1 (IP19_SCACHE | 0x5a)
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#define SDIRTYWBH_ERR2 (IP19_SCACHE | 0x5b)
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#define SDIRTYWBB_ERR1 (IP19_SCACHE | 0x5c)
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#define SDIRTYWBB_ERR2 (IP19_SCACHE | 0x5d)
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#define SDTAGECC_ERR1 (IP19_SCACHE | 0x5e)
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#define SDTAGECC_ERR2 (IP19_SCACHE | 0x5f)
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#define SDHITINV_ERR1 (IP19_SCACHE | 0x60)
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#define SDHITINV_ERR2 (IP19_SCACHE | 0x61)
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#define SDHITINV_ERR3 (IP19_SCACHE | 0x62)
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#define SDHITINV_ERR4 (IP19_SCACHE | 0x63)
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#define SDHITINV_ERR5 (IP19_SCACHE | 0x64)
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#define SDHITINV_ERR6 (IP19_SCACHE | 0x65)
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#define SDHITINV_ERR7 (IP19_SCACHE | 0x66)
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#define SDHITWB_ERR1 (IP19_SCACHE | 0x67)
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#define SDHITWB_ERR2 (IP19_SCACHE | 0x68)
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#define SDHITWB_ERR3 (IP19_SCACHE | 0x69)
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#define SDHITWB_ERR4 (IP19_SCACHE | 0x6a)
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#define SDHITWB_ERR5 (IP19_SCACHE | 0x6b)
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#define SDHITWB_ERR6 (IP19_SCACHE | 0x6c)
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#define SDHITWB_ERR7 (IP19_SCACHE | 0x6d)
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#define SDHITWBINV_ERR1 (IP19_SCACHE | 0x6e)
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#define SDHITWBINV_ERR2 (IP19_SCACHE | 0x6f)
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#define SDHITWBINV_ERR3 (IP19_SCACHE | 0x70)
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#define SDHITWBINV_ERR4 (IP19_SCACHE | 0x71)
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#define SDHITWBINV_ERR5 (IP19_SCACHE | 0x72)
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#define SDHITWBINV_ERR6 (IP19_SCACHE | 0x73)
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#define SDHITWBINV_ERR7 (IP19_SCACHE | 0x74)
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#define CLSTR_ERR1 (IP19_SCACHE | 0x75)
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#define CLSTR_ERR2 (IP19_SCACHE | 0x76)
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#define CLSTRWB_ERR1 (IP19_SCACHE | 0x77)
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#define CLSTRWB_ERR2 (IP19_SCACHE | 0x78)
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#define CLSTRWB_ERR3 (IP19_SCACHE | 0x79)
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#define CSTRESS_ERR (IP19_SCACHE | 0x7a)
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#define CSTRESS_PDERR (IP19_PCACHE | 0x7b)
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#define CSTRESS_SERR (IP19_SCACHE | 0x7c)
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#define CSTATE0_ERR (IP19_CACHE | 0x7d)
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#define CSTATE1_ERR (IP19_CACHE | 0x7e)
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#define CSTATE4_ERR (IP19_CACHE | 0x7f)
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#define CSTATE5_ERR (IP19_CACHE | 0x80)
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#define CSTATE6_ERR (IP19_CACHE | 0x81)
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#define CSTATE7_ERR (IP19_CACHE | 0x82)
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#define CSTATE12_ERR (IP19_CACHE | 0x83)
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#define CSTATE13_ERR (IP19_CACHE | 0x84)
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#define CSTATE14_ERR (IP19_CACHE | 0x85)
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#define CSTATE_STATE (IP19_CACHE | 0x86)
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#define CSTATE_ADDR (IP19_CACHE | 0x87)
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#define CSTATE_MEM (IP19_CACHE | 0x88)
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#define CSTATE_WRBK (IP19_CACHE | 0x89)
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#define CSTATE_2ND (IP19_CACHE | 0x8a)
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#define MP_EXCP (IP19_CACHE | 0x8b)
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#define MP_CDATA (IP19_CACHE | 0x8c)
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#define MP_CSIZE (IP19_CACHE | 0x8d)
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#define MP_JUMPER (IP19_CACHE | 0x8e)
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/* IP19 CC related message numbers */
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#define LOCAL_REGERR (IP19_CC | 0x1)
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#define CONFIG_ERR (IP19_CC | 0x2)
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#define BUSTAG_ERR (IP19_CC | 0x3)
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#define INT_L0_IP (IP19_CC | 0x4)
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#define INT_L0_HPIL (IP19_CC | 0x5)
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#define INT_L0_CAUSE (IP19_CC | 0x6)
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#define INT_L0_IPCLR (IP19_CC | 0x7)
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#define INT_L0_HPILCLR (IP19_CC | 0x8)
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#define INT_L0_CAUSECLR (IP19_CC | 0x9)
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#define INT_L0_CEL (IP19_CC | 0xa)
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#define INT_L0_CELHI (IP19_CC | 0xb)
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#define INT_L0_CELLO (IP19_CC | 0xc)
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#define INT_L0_CELCLR (IP19_CC | 0xd)
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#define INT_L0_MULT (IP19_CC | 0xe)
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#define INT_L0_MULTIP0 (IP19_CC | 0xf)
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#define INT_L0_MULTIP1 (IP19_CC | 0x10)
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#define INT_L0_MULTCL0 (IP19_CC | 0x11)
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#define INT_L0_MULTCL1 (IP19_CC | 0x12)
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#define INT_L0_MULTCLH (IP19_CC | 0x13)
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#define INT_L0_MULTCLC (IP19_CC | 0x14)
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#define INT_L0_NOINT (IP19_CC | 0x15)
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#define INT_L3_IP6 (IP19_CC | 0x16)
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#define INT_L3_ERTOIP (IP19_CC | 0x17)
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#define INT_L3_IP6NC (IP19_CC | 0x18)
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#define INT_L3_CERTOIP (IP19_CC | 0x19)
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#define INT_L3_NOINT (IP19_CC | 0x1a)
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#define TIMER_INV_INT (IP19_CC | 0x1b)
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#define TIMER_NOINT (IP19_CC | 0x1c)
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#define TIMER_CAUSECLR (IP19_CC | 0x1d)
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#define GROUP_IP (IP19_CC | 0x1e)
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#define GROUP_HPIL (IP19_CC | 0x1f)
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#define GROUP_CAUSE (IP19_CC | 0x20)
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#define GROUP_IPCLR (IP19_CC | 0x21)
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#define GROUP_HPILCLR (IP19_CC | 0x22)
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#define GROUP_CAUSECLR (IP19_CC | 0x23)
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#define GROUP_NOINT (IP19_CC | 0x24)
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#define GROUP_IP3NC (IP19_CC | 0x25)
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#define WG_CMDERR (IP19_CC | 0x26)
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#define WG_MIXERR (IP19_CC | 0x27)
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#define WG_DATAERR (IP19_CC | 0x28)
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#define MPRAND_ERR (IP19_CC | 0x1)
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/* IP19 R4K related message numbers */
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#define COMPARE_DERR (IP19_R4K | 0x1)
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#define COUNTER_BAD (IP19_R4K | 0x2)
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#define COUNTER_PINT (IP19_R4K | 0x3)
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#define COUNTER_NOINT (IP19_R4K | 0x4)
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