584 lines
19 KiB
C
584 lines
19 KiB
C
#ifndef __IDE_EVEREST_IP19_H__
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#define __IDE_EVEREST_IP19_H__
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/*
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* /include/ip19.h
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*
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* -- defines, addresses, and configs for IP19, IP21.
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*
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*
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* Copyright 1991,1992 Silicon Graphics, Inc.
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* All Rights Reserved.
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*
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* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
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* the contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of Silicon Graphics, Inc.
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*
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* RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
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* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
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* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
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* rights reserved under the Copyright Laws of the United States.
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*/
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#ident "$Revision: 1.15 $"
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#include <sys/sbd.h>
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#include <setjmp.h>
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#include <sys/EVEREST/everest.h>
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#ifndef _LANGUAGE_ASSEMBLY
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#include <libsk.h>
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#include <memstr.h>
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#include <parser.h>
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#include <fault.h>
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#endif /* !_LANGUAGE_ASSEMBLY */
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#define FPSR_COND 0x800000 /* condition bit in FPU status reg */
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#define FPSR_ENABLE 0xf80 /* enable bits in FPU status reg */
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#define BASE1 0x02000000 /* memory tests begin at 32 meg */
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/* must be a multiple of CHUNK_SIZE */
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/* PHYS_TO_MEM replaces PHYS_TO_K1 for IP19 in name only. This is done to allow
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the IP21 to use a different set of addresses for accessing the local
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registers and cache tag areas
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*/
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#define PHYS_TO_MEM(x) PHYS_TO_K1(x)
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#define getcpu_loc(loc) { \
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loc[0] = (EV_GET_LOCAL(EV_SPNUM) & EV_SLOTNUM_MASK) >> EV_SLOTNUM_SHFT; \
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loc[1] = (EV_GET_LOCAL(EV_SPNUM) & EV_PROCNUM_MASK); \
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}
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#define uc_bwrite(x,y) *(unsigned char *)PHYS_TO_MEM(x) = y
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#define uc_bread(x) *(unsigned char *)PHYS_TO_MEM(x)
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#define c_wwrite(x,y) *(unsigned int *)x = y
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#define c_wread(x) *(unsigned int *)x
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#define MAX_PRIM_LSIZE 32 /* IP17: 16 or 32 byte primary line length */
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#define MAX_2ND_LSIZE 128 /* IP17: 32, 64, or 128 byte 2nd level lines */
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/* SET_SHIFT was a constant in all previous machines: (Log base 2 of #bytes
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* in 2nd cache line, == 4). In IP17 this value varies from 4 to 7 (linesize
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* of 16 - 128 bytes). */
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#define FOUR_WD_2NDLINE 16
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#define EIGHT_WD_2NDLINE 32
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#define SIXTEEN_WD_2NDLINE 64
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#define THIRTYTWO_WD_2NDLINE 128
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/* mask clears to 32-byte boundaries */
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#define ALIGN_TO_32 (0xffffffe0)
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#define FILL_CHUNK_SIZE 32 /* pathasm.s:back* fns fill 32-byte chunks */
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#define MAX_PHYS_MEM 0x1fffffff /* 256 meg--max physical mem on IP17 */
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/* start generic filling at 4Meg--start of either 1M or 4M secondary cache */
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#define PHYS_FILL_LO BASE1 /* start generic filling at 4M */
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#define PHYS_CHECK_LO BASE1 /* mem checking begins at this addr */
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/* check_states() uses a bit field to determine what pieces of the
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* caches and memory to check, given the physical addr. */
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/* selects cache(s) for several path/ primitives to alter. Note that
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* since the icache tests are separated, the BOTH option refers to
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* the primary data and (combined) secondary. */
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#define PRIMARYD 0
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#define PRIMARYI 1
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#define SECONDARY 2
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#define BOTH 3
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#define DO_MEMORY 4
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#define TLBLO_19HWBITS 0x3fffffff /* 24 bit ppn, CDVG */
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#define TLBHI_TWIDBITS (TLBHI_VPNMASK|TLBHI_PIDMASK)
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#ifndef _LANGUAGE_ASSEMBLY
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/*
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* configuration struct -- config parms of IP17--some determined at startup
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*/
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struct config_info {
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/* all cache sizes in bytes */
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int icache_size; /* primary instruction cache size */
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int iline_size; /* primary instruction line size */
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int dcache_size; /* primary data cache size */
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int dline_size; /* primary data line size */
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int sidcache_size; /* second level instr-data cache size */
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int sidline_size; /* second level line size */
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int set_mask; /* mask of set */
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int tag_mask; /* mask of set */
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int key_shift; /* 18 for IP15, 16 for others */
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unsigned int stop:1, /* CTRL S and CTRL Q */
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ctrlc : 1, /* CTRL C */
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noctrlc : 1, /* NO CTRL C */
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:29;
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};
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extern struct config_info config_info;
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/*
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struct check_info {
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unsigned int check_list;
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unsigned int match_list;
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unsigned int phys_addr;
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unsigned int caller;
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unsigned int value;
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unsigned int pdline;
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unsigned int pdtag;
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unsigned int piline;
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unsigned int pitag;
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unsigned int sidline;
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unsigned int sidtag;
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unsigned int memory;
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} check_info_t;
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*/
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/*
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* addr_range structure for parse_addr()
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*/
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struct addr_range {
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int lo; /* beginning address */
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int hi; /* ending address */
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char size; /* byte, half word or word */
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};
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extern struct addr_range addr_range;
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/* In reading and writing the cache tags, some of the bits are
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* computed during the write (ECC or parity), and some of the bits
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* indicate illegal states (only 2 of the possible 4 Primary Data
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* cache states are valid for primary instruction caches even though
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* the taglo definition is shared). These bits will not read back
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* as they were written and must be exempted from any compares via masks.
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* - The lower 6 bits of the PTagLo register must not be tested for
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* primary DATA caches (5 bits undefined + 1 parity bit).
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* - The lower 8 bits of the PTagLo register must not be tested for
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* Primary INSTRUCTION caches (as P. Data above, plus the next two
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* (state) bits, due to the fewer legal states in the instruction cache).
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* - The lower 7 bits of STagLo for the ECC field.
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*/
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#define P_D_IGNMASK 0x0000003f
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#define P_I_IGNMASK 0x000000ff
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#define S_IGNMASK 0x0000007f
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/* The Unique_Tag_Addrs() tag test in path/cache_rams.c verfies that
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* all the tags can be uniquely address; in order to generate unique
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* yet easily-recognized addr patterns (given that the lower 7 or less
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* bits can't be written), the address is shifted up TAG_IGN_SHIFT
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* bits for all tags. */
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#define TAG_IGN_SHIFT 8
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#define PAT_FUNC(x,addr) ((5 * x) + addr + 1)
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/* define macro to compute maximum # of 2ndary cache-tags possible for IP17.
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* Some routines need it to size arrays (created dynamically) for tag-storage.
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* One tag per line; max-lines depends on scache-size */
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#define MAX_SCACHE_SIZE 0x400000 /* R4K max 2ndary cache size is 4mb */
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#define SCACHE_LSIZE 0x80 /* IP17 can't vary 2ndary linesize */
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#define MAX_S_TAGS (MAX_SCACHE_SIZE / SCACHE_LSIZE)
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/* some of the diagnostics continue on through errors, logging them up
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* to a certain point. NUM_ERRORS_ALLOWED is defines that point. */
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#define NUM_ERRORS_ALLOWED 3
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/* path/cache_states.c: runem uses a jump-table of functions returning ints
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* with 2 unsigned-integer parameters */
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typedef int (*PFI)(__psunsigned_t, uint);
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/* and others return uints and need one uint parameter */
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typedef uint (*PFUI)(uint);
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enum mem_space { k0seg, /* cached, unmapped access */
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k1seg, /* uncached, unmapped access */
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k2seg /* mapped; specified caching strategy */
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};
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/* indicates which cache state to set.
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* Some are specific to primary or secondary. Note that DIRTY_EXCL in
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* primary sets the writeback bit therefore acting like the secondary
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* does in that state. The DIRTY_EXCL_NWB state applies only to the
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* primary and is the special case where a line is read from a dirty
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* secondary but not modified in the primary. */
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enum c_states { INVALIDL, /* P or S: cache line is invalid */
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CLEAN_EXCL, /* P or S: clean exclusive */
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DIRTY_EXCL, /* P or S: dirty exclusive */
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DIRTY_EXCL_NWB /* P: Dirty Excl. w/ writeback bit clear */
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};
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/* path/mem_init() either sets memory to the value specified by the 'pattern'
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* parm (M_I_PATTERN mode below), an ascending value incremented by 4 per
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* word, with starting value specified by 'pattern' parm (M_I_ASCENDING mode),
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* the ascending one's complement of 'pattern' (M_I_ASCENDING_INV), or an
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* alternating-one's complement of the specified pattern (M_I_ALT_PATTERN).
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*/
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enum fill_mode { M_I_PATTERN,M_I_ASCENDING,M_I_ASCENDING_INV,M_I_ALT_PATTERN };
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/* sbd.h contains the masks for accessing the primary and secondary
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* fields in the TagLo register. The below #defines manipulate
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* those values into positions in the tag_info struct and then mask
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* the valid parts of those fields for use by get_tag_info.
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*
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* The tag_info struct holds the state (in the low 2 or 3 bits depending
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* upon which cache is being queried), the 3 Vindex bits shifted to
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* their proper position for use (if the tag is from secondary cache),
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* and the upper bits of the physaddr, also shifted to their useable
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* positions. If the tag is from a primary line the tag reported bits
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* 35..12, so physaddr contains bits 31..12 of the physical address.
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* If it is a secondary line, the tag contained bits 35..17, so physaddr
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* will contain bits 31..17.
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*/
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typedef struct tag_info {
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ushort state;
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ushort vindex;
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uint physaddr;
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} tag_info_t;
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/* get_tag rolls phys addrs from the taglo register to their correct
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* 31-bit positions before placing them in the tag_info.physaddr
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* field for easy comparision. The below masks return the valid portion
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* of the address (depending upon which cache the tag is from).
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*/
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#define PINFOADDRMASK 0xFFFFF000
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#define SINFOADDRMASK 0xFFFE0000
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/* top bit if phys addrs in taglo is 35: we want it to be 31 so roll left 4 */
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#define TAGADDRLROLL 4
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/* roll the 3 vindex (2ndary cache) bits from their taglo spot (9..7)
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* to their real positions (14..12) for easy comparision by get_tag_info */
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#define SVINDEXLROLL 5
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#define INFOVINDMASK 0x7000
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/* define bit-rolls to get cache-state portion to bottom of tag_lo word. */
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#define PSTATE_RROLL 6 /* tag_lo bits 7..6 indicate pcache state */
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#define SSTATE_RROLL 10 /* tag_lo bits 12..10 indicate scache state */
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/* DONT_DOIT is used by a variety of routines to indicate that a particular
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* parameter is a dummy for that particular call, and to NOT do the operation
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* for that parameter. */
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#define UINTMINUSONE (0xFFFFFFFF)
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#define DONT_DOIT UINTMINUSONE
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#define DONT_CHECK DONT_DOIT
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#define DONT_PRINTIT DONT_DOIT
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/* several primitives return MISSED_2NDARY when a cache instruction on
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* an address doesn't hit the secondary cache */
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#define MISSED_2NDARY (-2)
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/* mem/memsubs.c uses 32 of these chunks to determine how much phys mem
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* the system has. 8*1024*1024*32 == 2**28 == 256meg == max. phys mem.
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*/
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#define CHUNK_SIZE 4*1024*1024
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/* Most of the IP17stress diagnostic routines are coded to run icached or
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* not icached. The following enum tells the routines which mode to use.
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*/
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enum run_mode { ICACHED, IUNCACHED };
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/* memory-sizes are given in hex. Here are a few handy mnemonic defines
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* for loop values, etc.
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*/
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#define _4_K 0x001000
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#define _8_K 0x002000
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#define _16_K 0x004000
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#define _32_K 0x008000
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#define _64_K 0x010000
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#define _128_K 0x020000
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#define _1_MEG 0x100000
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#define _2_MEG 0x200000
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#define _3_MEG 0x300000
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#define _4_MEG 0x400000
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#define _5_MEG 0x500000
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#define _6_MEG 0x600000
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#define _7_MEG 0x700000
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#define _8_MEG 0x800000
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#define _9_MEG 0x900000
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#define _10_MEG 0x1000000
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/* Decimal iteration-counts for diag loops. Base 10 is more
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* intuitive for most humans than hex
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*/
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#define TEN_THOU 10000
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#define HUNDRED_THOU 100000
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#define ONE_MIL 1000000
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#define FIVE_MIL 5000000
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#define TEN_MIL 10000000
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#define HUNDRED_MIL 100000000
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#define SEC_VADDR_MASK (_128_K-1)
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#define PRIM_VADDR_MASK (_4_K-1)
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/* many of the cache-test routines change a value in a cache to ensure
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* that it does or does not flush out. GENERIC_INC is commonly used as
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* that increment-value. */
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#define GENERIC_INC 3
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typedef struct tlbptepairs {
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uint evenpg;
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uint oddpg;
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} tlbptepairs_t;
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#define RETCSERROR (!CSError ? 0 : 1)
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/* we want to ensure that the space we copy code into (for uncached
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* access) never maps to a cached-data access. Therefore we sandwich
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* the actual array between two 2nd-cache-sized lines. (The second-
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* cache-linesize constant is currently correct but could change.)
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*/
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#define SEC_CACHE_LSIZE 0x80
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#define CACHED_CODE_SIZE 0x1000
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#define EXTRA_SPACE (2*(SEC_CACHE_LSIZE/sizeof(uint)))
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/* 2ndary cache tags consist of 25 data bits monitored by 7 checkbits.
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* The internal format of the tags is different than when fetched into
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* the taglo register. These overly-complicated defines and macros
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* allow the taglo format to be converted into the internal one, which
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* anyone trying to diagnose hardware problems needs. */
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#define STAG_DBIT_SIZE 25
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#define STAG_CBIT_SIZE 7
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#define STAG_SIZE (STAG_DBIT_SIZE+STAG_CBIT_SIZE)
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/* S_taglo field format:
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* bitpositions--> 31..13 12..10 9..7 6..0
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* fields --> < p_addr, cstate, vind, ecc >.
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* Internal format:
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* 31..25 24..22 21..19 18..0
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* < ecc, cstate, vind, p_addr >.
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* the following defines tell ecc_swap_s_tag() how to shift the fields to
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* create the internal format from the s_taglo format.
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*/
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/* sizes of the fields */
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#define S_TAG_PADDR_BITS 19
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#define S_TAG_CS_BITS 3
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#define S_TAG_VIND_BITS 3
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#define S_TAG_ECC_CBITS 7
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/* bit positions of the fields in the s_taglo format */
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#define S_TAG_ECC_BITPOS 0
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#define S_TAG_VIND_BITPOS (S_TAG_ECC_BITPOS+S_TAG_ECC_CBITS) /* 7 */
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#define S_TAG_CS_BITPOS (S_TAG_VIND_BITPOS+S_TAG_VIND_BITS) /* 10 */
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#define S_TAG_PADDR_BITPOS (S_TAG_CS_BITPOS+S_TAG_CS_BITS) /* 13 */
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/* bit positions of the fields in the internal format */
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#define S_INT_PADDR_BITPOS 0
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#define S_INT_VIND_BITPOS (S_INT_PADDR_BITPOS+S_TAG_PADDR_BITS) /* 19 */
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#define S_INT_CS_BITPOS (S_INT_VIND_BITPOS+S_TAG_VIND_BITS) /* 22 */
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#define S_INT_ECC_BITPOS (S_INT_CS_BITPOS+S_TAG_CS_BITS) /* 25 */
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/* masks for the four fields in the 2ndary-cache-internal format:
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* < ecc, cstate, vindex, p_addr > */
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#define S_INT_PADDR_MASK 0x0007ffff
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#define S_INT_VIND_MASK 0x00380000
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#define S_INT_CS_MASK 0x01c00000
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#define S_INT_ECC_MASK 0xfe000000
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/* Below macros enable easy swapping of each of the 4 2ndary tag fields.
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* Note that the mask used by the conversion macros in extracting the
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* bits of the field depends on the direction of the swap */
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/* paddr: tag bit 13 <--> internal bit 0 */
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#define SADDR_SWAP_ROLL (S_TAG_PADDR_BITPOS-S_INT_PADDR_BITPOS)/* 13 */
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/* the saddr conversion rolls opposite from the other 3 fields: TagTOInternal
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* rolls addr DOWN to bottom */
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#define SADDR_TTOI(S_TAG) ((S_TAG & SADDRMASK) >> SADDR_SWAP_ROLL)
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#define SADDR_ITOT(S_TAG) ((S_TAG & S_INT_PADDR_MASK) << SADDR_SWAP_ROLL)
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/* cache state: tag bit 10 <--> internal bit 22 */
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#define SSTATE_SWAP_ROLL (S_INT_CS_BITPOS-S_TAG_CS_BITPOS) /* 12 */
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#define SSTATE_TTOI(S_TAG) ((S_TAG & SSTATEMASK) << SSTATE_SWAP_ROLL)
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#define SSTATE_ITOT(S_TAG) ((S_TAG & S_INT_CS_MASK) >> SSTATE_SWAP_ROLL)
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/* vindex: tag bit 7 <--> internal bit 19 */
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#define SVIND_SWAP_ROLL (S_INT_VIND_BITPOS-S_TAG_VIND_BITPOS) /* 12 */
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#define SVIND_TTOI(S_TAG) ((S_TAG & SVINDEXMASK) << SVIND_SWAP_ROLL)
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#define SVIND_ITOT(S_TAG) ((S_TAG & S_INT_VIND_MASK) >> SVIND_SWAP_ROLL)
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/* ecc: tag bit 0 <--> internal bit 25 */
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#define SECC_SWAP_ROLL (S_INT_ECC_BITPOS-S_TAG_ECC_BITPOS) /* 25 */
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#define SECC_TTOI(S_TAG) ((S_TAG & SECC_MASK) << SECC_SWAP_ROLL)
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#define SECC_ITOT(S_TAG) ((S_TAG & S_INT_ECC_MASK) >> SECC_SWAP_ROLL)
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/* provide macro to convert cached_code array to bytes for easy length comps */
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#define CC_BYTES ((CACHED_CODE_SIZE+EXTRA_SPACE)*sizeof(uint))
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extern uint cached_code[];
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extern tlbptepairs_t wpte[];
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extern unsigned char *k0a, *k1a, *pa;
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extern int CSError;
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/* begin prototype declarations, primarily for the primitives used
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* by the IP17 diagnostics. */
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/* from path/cache_states.c */
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extern runem(int);
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/* from path/IP17stress.c */
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extern uint ReadStress(enum run_mode, uint, uint);
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extern uint WriteStress(enum run_mode, uint, uint);
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extern uint WritebackStress(enum run_mode, uint, uint);
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/* from prims/bussubs.c */
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extern int clear_sema(void);
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extern int clear_pend(uint);
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/* from prims/cpusubs.c */
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/* extern walking_1(struct memstr *, int, uint, enum bitsense);
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extern bwaking_1(struct memstr *, int, uint, enum bitsense);
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extern walking_addr(struct memstr *, int);
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extern bwalking_addr(struct memstr *, int);
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extern addr_pattern(struct memstr *, int, enum bitsense);
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extern read_wr(struct memstr *, uint);
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extern bread_wr(struct memstr *, uint);
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*/
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extern void pte_setup(void);
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extern void flushall_tlb(void);
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extern scinv(void);
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/* from prims/genasm.s */
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extern uint pd_iwbinv(uint);
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extern uint sd_iwbinv(uint);
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extern uint pd_CDE(uint);
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extern uint sd_CDE(uint);
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extern uint pd_HINV(uint);
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extern uint sd_HINV(uint);
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extern uint pd_HWBINV(uint);
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extern uint pd_HWB(uint);
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extern uint sd_HSV(uint);
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extern int ICached(void);
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extern int ml_run_it(uint, uint, uint, uint);
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extern int ml_fast_reads();
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extern int ml_fr_end();
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extern int ml_fast_w_hwbinvs();
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extern int ml_fwh_end();
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extern int ml_fast_dirty_wbs();
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extern int ml_fdw_end();
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/* from prims/gensubs.c */
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extern int getcpuid(void);
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extern int cpuboard(void);
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extern uint calc_tag_cbits(uint);
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extern uint st_to_i(uint);
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extern int set_shift(void);
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extern unsigned char *buf_alloc(int, int);
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extern void buf_free(unsigned char *);
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/* from prims/handler.s */
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|
extern int handler_setup(void);
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/* from prims/memsubs.c */
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|
extern int size_mem(void);
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|
extern int EnableBusIntr(void);
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|
extern int DisableBusIntr(void);
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/* from prims/pathasm.s */
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|
extern back1(unsigned int, unsigned int);
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|
extern back2(unsigned int, unsigned int);
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/* extern read_tag(unsigned int, unsigned int, struct tag_regs *); */
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|
/* extern write_tag(unsigned int, unsigned int, struct tag_regs *); */
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|
extern int fill_ipline(uint *);
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|
extern int write_ipline(uint *);
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|
|
|
/* from prims/pathsubs.c */
|
|
extern fill_caches(unsigned int);
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|
extern fill_line(unsigned int, unsigned int);
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|
|
|
/* extern unsigned int mem_init(uint, uint, enum fill_mode, uint); */
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|
|
|
extern numtlbslots(void);
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|
extern store_n_fetch_tags(void);
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|
extern ch_bit_tests(void);
|
|
extern ce_test(void);
|
|
extern de_test(void);
|
|
extern ce_to_de_test(void);
|
|
|
|
extern test_c_instrs(int);
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|
|
|
|
|
/* from prims/tlb.s */
|
|
extern int ta_spl(void);
|
|
extern int dinvaltlb(int);
|
|
extern int clr_tlb_regs(void);
|
|
extern int settlbslot(int, uint, __psunsigned_t, uint, uint);
|
|
extern int dset_tlbpid(int);
|
|
extern int write_indexed_lo(int, tlbptepairs_t *);
|
|
extern int write_indexed_hi(int, uint);
|
|
extern uint read_indexed_hi(int);
|
|
extern uint read_indexed_lo(int, tlbptepairs_t *);
|
|
extern int matchtlb(int, uint);
|
|
extern int tlb_setup(uint, uint, uint, uint);
|
|
|
|
|
|
/* from prims/iosubs.c */
|
|
extern void close_on_exception(int);
|
|
extern void exception_close(void);
|
|
extern int write_test(char *, char *, uint, uint, uint);
|
|
extern int read_test(char *, char *, uint, uint, uint, uint);
|
|
extern int add_map(int, int);
|
|
extern int dump_map(int);
|
|
extern int dir_write(char *, char *, uint);
|
|
extern int setlev(char *);
|
|
extern int test_map(int);
|
|
extern int cleariomask(void);
|
|
extern int checkbuserr(void);
|
|
extern int clearbuserr(void);
|
|
extern int ecc_loop(void);
|
|
/* extern int force_ecc(int, int, char); */
|
|
extern int force_ecc_ip9(volatile int, volatile int, char);
|
|
extern int check_log(uint, uint, uint);
|
|
extern int lookup(uint, uint);
|
|
extern int logprint(uint);
|
|
extern int clearecc(uint, uint);
|
|
extern int vme_reset(void);
|
|
extern int clear_log(void);
|
|
extern int idbg_ecc(void);
|
|
extern struct iob * get_iob(int);
|
|
|
|
/* from saio/lib/cache.s */
|
|
extern uint get_dcachesize(void);
|
|
extern uint get_icachesize(void);
|
|
extern uint get_scachesize(void);
|
|
extern uint get_dcacheline(void);
|
|
extern uint get_icacheline(void);
|
|
extern uint get_scacheline(void);
|
|
|
|
|
|
|
|
extern int config_cache(void);
|
|
extern void flush_cache(void);
|
|
extern int invalidate_icache(uint, uint);
|
|
|
|
extern int _icache_size;
|
|
extern int _dcache_size;
|
|
extern int _sidcache_size;
|
|
|
|
extern int setup_icache(__psunsigned_t, __psunsigned_t);
|
|
|
|
|
|
#endif /* !_LANGUAGE_ASSEMBLY */
|
|
|
|
#endif /* __IDE_EVEREST_IP19_H__ */
|