168 lines
4.6 KiB
C
168 lines
4.6 KiB
C
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/*
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* mc2/bread_write.c
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*
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*
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* Copyright 1991, 1992 Silicon Graphics, Inc.
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* All Rights Reserved.
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*
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* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
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* the contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of Silicon Graphics, Inc.
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*
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* RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
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* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
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* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
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* rights reserved under the Copyright Laws of the United States.
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*/
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#ident "$Revision: 1.11 $"
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/*
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* bread_write -
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*
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* NOTICE: Reserved 1M memory for diagnostics.
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*/
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#include <sys/types.h>
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#include <sys/cpu.h>
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#include <sys/sbd.h>
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#ifdef IP19
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#include "ip19.h"
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#elif IP21
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#include "ip21.h"
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#elif IP25
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#include "ip25.h"
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#endif
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#include "pattern.h"
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#include "memstr.h"
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#include "mc3_reg.h"
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#include "exp_parser.h"
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#include <ide_msg.h>
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#include <everr_hints.h>
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#include <setjmp.h>
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#include <sys/EVEREST/evconfig.h>
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#include "fault.h"
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#include "uif.h"
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#include "prototypes.h"
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extern jmp_buf mem_buf;
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extern uint mem_slots;
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extern void TimerHandler();
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extern int bread_wr(struct memstr *, unsigned int, unsigned long long);
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bread_write()
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{
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register int fail = 0;
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struct memstr addr;
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register int inc = 1;
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register uint mem_slots;
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unsigned long long i, himem, memsize, paddr;
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register int first_time = 1;
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int val;
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msg_printf(SUM,"Byte Read-Write data test\n");
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if (quick_mode()) {
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msg_printf(SUM, "\nRunning in quick mode...\n");
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/*
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msg_printf(SUM, "\nQuick mode takes approximately 40 seconds");
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msg_printf(SUM, " for every 1GB of memory\n");
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*/
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inc = QUICK_INC_BRW;
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}
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else {
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/*
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msg_printf(SUM, "\nWARNING: This test takes approximately 15 minutes ");
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msg_printf(SUM, "for every 32MB of memory\n");
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*/
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}
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/*
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* from saio/lib/cache.s
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* invalidates all caches. Added because of the R4000 uncached writeback
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* bug - makes *sure* that there are no valid cache lines
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*/
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invalidate_caches();
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for (i = 0; i < EV_MAX_SLOTS; i++)
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if (board_type(i) == EVTYPE_MC3)
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setup_err_intr(i, 0); /* 0 is a no op for mc3 */
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mem_slots = mc3slots();
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mem_err_clear(mem_slots); /* clear error regs */
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if (val = setjmp(mem_buf)) {
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if (val == 1){
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msg_printf(ERR, "Unexpected exception during memory test\n");
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show_fault();
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}
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mem_err_log();
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mem_err_show();
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/* everest_error_show();*/
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fail = 1;
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goto SLOTFAILED;
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}
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else {
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set_nofault(mem_buf);
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memsize = readconfig_reg(RDCONFIG_MEMSIZE,0);
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first_time = 1;
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for (i = 0; i < memsize; i += DIRECT_MAP) {
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if (i < PHYS_CHECK_LO)
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paddr = PHYS_CHECK_LO;
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else
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paddr = i;
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addr.lomem =
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(uint *) map_addr(paddr, DIRECT_MAP, UNCACHED);
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if (memsize < (i + DIRECT_MAP)) {
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himem = ((__psunsigned_t) addr.lomem + (memsize - paddr));
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addr.himem = (uint *) himem;
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msg_printf(DBG,"memsize-paddr is 0x%llx, himem is 0x%x\n",
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memsize-paddr, (uint) himem);
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}
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else {
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himem = ((__psunsigned_t) addr.lomem +
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(DIRECT_MAP-(first_time*PHYS_CHECK_LO)));
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addr.himem = (uint *) himem;
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first_time = 0;
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}
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msg_printf(DBG, "lo:%x, hi:%x, p: %llx, inc: %d\n",
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addr.lomem, addr.himem, paddr, inc);
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/*
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* Write and read 0's and 1's
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*/
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addr.mask = 0xff;
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#ifdef IP19
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/* Enable the bouncing cursor via R4k Interrupts */
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/* every four seconds */
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InstallHandler( INT_Level5, TimerHandler);
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EnableTimer(4);
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#endif
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fail |= bread_wr(&addr, inc, paddr);
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} /* for i < memsize */
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} /* else ... setjmp */
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SLOTFAILED:
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#ifdef IP19
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/* Put back the orginal vector */
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RemoveHandler( INT_Level5);
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StopTimer();
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#endif
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/* Post processing */
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if (chk_memereg(mem_slots)){
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msg_printf(ERR, "Byte Read-Write data test detected non-zero MC3 error register contents\n");
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check_memereg(mem_slots);
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mem_err_clear(mem_slots);
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fail = 1;
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}
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clear_nofault();
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return (fail);
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}
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