186 lines
4.2 KiB
ArmAsm
186 lines
4.2 KiB
ArmAsm
/* dcache1
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*
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* This diag tests to make sure that the valid ram in the TFP IU dcache
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* is working correctly. First the valid ram are tested directly by
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* performing dctw and dctr instructions. Then they are tested again
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* by loading from one region of memory cached, and then a different
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* region uncached. At the end, all the tags in the dcache should be
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* invalid.
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*
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* Ported from MTI dcache1.p dk test. Tests the IU on-chip DCache.
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*
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* Vswami knows about this -- it came from /hosts/thrill.mti/x/lab/dcache1
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*/
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#ident "$Revision: 1.4 $"
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#include <sys/cpu.h>
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#include <sys/sbd.h>
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#include <sys/regdef.h>
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#include <asm.h>
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/* Write data cache tag.
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*/
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#define dcache_write(addr,value) \
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dmtc0 addr,C0_BADVADDR; \
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ssnop; \
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ssnop; \
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ssnop; \
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dmtc0 value,C0_DCACHE; \
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ssnop; \
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ssnop; \
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ssnop; \
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dctw; \
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ssnop; \
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ssnop; \
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ssnop
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/* Read data cache tag.
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*/
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#define dcache_read(addr,dst) \
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dmtc0 addr,C0_BADVADDR; \
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ssnop; \
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ssnop; \
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ssnop; \
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dctr; \
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ssnop; \
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ssnop; \
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ssnop; \
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dmfc0 dst,C0_DCACHE; \
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ssnop; \
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ssnop; \
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ssnop
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/* CPU speed dependent speed delay.
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*/
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#define delay(sec) \
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.align 4; \
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li v1,sec*20000000; \
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22: daddi v1,-1; \
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bgtz v1,22b; \
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nada
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/* test_dcache_tags -- test writing/reading dcache tags.
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*/
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#define DCACHE_SIZE 0x4000
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LEAF(test_dcache_tags)
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.align 7 # cache line aligned
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.set noreorder
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li t0,0x4000 # dcache size
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move v0,zero # error count
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move t1,zero # primed == false
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3:
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/* Write then read pattern DCACHE_VMASK (valid bits)
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*/
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dli a1,DCACHE_VMASK # first pattern
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move a0,zero # initial address
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1: dcache_write(a0,a1) # write tag
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daddiu a0,8 # bump one primary cache line
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blt a0,t0,1b # loop through full cache
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nop # BDSLOT
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beqz t1,1f # do not delay on prime
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nada # BDSLOT
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delay(4)
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1: move a0,zero # initial address
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1: dcache_read(a0,a2) # read tag
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beq a1,a2,2f # miscompare?
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nop # BDSLOT
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bnez t2,2f # do not fail on prime
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nop # BDSLOT
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daddiu v0,1 # bump error count
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2: daddiu a0,16 # bump one primary cache line
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blt a0,t0,1b
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nop
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/* Write then read pattern 0.
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*/
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move a1,zero # second pattern
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move a0,zero # inital address
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1: dcache_write(a0,a1); # write tag
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daddiu a0,16 # bump one primary cache line
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blt a0,t0,1b # loop through full cache
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nop # BDSLOT
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beqz t1,1f # do not delay on prime
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nada # BDSLOT
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delay(4)
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1: move a0,zero # initial address
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1: dcache_read(a0,a2) # read tag
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beq a1,a2,2f # miscompare?
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nop # BDSLOT
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bnez t2,2f # do not fail on prime
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nop # BDSLOT
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daddiu v0,0x1000 # bump error count
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2: daddiu a0,16 # bump one primary cache line
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blt a0,t0,1b # loop through full cache
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nop
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beqz t1,3b # loop again after prime
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addi t1,1 # BDSLOT: primed == true
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j ra # return
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nada
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.set reorder
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END(test_dcache_tags)
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#define TEST_ADDRESS 0x08c00000
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LEAF(test_dcache_ram)
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.set noreorder
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move v0,zero # init error count
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/* clear_uncached_region
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*/
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dli a0,PHYS_TO_K1(TEST_ADDRESS) # address
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daddiu a1,a0,DCACHE_SIZE # ending address
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1: sw zero,0(a0) # zero word
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daddiu a0,4 # next word
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bltu a0,a1,1b # loop
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nop # BDSLOT
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/* store_cached_data
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*/
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dli a0,PHYS_TO_K0(TEST_ADDRESS-DCACHE_SIZE) # address
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daddiu a1,a0,DCACHE_SIZE # ending address
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li a2,0xffffffff # test data
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1: sw a2,0(a0) # store word
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daddiu a0,4 # next word
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bltu a0,a1,1b # loop
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nop # BDSLOT
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delay(4)
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/* load_uncached_data
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*/
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dli a0,PHYS_TO_K1(TEST_ADDRESS) # address
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daddiu a1,a0,DCACHE_SIZE # ending address
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1: lw a3,0(a0) # load word
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beq a3,zero,2f # mismatch?
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nop # bdslot
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daddiu v0,0x1000 # incr error count
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2: daddiu a0,4 # next word
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bltu a0,a1,1b # loop
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nop # BDSLOT
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delay(4)
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/* load_cached_data
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*/
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dli a0,PHYS_TO_K0(TEST_ADDRESS-DCACHE_SIZE) # address
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daddiu a1,a0,DCACHE_SIZE # ending address
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dli a2,0xffffffffffffffff # test data
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1: lw a3,0(a0) # load word
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beq a3,a2,2f # mismatch?
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nop # BDSLOT
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daddiu v0,1 # incr error count
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2: daddu a0,4 # next word
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bltu a0,a1,1b # bdslot
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nop # BDSLOT
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j ra
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nop
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.set reorder
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END(test_dcache_ram)
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