251 lines
6.0 KiB
ArmAsm
251 lines
6.0 KiB
ArmAsm
#include <sys/cpu.h>
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#include <sys/sbd.h>
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#include <sys/regdef.h>
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#include <asm.h>
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#include <sys/IP26.h>
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#include <sys/IP22.h>
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#define GCACHE_SIZE_ADDR IP26_GCACHE_SIZE_ADDR
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/* End of stuff I added */
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/* get_dcachesize */
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#define MIN_CACH_POW2 12
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#define Ra_save0 s0 /* level 0 ra save registers */
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#define Ra_save1 s1 /* level 1 ra save registers */
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#define Ra_save2 s2 /* level 2 ra save registers */
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/*#define DC_INIT_ADDRESS 0xa8800000
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#define PTAG_E_ADDR TCC_ETAG_DA
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#define PTAG_E_ST TCC_ETAG_ST
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#define STARTUP_CTRL 0x00
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#define PTAG_ST_INIT 0x00
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#define SET_ALLOW GCACHE_SETALLOW
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*/
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#define SCACHE_TESTADDR 0xa800000008840000
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/* For dcache_tag */
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/* #define DC_TAG_ADDRESS 0x900000001fcfc000 */
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#define DC_TAG_ADDR_START 0x900000001cc00000
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#define DC_TAG_ADDR_END 0x900000001cc3ffff
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#define VALID_EX_BIT_MASK 0x780000000000800
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#define MAX_TAG_PATTERN 4
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/* These are EV DIAG error codes for v0 */
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#define DCACHE_TAG 11
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#define SCACHE_TAG 12
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/*--------------------------------------------------------------------------*/
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/* Initialize DCache by invalidating it. DCache is 16KB, with 32Byte line,
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* 28 bits Tag + 1 bit Exclusive + 8 bits Valid + 32 Bytes Data
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* Need two consecutive writes to half-line boundaries to clear Valid bits
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* for each line.
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*/
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LEAF(dcache_only_inval)
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.set noreorder
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move t3, ra
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li v1, 16 # size of the half of Dcache line
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jal get_dcachesize
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nop
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# v1: half line size, v0: cache size to be initialized
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dli t1,SCACHE_TESTADDR # Starting address for initializing
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# Dcache
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daddu t2, t1, v0 # t2: loop terminator
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# for each cache line:
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# mark it invalid
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1:
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DMTC0(t1,C0_BADVADDR)
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DMTC0(zero,C0_DCACHE) # clear all (4) Valid bits
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dctw # write to the Dcache Tag
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ssnop; ssnop; ssnop # pipeline hazard prevention
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.set reorder
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daddu t1, v1 # increment to next half-line
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bltu t1, t2, 1b # t2 is termination count
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j t3
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END(dcache_only_inval)
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LEAF(dump_dcache_tag)
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.set noreorder
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move a4, ra
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li a7, 16
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jal get_dcachesize
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nop
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/* li v0,256
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nop
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*/
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dli a5, SCACHE_TESTADDR
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nop
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daddu a6, a5, v0 #a6 is loop bound
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1:
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DMTC0(t1,C0_BADVADDR)
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dctr
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ssnop;ssnop
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DMFC0(t0, C0_DCACHE)
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move a0,t0
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jal pon_puthex
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nop
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dla a0,crlf
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nop
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jal pon_puts
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nop
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daddu a5, a7 # increment to next half-line
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# increment by 16
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bltu a5,a6, 1b
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nop
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move a0,a5
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jal pon_puthex
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nop
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dla a0, dump_dcache_tag_end
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nop
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jal pon_puts
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nop
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j a4
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nop
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END(dump_dcache_tag)
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.data
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dump_dcache_tag_end:
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.asciiz "\nDcache tag dump end \r\n"
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.text
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/*
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* return the size of the primary data cache
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*/
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LEAF(get_dcachesize)
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.set noreorder
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DMFC0(t0,C0_CONFIG)
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.set reorder
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and t0,CONFIG_DC
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srl t0,CONFIG_DC_SHFT
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addi t0,MIN_CACH_POW2
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li v0,1
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sll v0,t0
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j ra
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END(get_dcachesize)
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/*-----------------------------------------------------------------------------------*/
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LEAF(dcache_tag)
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.set noreorder
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move Ra_save1, ra
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/*
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li v1, 16 # size of the half of Dcache line
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# each cache tagram entry contains
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# 4 64 bit data
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jal get_dcachesize # 16k bytes
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nop
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*/
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# for each cache line in cache tag ram fill up the tag
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# with various tag patterns and do cache tag write
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# do this for whole 16kB Dcache tag
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.set noreorder
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1:
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dli t1, DC_TAG_ADDR_START
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dli t2, DC_TAG_ADDR_END
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2:
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DMTC0(t1,C0_BADVADDR)
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dli s5, 0x7777777777777777
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dli s4, 0xfffffff000
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and s5, s4
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dli s4, VALID_EX_BIT_MASK
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or s5, s4
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DMTC0(s5, C0_DCACHE)
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dctw # Dcache Tag Write
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ssnop; ssnop; ssnop # pipeline hazard prevention
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daddu t1, 0x10 # increment to next half-line
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# increment by 16
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bltu t1, t2, 2b # t2 is termination count
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ssnop
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nop
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# for each cache line in cache tag ram do cache tag
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# read and compare the result, do this for whole
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# 16KB cache tag
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dli t1,DC_TAG_ADDR_START # Starting address DC tag ram
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dli t2, DC_TAG_ADDR_END
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3:
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DMTC0(t1,C0_BADVADDR)
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dctr # Dcache Tag Read
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ssnop;ssnop
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DMFC0(t3, C0_DCACHE) # Read from Dcache register
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bne t3, s5, 99f
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ssnop
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daddu t1, 0x10 # increment to next half-line
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# increment by 16
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bltu t1, t2, 3b # t2 is termination count
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ssnop
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nop
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.set reorder
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# done with no error
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dla a0, dcache_tag_pass # dcache tagram pass msg
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jal pon_puts
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move v0, zero # zero retn -> no error
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j Ra_save1 # Jump to saved ra
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99:
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.set noreorder
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dla a0, dcache_tag_fail # dcache tagram fail msg
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jal pon_puts
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nop
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move a0,t1
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jal pon_puthex64 # output dcache tag entry
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nop
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dla a0, crlf
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jal pon_puts
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nop
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.set reorder
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li v0, DCACHE_TAG
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j Ra_save1 # Jump to saved ra
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END(dcache_tag)
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.data
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dcache_tag_pass:
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.asciiz "DCache tag test passed\r\n"
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dcache_tag_fail:
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.asciiz "DCache tag test failed at entry "
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tag_pattern:
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.word 0xaaaaaaaa, 0x55555555, 0, 0xffffffff
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.text
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