390 lines
9.3 KiB
C
390 lines
9.3 KiB
C
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/*
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* ide/IP30/cache/scache_ecc.c Secondary Cache ECC RAM/Interrupt Test
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*
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*
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* Copyright 1991, Silicon Graphics, Inc.
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* All Rights Reserved.
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*
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* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
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* the contents of this file may not be disclosed to third parties, copied or
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* duplicated in any form, in whole or in part, without the prior written
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* permission of Silicon Graphics, Inc.
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*
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* RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
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* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
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* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
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* rights reserved under the Copyright Laws of the United States.
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*/
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#ident "ide/IP30/cache/scache_ecc.c: $Revision: 1.17 $"
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#include <sys/param.h>
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#include <sys/sbd.h>
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#include <sys/cpu.h>
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#include <fault.h>
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#include <setjmp.h>
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#include <uif.h>
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#include <libsc.h>
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#include <libsk.h>
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#include <pon.h> /* for run_cached & run_uncached */
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#include "cache.h"
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/*
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* number of data patterns to fed through
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*/
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#define NUM_DATA_PATS 4
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#define NUM_XOR_PATS 4
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static uint data_pats[] = { 0, 0x55555555, 0xbbbbbbbb, 0xffffffff };
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static uint ecc_xor_pats[] = {0x55, 0xaa, 0xff, 0 };
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int scache_ecc_intr(void);
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int scache_ecc_ram(void);
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void setstackseg(__psunsigned_t);
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/*
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* scache_ecc - secondary cache ecc test called function. set up this
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* way to allow for more subtests later if needed
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*
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* NOTE - both of these tests are based on the assumption that on cache
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* data loads or instruction fills, the R4000 ECC register contents are
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* only forced into the PRIMARY cache parity fields. If errors crop up
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* here, I will have to rewrite parts of these diagnostics
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*/
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u_int
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scache_ecc(void)
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{
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extern int _sidcache_size;
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int error = 0;
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/* Check for a secondary cache, skip if a PC version */
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if(! _sidcache_size) {
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msg_printf(VRB|PRCPU,
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"*** No Secondary Cache detected, test skipped\n");
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return(0);
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}
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msg_printf(VRB|PRCPU, "Secondary Cache ECC RAM/Interrupt Test\n");
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/* flush stack to uncached space */
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flush_cache();
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/* make sp uncached too */
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setstackseg(K1BASE);
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run_uncached();
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invalidate_caches();
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error = scache_ecc_ram() || scache_ecc_intr();
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invalidate_caches();
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setstackseg(K0BASE);
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run_cached();
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flush_cache();
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if (error)
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sum_error("secondary cache");
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else
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okydoky();
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return error;
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}
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/*
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* scache_ecc_ram - secondary cache ecc ram test
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*
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* all memory locations in the cache are set to 0, so normal ECC for all
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* dwords will be 0. Different data patterns are XOR'd into the calculated
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* ECC and verified for all dwords in the scache.
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*/
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int
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scache_ecc_ram(void)
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{
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register uint *fillptr, r_pattern, w_pattern, readin;
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uint fail, i, j, is_rev1, clear_pat;
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struct tag_regs tags;
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volatile uint dummy, dummy2;
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k_machreg_t cur_stat;
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#if R10000
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int way,way_size;
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#endif
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fail = 0;
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/*
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* save current status register contents for restoration later
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*/
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cur_stat = GetSR();
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/*
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* start with caches known invalid so that uncached writes go to memory
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*/
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invalidate_caches();
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is_rev1 = 0;
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clear_pat = 0;
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/*
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* disable ECC exceptions
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*/
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SetSR(cur_stat | SR_DE);
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msg_printf(DBG|PRCPU, "Initializing Memory\n");
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/*
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* fill an area of phys ram the size of the scache with all 0's
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*/
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j = (uint) (SID_SIZE / sizeof(uint));
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fillptr = (uint *)PHYS_TO_K1(PHYS_CHECK_LO);
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while (j--)
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*fillptr++ = 0;
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#if R10000
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tags.tag_lo = 0x0;
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tags.tag_hi = 0x0;
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#endif
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/*
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* for each chosen set of XOR patterns, read in and verify current ECC
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* contents and write next pattern. since we do read and write in the
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* same pass, the patterns are jimmied so that the last XOR write will
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* restore original ECC value (0)
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*/
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for (j = 0; j < NUM_XOR_PATS; j++)
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{
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/*
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* get current readback and write data patterns
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*/
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r_pattern = ecc_xor_pats[j];
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if (is_rev1)
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w_pattern = ~r_pattern;
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else
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w_pattern = r_pattern;
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msg_printf(DBG|PRCPU, "ECC Ram - Writing 0x%x\n", r_pattern);
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/*
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* run current test patterns for all double words in the scache
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*/
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i = (uint) (SID_SIZE / (2 * sizeof(uint))); /*# dwords in scache*/
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way_size = i / 2; /* # dwords in 1 way of scache */
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fillptr = (uint *)PHYS_TO_K0(PHYS_CHECK_LO);
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while (i--)
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{
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*fillptr = 0; /* force cache load and modify */
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way = i / way_size;
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_write_cache_data(CACH_SD, (ulong)fillptr | way, (uint*)&tags,
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w_pattern);
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dummy = *fillptr; /* reload primary cache line */
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dummy2 = *(fillptr+1);
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/*
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* get ECC for selected dword by calling read_tag, which does
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* an indexed load tag cache op
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*/
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readin = _read_cache_data(CACH_SD, (ulong)fillptr | way,
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(uint*)&tags);
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if (readin != r_pattern) {
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/*
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* clean out the bad ECC pattern BEFORE calling errlog
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* or the exception handler goes off into the weeds . . .
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*/
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*fillptr = 0; /* cache load and modify */
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set_ecc(clear_pat); /* forces calculated ecc */
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pd_iwbinv((void *)fillptr); /* writeback to secondary */
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msg_printf(ERR|PRCPU,
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"Bad ECC at scache dword 0x%x - expected 0x%x, got 0x%x\n"
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"\tSRAM: %s\n",
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K0_TO_PHYS(fillptr), ip30_ssram_swizzle(r_pattern),
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ip30_ssram_swizzle(readin),
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ip30_ssram(fillptr,
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ip30_ssram_swizzle(readin),
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ip30_ssram_swizzle(r_pattern), cpuid()));
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fail = 1;
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break;
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}
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/*
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* next dword address
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*/
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fillptr += 2;
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}
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}
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/*
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* make sure that the caches and ecc register are clean
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*/
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set_ecc(0);
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invalidate_caches();
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/*
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* disable interrupts
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*/
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SetSR(cur_stat);
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return (fail);
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}
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/*
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* scache_ecc_intr - secondary cache ecc interrupt test
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*
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* all memory locations in the cache are set to the same values, so it
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* will not detect addressing errors well, but forces ECC single-bit errors
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* for every each bit in the ECC for every line in the secondary cache
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*/
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int scache_ecc_intr(void)
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{
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register uint *fillptr, d_pattern;
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uint fail, datacount, ecc_bshift;
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__psunsigned_t cur_err;
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volatile uint dummy;
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#if R10000
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struct tag_regs tags;
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int way;
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#endif
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fail = 0;
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#if R10000
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/* test all ways */
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for (way = 0; way < 2 ; way++) {
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#endif
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/*
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* make sure we start with the caches in a known state
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*/
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invalidate_caches();
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/*
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* start at the base of the scratch address area for each pattern
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*/
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fillptr = (uint *) PHYS_TO_K0(PHYS_CHECK_LO);
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/*
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* use each one of the data test patterns
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*/
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for (datacount = 0; datacount < NUM_DATA_PATS; datacount++)
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{
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d_pattern = data_pats[datacount];
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msg_printf(DBG|PRCPU, "Testing pattern 0x%x\n", d_pattern);
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/*
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* test each bit of scache ecc separately
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*/
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for (ecc_bshift = 0; ecc_bshift < 9; ecc_bshift++) {
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__psunsigned_t old_cache_err;
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/*
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* invalidate secondary cache (and primary dcache) so will
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* force refill - this should also work around the R4k
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* uncached writeback bug
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*/
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invalidate_dcache(PD_SIZE, PDL_SIZE);
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invalidate_scache(SID_SIZE, SIDL_SIZE);
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/*
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* store currently selected data pattern into primary
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* data cache
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*/
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old_cache_err = get_cache_err();
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*fillptr = d_pattern;
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if (old_cache_err != get_cache_err())
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fail = 1;
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/*
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* force the dirty data in the primary dcache back into the
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* secondary cache. Since the force bit is set in the status
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* register, the writeback will XOR the value in the ECC
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* register with the calculated ECC value
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*/
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if (setjmp(cache_fault_buf))
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{
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cur_err = get_cache_err(); /* get error status */
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/*
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* if cache error exception, but not ECC_DFIELD,
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* set error flag and log it
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*/
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if(!(cur_err & CACHERR_DC_D)) {
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msg_printf(ERR|PRCPU,
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"Did not get expected cache datafield error exception at 0x%08lx, CO_CACHE_ERR: 0x%08x\n",
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(void *) fillptr, cur_err);
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fail = 1;
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}
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/*
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* invalidate cache line
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*/
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sd_hitinv((void *)((ulong)fillptr|way));
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/*
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* load valid cache line
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*/
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dummy = *fillptr;
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/*
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* force ERET back to next address to clear exception
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*/
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DoErrorEret();
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/*
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* abort test after error
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*/
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if (fail)
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break;
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}
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else
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{
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nofault = cache_fault_buf;
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tags.tag_lo = d_pattern;
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tags.tag_hi = d_pattern;
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/*
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* enable interrupts for cache parity/ECC while
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* parity force is enabled
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*/
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SetSR (GetSR() & ~SR_DE);
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/* fool w/ ecc bits in 2ndary cache */
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_write_cache_data(CACH_SD, (ulong)fillptr|way, (uint*)&tags,
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~(1 << ecc_bshift));
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/* write to memory */
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sd_HWBINV((uint*)((ulong)fillptr|way));
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/*
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* read the data back into the primay dcache
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*/
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dummy = *fillptr;
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/*
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* if it won't take ECC exception in 10 uS, it ain't
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* gonna
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*/
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DELAY(10);
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/* NO CACHE ERROR - PRINT LOG MESSAGE */
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msg_printf(ERR|PRCPU,
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"Scache ECC - no exception for pattern 0x%x, ECC bit %d\n",
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d_pattern, ecc_bshift);
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fail = 1;
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break;
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}
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SetSR (GetSR() & ~SR_IEC);
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} /* END of ECC bitwalk loop */
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} /* END of data pattern loop */
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#if R10000
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} /* end of for way loop */
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#endif
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return fail;
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}
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